starfive-tech/linux.git/drivers/perf, branch VF2_v2.8.0

RISC-V: Support CPUID for risc-v in perf

2023-01-03T06:26:18+00:00

This patch creates the header.c file for the risc-v architecture and introduces support for PMU identification through sysfs. It is now possible to configure pmu-events in risc-v. Depends on patch [1], that introduces the id sysfs file. Signed-off-by: João Mário Domingos Signed-off-by: minda.chen

RISC-V: Create unique identification for SoC PMU

2023-01-03T06:26:18+00:00

The SBI PMU platform driver did not provide any identification for perf events matching. This patch introduces a new sysfs file inside the platform device (soc:pmu/id) for pmu identification. The identification is a 64-bit value generated as: [63-32]: mvendorid; [31]: marchid[MSB]; [30-16]: marchid[15-0]; [15-0]: mimpid[15MSBs]; The CSRs are detailed in the RISC-V privileged spec [1]. The marchid is split in MSB + 15LSBs, due to the MSB being used for open-source architecture identification. [1] https://github.com/riscv/riscv-isa-manual Signed-off-by: João Mário Domingos

RISC-V: Add sscofpmf extension support

2023-01-03T06:26:17+00:00

The sscofpmf extension allows counter overflow and filtering for programmable counters. Enable the perf driver to handle the overflow interrupt. The overflow interrupt is a hart local interrupt. Thus, per cpu overflow interrupts are setup as a child under the root INTC irq domain. Signed-off-by: Atish Patra Signed-off-by: Atish Patra

RISC-V: Add perf platform driver based on SBI PMU extension

2023-01-03T06:26:17+00:00

RISC-V SBI specification added a PMU extension that allows to configure start/stop any pmu counter. The RISC-V perf can use most of the generic perf features except interrupt overflow and event filtering based on privilege mode which will be added in future. It also allows to monitor a handful of firmware counters that can provide insights into firmware activity during a performance analysis. Signed-off-by: Atish Patra Signed-off-by: Atish Patra

RISC-V: Add a simple platform driver for RISC-V legacy perf

2023-01-03T06:26:17+00:00

The old RISC-V perf implementation allowed counting of only cycle/instruction counters using perf. Restore that feature by implementing a simple platform driver under a separate config to provide backward compatibility. Any existing software stack will continue to work as it is. However, it provides an easy way out in future where we can remove the legacy driver. Reviewed-by: Anup Patel Signed-off-by: Atish Patra Signed-off-by: Atish Patra

RISC-V: Add a perf core library for pmu drivers

2023-01-03T06:26:17+00:00

Implement a perf core library that can support all the essential perf features in future. It can also accommodate any type of PMU implementation in future. Currently, both SBI based perf driver and legacy driver implemented uses the library. Most of the common perf functionalities are kept in this core library wile PMU specific driver can implement PMU specific features. For example, the SBI specific functionality will be implemented in the SBI specific driver. Reviewed-by: Anup Patel Signed-off-by: Atish Patra Signed-off-by: Atish Patra

KVM: arm64: Fix PMU probe ordering

2021-09-20T11:43:34+00:00

Russell reported that since 5.13, KVM's probing of the PMU has started to fail on his HW. As it turns out, there is an implicit ordering dependency between the architectural PMU probing code and and KVM's own probing. If, due to probe ordering reasons, KVM probes before the PMU driver, it will fail to detect the PMU and prevent it from being advertised to guests as well as the VMM. Obviously, this is one probing too many, and we should be able to deal with any ordering. Add a callback from the PMU code into KVM to advertise the registration of a host CPU PMU, allowing for any probing order. Fixes: 5421db1be3b1 ("KVM: arm64: Divorce the perf code from oprofile helpers") Reported-by: "Russell King (Oracle)" Tested-by: Russell King (Oracle) Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/YUYRKVflRtUytzy5@shell.armlinux.org.uk Cc: stable@vger.kernel.org

drivers/perf: fix the missed ida_simple_remove() in ddr_perf_probe()

2021-06-17T18:45:24+00:00

ddr_perf_probe() misses to call ida_simple_remove() in an error path. Jump to cpuhp_state_err to fix it. Signed-off-by: Jing Xiangfeng Reviewed-by: Dong Aisheng Link: https://lore.kernel.org/r/20210617122614.166823-1-jingxiangfeng@huawei.com Signed-off-by: Will Deacon

perf/arm-cmn: Fix invalid pointer when access dtc object sharing the same IRQ number

2021-06-17T18:45:02+00:00

When multiple dtcs share the same IRQ number, the irq_friend which used to refer to dtc object gets calculated incorrect which leads to invalid pointer. Fixes: 0ba64770a2f2 ("perf: Add Arm CMN-600 PMU driver") Signed-off-by: Tuan Phan Reviewed-by: Robin Murphy Link: https://lore.kernel.org/r/1623946129-3290-1-git-send-email-tuanphan@os.amperecomputing.com Signed-off-by: Will Deacon

drivers/perf: Simplify EVENT ATTR macro in fsl_imx8_ddr_perf.c

2021-06-11T10:18:40+00:00

Use common macro PMU_EVENT_ATTR_ID to simplify IMX8_DDR_PMU_EVENT_ATTR Reviewed by Frank Li Cc: Frank Li Cc: Will Deacon Cc: Mark Rutland Signed-off-by: Qi Liu Link: https://lore.kernel.org/r/1623220863-58233-7-git-send-email-liuqi115@huawei.com Signed-off-by: Will Deacon