<feed xmlns='http://www.w3.org/2005/Atom'>
<title>starfive-tech/linux.git/drivers/mailbox, branch VF2_v2.5.0</title>
<subtitle>StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)</subtitle>
<id>https://git.radix-linux.su/starfive-tech/linux.git/atom?h=VF2_v2.5.0</id>
<link rel='self' href='https://git.radix-linux.su/starfive-tech/linux.git/atom?h=VF2_v2.5.0'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/'/>
<updated>2022-10-27T05:57:27+00:00</updated>
<entry>
<title>drive:mailbox:add pm ops</title>
<updated>2022-10-27T05:57:27+00:00</updated>
<author>
<name>ys</name>
<email>eason.xiong@starfivetech.com</email>
</author>
<published>2022-10-26T06:18:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=021fbb3bc3fa031d37c004d8d33f03d8cb31105c'/>
<id>urn:sha1:021fbb3bc3fa031d37c004d8d33f03d8cb31105c</id>
<content type='text'>
add runtime pm and system pm ops

Signed-off-by: ys &lt;eason.xiong@starfivetech.com&gt;
</content>
</entry>
<entry>
<title>mailbox:starfive: use clk/rst API.</title>
<updated>2022-04-26T06:06:03+00:00</updated>
<author>
<name>shanlong.li</name>
<email>shanlong.li@starfivetech.com</email>
</author>
<published>2022-04-25T11:29:36+00:00</published>
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<id>urn:sha1:2f5efd0235b4543672f8fba52e903480ed72de73</id>
<content type='text'>
1) use clk/rst api
2) fix coding style.

Signed-off-by: shanlong.li &lt;shanlong.li@starfivetech.com&gt;
</content>
</entry>
<entry>
<title>1.add mailbox driver; 2.add mailbox test driver.</title>
<updated>2022-01-13T10:32:53+00:00</updated>
<author>
<name>shanlong.li</name>
<email>shanlong.li@starfivetech.com</email>
</author>
<published>2022-01-13T10:32:53+00:00</published>
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<id>urn:sha1:e8f6d6996ea795c27cef02cb996041eccfb6020e</id>
<content type='text'>
</content>
</entry>
<entry>
<title>mailbox: cmdq: add multi-gce clocks support for mt8195</title>
<updated>2021-09-01T03:57:45+00:00</updated>
<author>
<name>jason-jh.lin</name>
<email>jason-jh.lin@mediatek.com</email>
</author>
<published>2021-08-31T07:09:03+00:00</published>
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<id>urn:sha1:85dfdbfc13ea9614a2168ce4a7d2cd089d84cb64</id>
<content type='text'>
For the design of GCE hardware event signal transportation,
evnet rx will send the event signal to all GCE event merges
after receiving the event signal from the other hardware.

Because GCE event merges need to response to event rx, their
clocks must be enabled at that time.

To make sure all the gce clock is enabled while receiving the
hardware event, each cmdq mailbox should enable or disable
the others gce clk at the same time.

Signed-off-by: jason-jh.lin &lt;jason-jh.lin@mediatek.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>mailbox: cmdq: add mediatek mailbox support for mt8195</title>
<updated>2021-09-01T03:57:39+00:00</updated>
<author>
<name>jason-jh.lin</name>
<email>jason-jh.lin@mediatek.com</email>
</author>
<published>2021-08-31T07:09:02+00:00</published>
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<id>urn:sha1:8d4f5a9e012abb7919f7b63656ea571f22789918</id>
<content type='text'>
Add mt8195 compatible name in the driver data of cmdq mailbox driver.

Signed-off-by: jason-jh.lin &lt;jason-jh.lin@mediatek.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>mailbox: qcom-apcs-ipc: Add compatible for MSM8953 SoC</title>
<updated>2021-08-30T05:29:29+00:00</updated>
<author>
<name>Vladimir Lypak</name>
<email>junak.pub@gmail.com</email>
</author>
<published>2021-08-10T16:44:33+00:00</published>
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<id>urn:sha1:e5c11ee3106072ef4b949eca93db160f55e6b55b</id>
<content type='text'>
MSM8953 has an APCS block similar to MSM8916 but with different clocks
which are spread over 2MB IO region next to it.

Signed-off-by: Vladimir Lypak &lt;junak.pub@gmail.com&gt;
Signed-off-by: Sireesh Kodali &lt;sireeshkodali@protonmail.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>mailbox: qcom: Add support for SM6115 APCS IPC</title>
<updated>2021-08-30T05:28:34+00:00</updated>
<author>
<name>Iskren Chernev</name>
<email>iskren.chernev@gmail.com</email>
</author>
<published>2021-06-27T18:58:28+00:00</published>
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<id>urn:sha1:dc2b8edfa3b3e691fa43694c4bd1e16b682393e1</id>
<content type='text'>
Qcom SM4250/6115, have APCS mailbox setup similar to msm8998 and
msm8916.

Signed-off-by: Iskren Chernev &lt;iskren.chernev@gmail.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: cmdq: add address shift in jump</title>
<updated>2021-08-30T05:21:38+00:00</updated>
<author>
<name>Yongqiang Niu</name>
<email>yongqiang.niu@mediatek.com</email>
</author>
<published>2021-08-02T07:52:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=8b60ed2b1674b78ebc433a11efa7d48821229037'/>
<id>urn:sha1:8b60ed2b1674b78ebc433a11efa7d48821229037</id>
<content type='text'>
Add address shift when compose jump instruction
to compatible with 35bit format.

Fixes: 0858fde496f8 ("mailbox: cmdq: variablize address shift in platform")
Signed-off-by: Yongqiang Niu &lt;yongqiang.niu@mediatek.com&gt;
Reviewed-by: Nicolas Boichat &lt;drinkcat@chromium.org&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>mailbox: cmdq: add mt8192 support</title>
<updated>2021-08-30T05:20:36+00:00</updated>
<author>
<name>Yongqiang Niu</name>
<email>yongqiang.niu@mediatek.com</email>
</author>
<published>2021-08-02T07:46:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=84fd4201b78b96f8d31f6a2624be27ad6306a9bc'/>
<id>urn:sha1:84fd4201b78b96f8d31f6a2624be27ad6306a9bc</id>
<content type='text'>
add mt8192 support

Signed-off-by: Yongqiang Niu &lt;yongqiang.niu@mediatek.com&gt;
Signed-off-by: Hsin-Yi Wang &lt;hsinyi@chromium.org&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>mailbox: qcom-ipcc: Enable loading QCOM_IPCC as a module</title>
<updated>2021-08-30T04:50:15+00:00</updated>
<author>
<name>Amit Pundir</name>
<email>amit.pundir@linaro.org</email>
</author>
<published>2021-07-16T07:49:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=8d7e5908c0bcf8a0abc437385e58e49abab11a93'/>
<id>urn:sha1:8d7e5908c0bcf8a0abc437385e58e49abab11a93</id>
<content type='text'>
This patch enables the qcom_ipcc driver to be loaded as a
module. IPCC is fairly core to system, so as such it should
never be unloaded. It registers as a mailbox + irq controller
and the irq controller drivers in kernel are not supposed to
be unloaded as they don't have the visibility over the clients
consuming the irqs. Hence adding supress_bind_attrs to disable
bind/unbind via sysfs.

Signed-off-by: Amit Pundir &lt;amit.pundir@linaro.org&gt;
Reviewed-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
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