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<title>starfive-tech/linux.git, branch rt-ethercat-release</title>
<subtitle>StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)</subtitle>
<id>https://git.radix-linux.su/starfive-tech/linux.git/atom?h=rt-ethercat-release</id>
<link rel='self' href='https://git.radix-linux.su/starfive-tech/linux.git/atom?h=rt-ethercat-release'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/'/>
<updated>2023-11-07T02:35:09+00:00</updated>
<entry>
<title>configs: vf2: set freq to max and set ethercat to module</title>
<updated>2023-11-07T02:35:09+00:00</updated>
<author>
<name>Minda Chen</name>
<email>minda.chen@starfivetech.com</email>
</author>
<published>2023-11-07T02:30:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=fd9ab6285a465cad773f8b48bc41946455460a58'/>
<id>urn:sha1:fd9ab6285a465cad773f8b48bc41946455460a58</id>
<content type='text'>
Set defualt to max frequeuce to set latency to minium.
Alse disable cpu idle and hibernation pm ops.

etercat module module install sequence

modprobe phylink
insmod ec_master.ko main_devices=&lt;ethercat gmac mac address&gt;
insmod ec_generic.ko
modprobe pcs_xpcs

cd /lib/modules/5.15.0-rt17+/kernel/drivers/net/ethernet/stmicro/stmmac/
insmod stmmac.ko
insmod stmmac-platform.ko
insmod dwmac-starfive-plat.ko

mac address example:
insmod ec_master.ko main_devices=6c:cf:39:00:27:48

Signed-off-by: Minda Chen &lt;minda.chen@starfivetech.com&gt;
</content>
</entry>
<entry>
<title>stmmac: add ethercat support</title>
<updated>2023-11-07T02:30:17+00:00</updated>
<author>
<name>Minda Chen</name>
<email>minda.chen@starfivetech.com</email>
</author>
<published>2023-11-07T02:30:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=985df375a65f2338127f1b2a0ba032a3ca7a5111'/>
<id>urn:sha1:985df375a65f2338127f1b2a0ba032a3ca7a5111</id>
<content type='text'>
Signed-off-by: Minda Chen &lt;minda.chen@starfivetech.com&gt;
</content>
</entry>
<entry>
<title>add ethercat codes.</title>
<updated>2023-11-06T11:47:35+00:00</updated>
<author>
<name>Minda Chen</name>
<email>minda.chen@starfivetech.com</email>
</author>
<published>2023-06-27T12:23:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=c606d37f6e41251c0de22144f07d2d0c17e96cd4'/>
<id>urn:sha1:c606d37f6e41251c0de22144f07d2d0c17e96cd4</id>
<content type='text'>
Signed-off-by: Minda Chen &lt;minda.chen@starfivetech.com&gt;
</content>
</entry>
<entry>
<title>cpupri: a work around for non-rt test panic</title>
<updated>2023-11-06T11:36:13+00:00</updated>
<author>
<name>Minda Chen</name>
<email>minda.chen@starfivetech.com</email>
</author>
<published>2023-10-26T08:46:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=5322763afa20323701d14a95e2e07a5db3ae48b7'/>
<id>urn:sha1:5322763afa20323701d14a95e2e07a5db3ae48b7</id>
<content type='text'>
kernel BUG at kernel/sched/cpupri.c:151!
The same issue can be seen in link.
https://www.spinics.net/lists/kernel/msg4184866.html

Signed-off-by: Minda Chen &lt;minda.chen@starfivetech.com&gt;
</content>
</entry>
<entry>
<title>riscv: rt: add riscv lazy preempt support.</title>
<updated>2023-11-06T11:36:10+00:00</updated>
<author>
<name>minda.chen</name>
<email>minda.chen@starfivetech.com</email>
</author>
<published>2023-02-10T06:31:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=5cbe44ac9b1fe85bf136c197de241e084cc16d4b'/>
<id>urn:sha1:5cbe44ac9b1fe85bf136c197de241e084cc16d4b</id>
<content type='text'>
The code is origin from arm64/x86

Signed-off-by: Minda Chen &lt;minda.chen@starfivetech.com&gt;
</content>
</entry>
<entry>
<title>config: add vf2 PREEMPT_RT and other config</title>
<updated>2023-11-06T11:31:56+00:00</updated>
<author>
<name>Minda Chen</name>
<email>minda.chen@starfivetech.com</email>
</author>
<published>2023-11-06T11:30:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=fce1b5db665835470a1ff6074130c1eed18119a0'/>
<id>urn:sha1:fce1b5db665835470a1ff6074130c1eed18119a0</id>
<content type='text'>
enable full preempt RT config.
Set HZ 1000 and set no tickless

Signed-off-by: Minda Chen &lt;minda.chen@starfivetech.com&gt;
</content>
</entry>
<entry>
<title>riscv: Allow riscv PREEMPT_RT config.</title>
<updated>2023-11-06T11:25:49+00:00</updated>
<author>
<name>minda.chen</name>
<email>minda.chen@starfivetech.com</email>
</author>
<published>2023-02-06T08:00:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=f1932562a807f6ab0639e4cf38ce4b5d9819c529'/>
<id>urn:sha1:f1932562a807f6ab0639e4cf38ce4b5d9819c529</id>
<content type='text'>
RISCV allow to select RT

Signed-off-by: minda.chen &lt;minda.chen@starfivetech.com&gt;
</content>
</entry>
<entry>
<title>POWERPC: Allow to enable RT</title>
<updated>2023-11-06T11:24:53+00:00</updated>
<author>
<name>Sebastian Andrzej Siewior</name>
<email>bigeasy@linutronix.de</email>
</author>
<published>2019-10-11T11:14:41+00:00</published>
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<id>urn:sha1:ac5d2d77f46733f06f223fcd3df7218f9d61048d</id>
<content type='text'>
Allow to select RT.

Signed-off-by: Sebastian Andrzej Siewior &lt;bigeasy@linutronix.de&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</content>
</entry>
<entry>
<title>powerpc/stackprotector: work around stack-guard init from atomic</title>
<updated>2023-11-06T11:24:53+00:00</updated>
<author>
<name>Sebastian Andrzej Siewior</name>
<email>bigeasy@linutronix.de</email>
</author>
<published>2019-03-26T17:31:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=6156a09a45d7fbacc22f5380ed2bbc35de718602'/>
<id>urn:sha1:6156a09a45d7fbacc22f5380ed2bbc35de718602</id>
<content type='text'>
This is invoked from the secondary CPU in atomic context. On x86 we use
tsc instead. On Power we XOR it against mftb() so lets use stack address
as the initial value.

Cc: stable-rt@vger.kernel.org
Signed-off-by: Sebastian Andrzej Siewior &lt;bigeasy@linutronix.de&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</content>
</entry>
<entry>
<title>powerpc/kvm: Disable in-kernel MPIC emulation for PREEMPT_RT</title>
<updated>2023-11-06T11:24:53+00:00</updated>
<author>
<name>Bogdan Purcareata</name>
<email>bogdan.purcareata@freescale.com</email>
</author>
<published>2015-04-24T15:53:13+00:00</published>
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<id>urn:sha1:e5786f65d0ad1855d6f53760c5720d9524838e80</id>
<content type='text'>
While converting the openpic emulation code to use a raw_spinlock_t enables
guests to run on RT, there's still a performance issue. For interrupts sent in
directed delivery mode with a multiple CPU mask, the emulated openpic will loop
through all of the VCPUs, and for each VCPUs, it call IRQ_check, which will loop
through all the pending interrupts for that VCPU. This is done while holding the
raw_lock, meaning that in all this time the interrupts and preemption are
disabled on the host Linux. A malicious user app can max both these number and
cause a DoS.

This temporary fix is sent for two reasons. First is so that users who want to
use the in-kernel MPIC emulation are aware of the potential latencies, thus
making sure that the hardware MPIC and their usage scenario does not involve
interrupts sent in directed delivery mode, and the number of possible pending
interrupts is kept small. Secondly, this should incentivize the development of a
proper openpic emulation that would be better suited for RT.

Acked-by: Scott Wood &lt;scottwood@freescale.com&gt;
Signed-off-by: Bogdan Purcareata &lt;bogdan.purcareata@freescale.com&gt;
Signed-off-by: Sebastian Andrzej Siewior &lt;bigeasy@linutronix.de&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</content>
</entry>
</feed>
