blob: 754c54a6eb06a46dafeeb030df71dc6b96c16866 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
|
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a779g0 CPG Core Clocks */
#define R8A779G0_CLK_ZX 0
#define R8A779G0_CLK_ZS 1
#define R8A779G0_CLK_ZT 2
#define R8A779G0_CLK_ZTR 3
#define R8A779G0_CLK_S0D2 4
#define R8A779G0_CLK_S0D3 5
#define R8A779G0_CLK_S0D4 6
#define R8A779G0_CLK_S0D1_VIO 7
#define R8A779G0_CLK_S0D2_VIO 8
#define R8A779G0_CLK_S0D4_VIO 9
#define R8A779G0_CLK_S0D8_VIO 10
#define R8A779G0_CLK_S0D1_VC 11
#define R8A779G0_CLK_S0D2_VC 12
#define R8A779G0_CLK_S0D4_VC 13
#define R8A779G0_CLK_S0D2_MM 14
#define R8A779G0_CLK_S0D4_MM 15
#define R8A779G0_CLK_S0D2_U3DG 16
#define R8A779G0_CLK_S0D4_U3DG 17
#define R8A779G0_CLK_S0D2_RT 18
#define R8A779G0_CLK_S0D3_RT 19
#define R8A779G0_CLK_S0D4_RT 20
#define R8A779G0_CLK_S0D6_RT 21
#define R8A779G0_CLK_S0D24_RT 22
#define R8A779G0_CLK_S0D2_PER 23
#define R8A779G0_CLK_S0D3_PER 24
#define R8A779G0_CLK_S0D4_PER 25
#define R8A779G0_CLK_S0D6_PER 26
#define R8A779G0_CLK_S0D12_PER 27
#define R8A779G0_CLK_S0D24_PER 28
#define R8A779G0_CLK_S0D1_HSC 29
#define R8A779G0_CLK_S0D2_HSC 30
#define R8A779G0_CLK_S0D4_HSC 31
#define R8A779G0_CLK_S0D2_CC 32
#define R8A779G0_CLK_SVD1_IR 33
#define R8A779G0_CLK_SVD2_IR 34
#define R8A779G0_CLK_SVD1_VIP 35
#define R8A779G0_CLK_SVD2_VIP 36
#define R8A779G0_CLK_CL 37
#define R8A779G0_CLK_CL16M 38
#define R8A779G0_CLK_CL16M_MM 39
#define R8A779G0_CLK_CL16M_RT 40
#define R8A779G0_CLK_CL16M_PER 41
#define R8A779G0_CLK_CL16M_HSC 42
#define R8A779G0_CLK_Z0 43
#define R8A779G0_CLK_ZB3 44
#define R8A779G0_CLK_ZB3D2 45
#define R8A779G0_CLK_ZB3D4 46
#define R8A779G0_CLK_ZG 47
#define R8A779G0_CLK_SD0H 48
#define R8A779G0_CLK_SD0 49
#define R8A779G0_CLK_RPC 50
#define R8A779G0_CLK_RPCD2 51
#define R8A779G0_CLK_MSO 52
#define R8A779G0_CLK_CANFD 53
#define R8A779G0_CLK_CSI 54
#define R8A779G0_CLK_FRAY 55
#define R8A779G0_CLK_IPC 56
#define R8A779G0_CLK_SASYNCRT 57
#define R8A779G0_CLK_SASYNCPERD1 58
#define R8A779G0_CLK_SASYNCPERD2 59
#define R8A779G0_CLK_SASYNCPERD4 60
#define R8A779G0_CLK_VIOBUS 61
#define R8A779G0_CLK_VIOBUSD2 62
#define R8A779G0_CLK_VCBUS 63
#define R8A779G0_CLK_VCBUSD2 64
#define R8A779G0_CLK_DSIEXT 65
#define R8A779G0_CLK_DSIREF 66
#define R8A779G0_CLK_ADGH 67
#define R8A779G0_CLK_OSC 68
#define R8A779G0_CLK_ZR0 69
#define R8A779G0_CLK_ZR1 70
#define R8A779G0_CLK_ZR2 71
#define R8A779G0_CLK_IMPA 72
#define R8A779G0_CLK_IMPAD4 73
#define R8A779G0_CLK_CPEX 74
#define R8A779G0_CLK_CBFUSA 75
#define R8A779G0_CLK_R 76
#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */
|
