1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
|
/*
* CARMA Board DATA-FPGA Programmer
*
* Copyright (c) 2009-2011 Ira W. Snyder <iws@ovro.caltech.edu>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/dma-mapping.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/completion.h>
#include <linux/miscdevice.h>
#include <linux/dmaengine.h>
#include <linux/fsldma.h>
#include <linux/interrupt.h>
#include <linux/highmem.h>
#include <linux/vmalloc.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/leds.h>
#include <linux/slab.h>
#include <linux/kref.h>
#include <linux/fs.h>
#include <linux/io.h>
/* MPC8349EMDS specific get_immrbase() */
#include <sysdev/fsl_soc.h>
static const char drv_name[] = "carma-fpga-program";
/*
* Firmware images are always this exact size
*
* 12849552 bytes for a CARMA Digitizer Board (EP2S90 FPGAs)
* 18662880 bytes for a CARMA Correlator Board (EP2S130 FPGAs)
*/
#define FW_SIZE_EP2S90 12849552
#define FW_SIZE_EP2S130 18662880
struct fpga_dev {
struct miscdevice miscdev;
/* Reference count */
struct kref ref;
/* Device Registers */
struct device *dev;
void __iomem *regs;
void __iomem *immr;
/* Freescale DMA Device */
struct dma_chan *chan;
/* Interrupts */
int irq, status;
struct completion completion;
/* FPGA Bitfile */
struct mutex lock;
void *vaddr;
struct scatterlist *sglist;
int sglen;
int nr_pages;
bool buf_allocated;
/* max size and written bytes */
size_t fw_size;
size_t bytes;
};
static int fpga_dma_init(struct fpga_dev *priv, int nr_pages)
{
struct page *pg;
int i;
priv->vaddr = vmalloc_32(nr_pages << PAGE_SHIFT);
if (NULL == priv->vaddr) {
pr_debug("vmalloc_32(%d pages) failed\n", nr_pages);
return -ENOMEM;
}
pr_debug("vmalloc is at addr 0x%08lx, size=%d\n",
(unsigned long)priv->vaddr,
nr_pages << PAGE_SHIFT);
memset(priv->vaddr, 0, nr_pages << PAGE_SHIFT);
priv->nr_pages = nr_pages;
priv->sglist = vzalloc(priv->nr_pages * sizeof(*priv->sglist));
if (NULL == priv->sglist)
goto vzalloc_err;
sg_init_table(priv->sglist, priv->nr_pages);
for (i = 0; i < priv->nr_pages; i++) {
pg = vmalloc_to_page(priv->vaddr + i * PAGE_SIZE);
if (NULL == pg)
goto vmalloc_to_page_err;
sg_set_page(&priv->sglist[i], pg, PAGE_SIZE, 0);
}
return 0;
vmalloc_to_page_err:
vfree(priv->sglist);
priv->sglist = NULL;
vzalloc_err:
vfree(priv->vaddr);
priv->vaddr = NULL;
return -ENOMEM;
}
static int fpga_dma_map(struct fpga_dev *priv)
{
priv->sglen = dma_map_sg(priv->dev, priv->sglist,
priv->nr_pages, DMA_TO_DEVICE);
if (0 == priv->sglen) {
pr_warn("%s: dma_map_sg failed\n", __func__);
return -ENOMEM;
}
return 0;
}
static int fpga_dma_unmap(struct fpga_dev *priv)
{
if (!priv->sglen)
return 0;
dma_unmap_sg(priv->dev, priv->sglist, priv->sglen, DMA_TO_DEVICE);
priv->sglen = 0;
return 0;
}
/*
* FPGA Bitfile Helpers
*/
/**
* fpga_drop_firmware_data() - drop the bitfile image from memory
* @priv: the driver's private data structure
*
* LOCKING: must hold priv->lock
*/
static void fpga_drop_firmware_data(struct fpga_dev *priv)
{
vfree(priv->sglist);
vfree(priv->vaddr);
priv->buf_allocated = false;
priv->bytes = 0;
}
/*
* Private Data Reference Count
*/
static void fpga_dev_remove(struct kref *ref)
{
struct fpga_dev *priv = container_of(ref, struct fpga_dev, ref);
/* free any firmware image that was not programmed */
fpga_drop_firmware_data(priv);
mutex_destroy(&priv->lock);
kfree(priv);
}
/*
* LED Trigger (could be a seperate module)
*/
/*
* NOTE: this whole thing does have the problem that whenever the led's are
* NOTE: first set to use the fpga trigger, they could be in the wrong state
*/
DEFINE_LED_TRIGGER(ledtrig_fpga);
static void ledtrig_fpga_programmed(bool enabled)
{
if (enabled)
led_trigger_event(ledtrig_fpga, LED_FULL);
else
led_trigger_event(ledtrig_fpga, LED_OFF);
}
/*
* FPGA Register Helpers
*/
/* Register Definitions */
#define FPGA_CONFIG_CONTROL 0x40
#define FPGA_CONFIG_STATUS 0x44
#define FPGA_CONFIG_FIFO_SIZE 0x48
#define FPGA_CONFIG_FIFO_USED 0x4C
#define FPGA_CONFIG_TOTAL_BYTE_COUNT 0x50
#define FPGA_CONFIG_CUR_BYTE_COUNT 0x54
#define FPGA_FIFO_ADDRESS 0x3000
static int fpga_fifo_size(void __iomem *regs)
{
return ioread32be(regs + FPGA_CONFIG_FIFO_SIZE);
}
#define CFG_STATUS_ERR_MASK 0xfffe
static int fpga_config_error(void __iomem *regs)
{
return ioread32be(regs + FPGA_CONFIG_STATUS) & CFG_STATUS_ERR_MASK;
}
static int fpga_fifo_empty(void __iomem *regs)
{
return ioread32be(regs + FPGA_CONFIG_FIFO_USED) == 0;
}
static void fpga_fifo_write(void __iomem *regs, u32 val)
{
iowrite32be(val, regs + FPGA_FIFO_ADDRESS);
}
static void fpga_set_byte_count(void __iomem *regs, u32 count)
{
iowrite32be(count, regs + FPGA_CONFIG_TOTAL_BYTE_COUNT);
}
#define CFG_CTL_ENABLE (1 << 0)
#define CFG_CTL_RESET (1 << 1)
#define CFG_CTL_DMA (1 << 2)
static void fpga_programmer_enable(struct fpga_dev *priv, bool dma)
{
u32 val;
val = (dma) ? (CFG_CTL_ENABLE | CFG_CTL_DMA) : CFG_CTL_ENABLE;
iowrite32be(val, priv->regs + FPGA_CONFIG_CONTROL);
}
static void fpga_programmer_disable(struct fpga_dev *priv)
{
iowrite32be(0x0, priv->regs + FPGA_CONFIG_CONTROL);
}
static void fpga_dump_registers(struct fpga_dev *priv)
{
u32 control, status, size, used, total, curr;
/* good status: do nothing */
if (priv->status == 0)
return;
/* Dump all status registers */
control = ioread32be(priv->regs + FPGA_CONFIG_CONTROL);
status = ioread32be(priv->regs + FPGA_CONFIG_STATUS);
size = ioread32be(priv->regs + FPGA_CONFIG_FIFO_SIZE);
used = ioread32be(priv->regs + FPGA_CONFIG_FIFO_USED);
total = ioread32be(priv->regs + FPGA_CONFIG_TOTAL_BYTE_COUNT);
curr = ioread32be(priv->regs + FPGA_CONFIG_CUR_BYTE_COUNT);
dev_err(priv->dev, "Configuration failed, dumping status registers\n");
dev_err(priv->dev, "Control: 0x%.8x\n", control);
dev_err(priv->dev, "Status: 0x%.8x\n", status);
dev_err(priv->dev, "FIFO Size: 0x%.8x\n", size);
dev_err(priv->dev, "FIFO Used: 0x%.8x\n", used);
dev_err(priv->dev, "FIFO Total: 0x%.8x\n", total);
dev_err(priv->dev, "FIFO Curr: 0x%.8x\n", curr);
}
/*
* FPGA Power Supply Code
*/
#define CTL_PWR_CONTROL 0x2006
#define CTL_PWR_STATUS 0x200A
#define CTL_PWR_FAIL 0x200B
#define PWR_CONTROL_ENABLE 0x01
#define PWR_STATUS_ERROR_MASK 0x10
#define PWR_STATUS_GOOD 0x0f
/*
* Determine if the FPGA power is good for all supplies
*/
static bool fpga_power_good(struct fpga_dev *priv)
{
u8 val;
val = ioread8(priv->regs + CTL_PWR_STATUS);
if (val & PWR_STATUS_ERROR_MASK)
return false;
return val == PWR_STATUS_GOOD;
}
/*
* Disable the FPGA power supplies
*/
static void fpga_disable_power_supplies(struct fpga_dev *priv)
{
unsigned long start;
u8 val;
iowrite8(0x0, priv->regs + CTL_PWR_CONTROL);
/*
* Wait 500ms for the power rails to discharge
*
* Without this delay, the CTL-CPLD state machine can get into a
* state where it is waiting for the power-goods to assert, but they
* never do. This only happens when enabling and disabling the
* power sequencer very rapidly.
*
* The loop below will also wait for the power goods to de-assert,
* but testing has shown that they are always disabled by the time
* the sleep completes. However, omitting the sleep and only waiting
* for the power-goods to de-assert was not sufficient to ensure
* that the power sequencer would not wedge itself.
*/
msleep(500);
start = jiffies;
while (time_before(jiffies, start + HZ)) {
val = ioread8(priv->regs + CTL_PWR_STATUS);
if (!(val & PWR_STATUS_GOOD))
break;
usleep_range(5000, 10000);
}
val = ioread8(priv->regs + CTL_PWR_STATUS);
if (val & PWR_STATUS_GOOD) {
dev_err(priv->dev, "power disable failed: "
"power goods: status 0x%.2x\n", val);
}
if (val & PWR_STATUS_ERROR_MASK) {
dev_err(priv->dev, "power disable failed: "
"alarm bit set: status 0x%.2x\n", val);
}
}
/**
* fpga_enable_power_supplies() - enable the DATA-FPGA power supplies
* @priv: the driver's private data structure
*
* Enable the DATA-FPGA power supplies, waiting up to 1 second for
* them to enable successfully.
*
* Returns 0 on success, -ERRNO otherwise
*/
static int fpga_enable_power_supplies(struct fpga_dev *priv)
{
unsigned long start = jiffies;
if (fpga_power_good(priv)) {
dev_dbg(priv->dev, "power was already good\n");
return 0;
}
iowrite8(PWR_CONTROL_ENABLE, priv->regs + CTL_PWR_CONTROL);
while (time_before(jiffies, start + HZ)) {
if (fpga_power_good(priv))
return 0;
usleep_range(5000, 10000);
}
return fpga_power_good(priv) ? 0 : -ETIMEDOUT;
}
/*
* Determine if the FPGA power supplies are all enabled
*/
static bool fpga_power_enabled(struct fpga_dev *priv)
{
u8 val;
val = ioread8(priv->regs + CTL_PWR_CONTROL);
if (val & PWR_CONTROL_ENABLE)
return true;
return false;
}
/*
* Determine if the FPGA's are programmed and running correctly
*/
static bool fpga_running(struct fpga_dev *priv)
{
if (!fpga_power_good(priv))
return false;
/* Check the config done bit */
return ioread32be(priv->regs + FPGA_CONFIG_STATUS) & (1 << 18);
}
/*
* FPGA Programming Code
*/
/**
* fpga_program_block() - put a block of data into the programmer's FIFO
* @priv: the driver's private data structure
* @buf: the data to program
* @count: the length of data to program (must be a multiple of 4 bytes)
*
* Returns 0 on success, -ERRNO otherwise
*/
static int fpga_program_block(struct fpga_dev *priv, void *buf, size_t count)
{
u32 *data = buf;
int size = fpga_fifo_size(priv->regs);
int i, len;
unsigned long timeout;
/* enforce correct data length for the FIFO */
BUG_ON(count % 4 != 0);
while (count > 0) {
/* Get the size of the block to write (maximum is FIFO_SIZE) */
len = min_t(size_t, count, size);
timeout = jiffies + HZ / 4;
/* Write the block */
for (i = 0; i < len / 4; i++)
fpga_fifo_write(priv->regs, data[i]);
/* Update the amounts left */
count -= len;
data += len / 4;
/* Wait for the fifo to empty */
while (true) {
if (fpga_fifo_empty(priv->regs)) {
break;
} else {
dev_dbg(priv->dev, "Fifo not empty\n");
cpu_relax();
}
if (fpga_config_error(priv->regs)) {
dev_err(priv->dev, "Error detected\n");
return -EIO;
}
if (time_after(jiffies, timeout)) {
dev_err(priv->dev, "Fifo drain timeout\n");
return -ETIMEDOUT;
}
usleep_range(5000, 10000);
}
}
return 0;
}
/**
* fpga_program_cpu() - program the DATA-FPGA's using the CPU
* @priv: the driver's private data structure
*
* This is useful when the DMA programming method fails. It is possible to
* wedge the Freescale DMA controller such that the DMA programming method
* always fails. This method has always succeeded.
*
* Returns 0 on success, -ERRNO otherwise
*/
static noinline int fpga_program_cpu(struct fpga_dev *priv)
{
int ret;
/* Disable the programmer */
fpga_programmer_disable(priv);
/* Set the total byte count */
fpga_set_byte_count(priv->regs, priv->bytes);
dev_dbg(priv->dev, "total byte count %u bytes\n", priv->bytes);
/* Enable the controller for programming */
fpga_programmer_enable(priv, false);
dev_dbg(priv->dev, "enabled the controller\n");
/* Write each chunk of the FPGA bitfile to FPGA programmer */
ret = fpga_program_block(priv, priv->vaddr, priv->bytes);
if (ret)
goto out_disable_controller;
/* Wait for the interrupt handler to signal that programming finished */
ret = wait_for_completion_timeout(&priv->completion, 2 * HZ);
if (!ret) {
dev_err(priv->dev, "Timed out waiting for completion\n");
ret = -ETIMEDOUT;
goto out_disable_controller;
}
/* Retrieve the status from the interrupt handler */
ret = priv->status;
out_disable_controller:
fpga_programmer_disable(priv);
return ret;
}
#define FIFO_DMA_ADDRESS 0xf0003000
#define FIFO_MAX_LEN 4096
/**
* fpga_program_dma() - program the DATA-FPGA's using the DMA engine
* @priv: the driver's private data structure
*
* Program the DATA-FPGA's using the Freescale DMA engine. This requires that
* the engine is programmed such that the hardware DMA request lines can
* control the entire DMA transaction. The system controller FPGA then
* completely offloads the programming from the CPU.
*
* Returns 0 on success, -ERRNO otherwise
*/
static noinline int fpga_program_dma(struct fpga_dev *priv)
{
struct dma_chan *chan = priv->chan;
struct dma_async_tx_descriptor *tx;
size_t num_pages, len, avail = 0;
struct dma_slave_config config;
struct scatterlist *sg;
struct sg_table table;
dma_cookie_t cookie;
int ret, i;
/* Disable the programmer */
fpga_programmer_disable(priv);
/* Allocate a scatterlist for the DMA destination */
num_pages = DIV_ROUND_UP(priv->bytes, FIFO_MAX_LEN);
ret = sg_alloc_table(&table, num_pages, GFP_KERNEL);
if (ret) {
dev_err(priv->dev, "Unable to allocate dst scatterlist\n");
ret = -ENOMEM;
goto out_return;
}
/*
* This is an ugly hack
*
* We fill in a scatterlist as if it were mapped for DMA. This is
* necessary because there exists no better structure for this
* inside the kernel code.
*
* As an added bonus, we can use the DMAEngine API for all of this,
* rather than inventing another extremely similar API.
*/
avail = priv->bytes;
for_each_sg(table.sgl, sg, num_pages, i) {
len = min_t(size_t, avail, FIFO_MAX_LEN);
sg_dma_address(sg) = FIFO_DMA_ADDRESS;
sg_dma_len(sg) = len;
avail -= len;
}
/* Map the buffer for DMA */
ret = fpga_dma_map(priv);
if (ret) {
dev_err(priv->dev, "Unable to map buffer for DMA\n");
goto out_free_table;
}
/*
* Configure the DMA channel to transfer FIFO_SIZE / 2 bytes per
* transaction, and then put it under external control
*/
memset(&config, 0, sizeof(config));
config.direction = DMA_MEM_TO_DEV;
config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
config.dst_maxburst = fpga_fifo_size(priv->regs) / 2 / 4;
ret = dmaengine_slave_config(chan, &config);
if (ret) {
dev_err(priv->dev, "DMA slave configuration failed\n");
goto out_dma_unmap;
}
ret = fsl_dma_external_start(chan, 1);
if (ret) {
dev_err(priv->dev, "DMA external control setup failed\n");
goto out_dma_unmap;
}
/* setup and submit the DMA transaction */
tx = dmaengine_prep_dma_sg(chan, table.sgl, num_pages,
priv->sglist, priv->sglen, 0);
if (!tx) {
dev_err(priv->dev, "Unable to prep DMA transaction\n");
ret = -ENOMEM;
goto out_dma_unmap;
}
cookie = tx->tx_submit(tx);
if (dma_submit_error(cookie)) {
dev_err(priv->dev, "Unable to submit DMA transaction\n");
ret = -ENOMEM;
goto out_dma_unmap;
}
dma_async_issue_pending(chan);
/* Set the total byte count */
fpga_set_byte_count(priv->regs, priv->bytes);
dev_dbg(priv->dev, "total byte count %u bytes\n", priv->bytes);
/* Enable the controller for DMA programming */
fpga_programmer_enable(priv, true);
dev_dbg(priv->dev, "enabled the controller\n");
/* Wait for the interrupt handler to signal that programming finished */
ret = wait_for_completion_timeout(&priv->completion, 2 * HZ);
if (!ret) {
dev_err(priv->dev, "Timed out waiting for completion\n");
ret = -ETIMEDOUT;
goto out_disable_controller;
}
/* Retrieve the status from the interrupt handler */
ret = priv->status;
out_disable_controller:
fpga_programmer_disable(priv);
out_dma_unmap:
fpga_dma_unmap(priv);
out_free_table:
sg_free_table(&table);
out_return:
return ret;
}
/*
* Interrupt Handling
*/
static irqreturn_t fpga_irq(int irq, void *dev_id)
{
struct fpga_dev *priv = dev_id;
/* Save the status */
priv->status = fpga_config_error(priv->regs) ? -EIO : 0;
dev_dbg(priv->dev, "INTERRUPT status %d\n", priv->status);
fpga_dump_registers(priv);
/* Disabling the programmer clears the interrupt */
fpga_programmer_disable(priv);
/* Notify any waiters */
complete(&priv->completion);
return IRQ_HANDLED;
}
/*
* SYSFS Helpers
*/
/**
* fpga_do_stop() - deconfigure (reset) the DATA-FPGA's
* @priv: the driver's private data structure
*
* LOCKING: must hold priv->lock
*/
static int fpga_do_stop(struct fpga_dev *priv)
{
u32 val;
/* Set the led to unprogrammed */
ledtrig_fpga_programmed(false);
/* Pulse the config line to reset the FPGA's */
val = CFG_CTL_ENABLE | CFG_CTL_RESET;
iowrite32be(val, priv->regs + FPGA_CONFIG_CONTROL);
iowrite32be(0x0, priv->regs + FPGA_CONFIG_CONTROL);
return 0;
}
static noinline int fpga_do_program(struct fpga_dev *priv)
{
int ret;
if (priv->bytes != priv->fw_size) {
dev_err(priv->dev, "Incorrect bitfile size: got %zu bytes, "
"should be %zu bytes\n",
priv->bytes, priv->fw_size);
return -EINVAL;
}
if (!fpga_power_enabled(priv)) {
dev_err(priv->dev, "Power not enabled\n");
return -EINVAL;
}
if (!fpga_power_good(priv)) {
dev_err(priv->dev, "Power not good\n");
return -EINVAL;
}
/* Set the LED to unprogrammed */
ledtrig_fpga_programmed(false);
/* Try to program the FPGA's using DMA */
ret = fpga_program_dma(priv);
/* If DMA failed or doesn't exist, try with CPU */
if (ret) {
dev_warn(priv->dev, "Falling back to CPU programming\n");
ret = fpga_program_cpu(priv);
}
if (ret) {
dev_err(priv->dev, "Unable to program FPGA's\n");
return ret;
}
/* Drop the firmware bitfile from memory */
fpga_drop_firmware_data(priv);
dev_dbg(priv->dev, "FPGA programming successful\n");
ledtrig_fpga_programmed(true);
return 0;
}
/*
* File Operations
*/
static int fpga_open(struct inode *inode, struct file *filp)
{
/*
* The miscdevice layer puts our struct miscdevice into the
* filp->private_data field. We use this to find our private
* data and then overwrite it with our own private structure.
*/
struct fpga_dev *priv = container_of(filp->private_data,
struct fpga_dev, miscdev);
unsigned int nr_pages;
int ret;
/* We only allow one process at a time */
ret = mutex_lock_interruptible(&priv->lock);
if (ret)
return ret;
filp->private_data = priv;
kref_get(&priv->ref);
/* Truncation: drop any existing data */
if (filp->f_flags & O_TRUNC)
priv->bytes = 0;
/* Check if we have already allocated a buffer */
if (priv->buf_allocated)
return 0;
/* Allocate a buffer to hold enough data for the bitfile */
nr_pages = DIV_ROUND_UP(priv->fw_size, PAGE_SIZE);
ret = fpga_dma_init(priv, nr_pages);
if (ret) {
dev_err(priv->dev, "unable to allocate data buffer\n");
mutex_unlock(&priv->lock);
kref_put(&priv->ref, fpga_dev_remove);
return ret;
}
priv->buf_allocated = true;
return 0;
}
static int fpga_release(struct inode *inode, struct file *filp)
{
struct fpga_dev *priv = filp->private_data;
mutex_unlock(&priv->lock);
kref_put(&priv->ref, fpga_dev_remove);
return 0;
}
static ssize_t fpga_write(struct file *filp, const char __user *buf,
size_t count, loff_t *f_pos)
{
struct fpga_dev *priv = filp->private_data;
/* FPGA bitfiles have an exact size: disallow anything else */
if (priv->bytes >= priv->fw_size)
return -ENOSPC;
count = min_t(size_t, priv->fw_size - priv->bytes, count);
if (copy_from_user(priv->vaddr + priv->bytes, buf, count))
return -EFAULT;
priv->bytes += count;
return count;
}
static ssize_t fpga_read(struct file *filp, char __user *buf, size_t count,
loff_t *f_pos)
{
struct fpga_dev *priv = filp->private_data;
return simple_read_from_buffer(buf, count, f_pos,
priv->vaddr, priv->bytes);
}
static loff_t fpga_llseek(struct file *filp, loff_t offset, int origin)
{
struct fpga_dev *priv = filp->private_data;
/* only read-only opens are allowed to seek */
if ((filp->f_flags & O_ACCMODE) != O_RDONLY)
return -EINVAL;
return fixed_size_llseek(filp, offset, origin, priv->fw_size);
}
static const struct file_operations fpga_fops = {
.open = fpga_open,
.release = fpga_release,
.write = fpga_write,
.read = fpga_read,
.llseek = fpga_llseek,
};
/*
* Device Attributes
*/
static ssize_t pfail_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct fpga_dev *priv = dev_get_drvdata(dev);
u8 val;
val = ioread8(priv->regs + CTL_PWR_FAIL);
return snprintf(buf, PAGE_SIZE, "0x%.2x\n", val);
}
static ssize_t pgood_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct fpga_dev *priv = dev_get_drvdata(dev);
return snprintf(buf, PAGE_SIZE, "%d\n", fpga_power_good(priv));
}
static ssize_t penable_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct fpga_dev *priv = dev_get_drvdata(dev);
return snprintf(buf, PAGE_SIZE, "%d\n", fpga_power_enabled(priv));
}
static ssize_t penable_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct fpga_dev *priv = dev_get_drvdata(dev);
unsigned long val;
int ret;
ret = kstrtoul(buf, 0, &val);
if (ret)
return ret;
if (val) {
ret = fpga_enable_power_supplies(priv);
if (ret)
return ret;
} else {
fpga_do_stop(priv);
fpga_disable_power_supplies(priv);
}
return count;
}
static ssize_t program_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct fpga_dev *priv = dev_get_drvdata(dev);
return snprintf(buf, PAGE_SIZE, "%d\n", fpga_running(priv));
}
static ssize_t program_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct fpga_dev *priv = dev_get_drvdata(dev);
unsigned long val;
int ret;
ret = kstrtoul(buf, 0, &val);
if (ret)
return ret;
/* We can't have an image writer and be programming simultaneously */
if (mutex_lock_interruptible(&priv->lock))
return -ERESTARTSYS;
/* Program or Reset the FPGA's */
ret = val ? fpga_do_program(priv) : fpga_do_stop(priv);
if (ret)
goto out_unlock;
/* Success */
ret = count;
out_unlock:
mutex_unlock(&priv->lock);
return ret;
}
static DEVICE_ATTR(power_fail, S_IRUGO, pfail_show, NULL);
static DEVICE_ATTR(power_good, S_IRUGO, pgood_show, NULL);
static DEVICE_ATTR(power_enable, S_IRUGO | S_IWUSR,
penable_show, penable_store);
static DEVICE_ATTR(program, S_IRUGO | S_IWUSR,
program_show, program_store);
static struct attribute *fpga_attributes[] = {
&dev_attr_power_fail.attr,
&dev_attr_power_good.attr,
&dev_attr_power_enable.attr,
&dev_attr_program.attr,
NULL,
};
static const struct attribute_group fpga_attr_group = {
.attrs = fpga_attributes,
};
/*
* OpenFirmware Device Subsystem
*/
#define SYS_REG_VERSION 0x00
#define SYS_REG_GEOGRAPHIC 0x10
static bool dma_filter(struct dma_chan *chan, void *data)
{
/*
* DMA Channel #0 is the only acceptable device
*
* This probably won't survive an unload/load cycle of the Freescale
* DMAEngine driver, but that won't be a problem
*/
return chan->chan_id == 0 && chan->device->dev_id == 0;
}
static int fpga_of_remove(struct platform_device *op)
{
struct fpga_dev *priv = platform_get_drvdata(op);
struct device *this_device = priv->miscdev.this_device;
sysfs_remove_group(&this_device->kobj, &fpga_attr_group);
misc_deregister(&priv->miscdev);
free_irq(priv->irq, priv);
irq_dispose_mapping(priv->irq);
/* make sure the power supplies are off */
fpga_disable_power_supplies(priv);
/* unmap registers */
iounmap(priv->immr);
iounmap(priv->regs);
dma_release_channel(priv->chan);
/* drop our reference to the private data structure */
kref_put(&priv->ref, fpga_dev_remove);
return 0;
}
/* CTL-CPLD Version Register */
#define CTL_CPLD_VERSION 0x2000
static int fpga_of_probe(struct platform_device *op)
{
struct device_node *of_node = op->dev.of_node;
struct device *this_device;
struct fpga_dev *priv;
dma_cap_mask_t mask;
u32 ver;
int ret;
/* Allocate private data */
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv) {
dev_err(&op->dev, "Unable to allocate private data\n");
ret = -ENOMEM;
goto out_return;
}
/* Setup the miscdevice */
priv->miscdev.minor = MISC_DYNAMIC_MINOR;
priv->miscdev.name = drv_name;
priv->miscdev.fops = &fpga_fops;
kref_init(&priv->ref);
platform_set_drvdata(op, priv);
priv->dev = &op->dev;
mutex_init(&priv->lock);
init_completion(&priv->completion);
dev_set_drvdata(priv->dev, priv);
dma_cap_zero(mask);
dma_cap_set(DMA_MEMCPY, mask);
dma_cap_set(DMA_SLAVE, mask);
dma_cap_set(DMA_SG, mask);
/* Get control of DMA channel #0 */
priv->chan = dma_request_channel(mask, dma_filter, NULL);
if (!priv->chan) {
dev_err(&op->dev, "Unable to acquire DMA channel #0\n");
ret = -ENODEV;
goto out_free_priv;
}
/* Remap the registers for use */
priv->regs = of_iomap(of_node, 0);
if (!priv->regs) {
dev_err(&op->dev, "Unable to ioremap registers\n");
ret = -ENOMEM;
goto out_dma_release_channel;
}
/* Remap the IMMR for use */
priv->immr = ioremap(get_immrbase(), 0x100000);
if (!priv->immr) {
dev_err(&op->dev, "Unable to ioremap IMMR\n");
ret = -ENOMEM;
goto out_unmap_regs;
}
/*
* Check that external DMA is configured
*
* U-Boot does this for us, but we should check it and bail out if
* there is a problem. Failing to have this register setup correctly
* will cause the DMA controller to transfer a single cacheline
* worth of data, then wedge itself.
*/
if ((ioread32be(priv->immr + 0x114) & 0xE00) != 0xE00) {
dev_err(&op->dev, "External DMA control not configured\n");
ret = -ENODEV;
goto out_unmap_immr;
}
/*
* Check the CTL-CPLD version
*
* This driver uses the CTL-CPLD DATA-FPGA power sequencer, and we
* don't want to run on any version of the CTL-CPLD that does not use
* a compatible register layout.
*
* v2: changed register layout, added power sequencer
* v3: added glitch filter on the i2c overcurrent/overtemp outputs
*/
ver = ioread8(priv->regs + CTL_CPLD_VERSION);
if (ver != 0x02 && ver != 0x03) {
dev_err(&op->dev, "CTL-CPLD is not version 0x02 or 0x03!\n");
ret = -ENODEV;
goto out_unmap_immr;
}
/* Set the exact size that the firmware image should be */
ver = ioread32be(priv->regs + SYS_REG_VERSION);
priv->fw_size = (ver & (1 << 18)) ? FW_SIZE_EP2S130 : FW_SIZE_EP2S90;
/* Find the correct IRQ number */
priv->irq = irq_of_parse_and_map(of_node, 0);
if (priv->irq == NO_IRQ) {
dev_err(&op->dev, "Unable to find IRQ line\n");
ret = -ENODEV;
goto out_unmap_immr;
}
/* Request the IRQ */
ret = request_irq(priv->irq, fpga_irq, IRQF_SHARED, drv_name, priv);
if (ret) {
dev_err(&op->dev, "Unable to request IRQ %d\n", priv->irq);
ret = -ENODEV;
goto out_irq_dispose_mapping;
}
/* Reset and stop the FPGA's, just in case */
fpga_do_stop(priv);
/* Register the miscdevice */
ret = misc_register(&priv->miscdev);
if (ret) {
dev_err(&op->dev, "Unable to register miscdevice\n");
goto out_free_irq;
}
/* Create the sysfs files */
this_device = priv->miscdev.this_device;
dev_set_drvdata(this_device, priv);
ret = sysfs_create_group(&this_device->kobj, &fpga_attr_group);
if (ret) {
dev_err(&op->dev, "Unable to create sysfs files\n");
goto out_misc_deregister;
}
dev_info(priv->dev, "CARMA FPGA Programmer: %s rev%s with %s FPGAs\n",
(ver & (1 << 17)) ? "Correlator" : "Digitizer",
(ver & (1 << 16)) ? "B" : "A",
(ver & (1 << 18)) ? "EP2S130" : "EP2S90");
return 0;
out_misc_deregister:
misc_deregister(&priv->miscdev);
out_free_irq:
free_irq(priv->irq, priv);
out_irq_dispose_mapping:
irq_dispose_mapping(priv->irq);
out_unmap_immr:
iounmap(priv->immr);
out_unmap_regs:
iounmap(priv->regs);
out_dma_release_channel:
dma_release_channel(priv->chan);
out_free_priv:
kref_put(&priv->ref, fpga_dev_remove);
out_return:
return ret;
}
static struct of_device_id fpga_of_match[] = {
{ .compatible = "carma,fpga-programmer", },
{},
};
static struct platform_driver fpga_of_driver = {
.probe = fpga_of_probe,
.remove = fpga_of_remove,
.driver = {
.name = drv_name,
.of_match_table = fpga_of_match,
.owner = THIS_MODULE,
},
};
/*
* Module Init / Exit
*/
static int __init fpga_init(void)
{
led_trigger_register_simple("fpga", &ledtrig_fpga);
return platform_driver_register(&fpga_of_driver);
}
static void __exit fpga_exit(void)
{
platform_driver_unregister(&fpga_of_driver);
led_trigger_unregister_simple(ledtrig_fpga);
}
MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>");
MODULE_DESCRIPTION("CARMA Board DATA-FPGA Programmer");
MODULE_LICENSE("GPL");
module_init(fpga_init);
module_exit(fpga_exit);
|