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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
/dts-v1/;
#include "jaguar2_common.dtsi"
/ {
model = "Jaguar2 Cu48 PCB111 Reference Board";
compatible = "mscc,jr2-pcb111", "mscc,jr2";
aliases {
i2c0 = &i2c0;
i2c149 = &i2c149;
i2c150 = &i2c150;
i2c151 = &i2c151;
i2c152 = &i2c152;
i2c203 = &i2c203;
};
i2c0_imux: i2c0-imux {
compatible = "i2c-mux-pinctrl";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&i2c0>;
pinctrl-names =
"i2c149", "i2c150", "i2c151", "i2c152", "i2c203", "idle";
pinctrl-0 = <&i2cmux_0>;
pinctrl-1 = <&i2cmux_1>;
pinctrl-2 = <&i2cmux_2>;
pinctrl-3 = <&i2cmux_3>;
pinctrl-4 = <&i2cmux_pins_i>; // Added by convention for PoE
pinctrl-5 = <&i2cmux_pins_i>;
i2c149: i2c@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c150: i2c@1 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c151: i2c@2 {
reg = <0x2>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c152: i2c@3 {
reg = <0x3>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c203: i2c@4 {
reg = <0x4>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&gpio {
synce_builtin_pins: synce-builtin-pins {
// GPIO 49 == SI_nCS13
pins = "GPIO_49";
function = "si";
};
cpld_pins: cpld-pins {
// GPIO 50 == SI_nCS14
pins = "GPIO_50";
function = "si";
};
cpld_fifo_pins: synce-builtin-pins {
// GPIO 51 == SI_nCS15
pins = "GPIO_51";
function = "si";
};
};
&gpio {
i2cmux_pins_i: i2cmux-pins {
pins = "GPIO_17", "GPIO_18";
function = "twi_scl_m";
output-low;
};
i2cmux_0: i2cmux-0-pins {
pins = "GPIO_17";
function = "twi_scl_m";
output-high;
};
i2cmux_1: i2cmux-1-pins {
pins = "GPIO_18";
function = "twi_scl_m";
output-high;
};
i2cmux_2: i2cmux-2-pins {
pins = "GPIO_20";
function = "twi_scl_m";
output-high;
};
i2cmux_3: i2cmux-3-pins {
pins = "GPIO_21";
function = "twi_scl_m";
output-high;
};
};
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