summaryrefslogtreecommitdiff
path: root/arch/arm/mach-at91/sama5d4.c
blob: 7638509639f4b4da2f0337f8cf62af216496fe56 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
/*
 *  Chip-specific setup code for the SAMA5D4 family
 *
 *  Copyright (C) 2013 Atmel Corporation,
 *                     Nicolas Ferre <nicolas.ferre@atmel.com>
 *
 * Licensed under GPLv2 or later.
 */

#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/clk/at91_pmc.h>

#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/sama5d4.h>
#include <mach/cpu.h>
#include <mach/hardware.h>

#include "soc.h"
#include "generic.h"
#include "sam9_smc.h"

/* --------------------------------------------------------------------
 *  Processor initialization
 * -------------------------------------------------------------------- */
static struct map_desc at91_io_desc[] __initdata = {
	{
	.virtual        = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_MPDDRC),
	.pfn            = __phys_to_pfn(SAMA5D4_BASE_MPDDRC),
	.length         = SZ_512,
	.type           = MT_DEVICE,
	},
	{
	.virtual        = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_PMC),
	.pfn            = __phys_to_pfn(SAMA5D4_BASE_PMC),
	.length         = SZ_512,
	.type           = MT_DEVICE,
	},
	{ /* On sama5d4, we use USART3 as serial console */
	.virtual        = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_USART3),
	.pfn            = __phys_to_pfn(SAMA5D4_BASE_USART3),
	.length         = SZ_256,
	.type           = MT_DEVICE,
	},
	{ /* A bunch of peripheral with fine grained IO space */
	.virtual        = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_SYS2),
	.pfn            = __phys_to_pfn(SAMA5D4_BASE_SYS2),
	.length         = SZ_2K,
	.type           = MT_DEVICE,
	},
};


static void __init sama5d4_map_io(void)
{
	iotable_init(at91_io_desc, ARRAY_SIZE(at91_io_desc));
	at91_init_sram(0, SAMA5D4_NS_SRAM_BASE, SAMA5D4_NS_SRAM_SIZE);
}

AT91_SOC_START(sama5d4)
	.map_io = sama5d4_map_io,
AT91_SOC_END