Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller

maintainers:
  - Michal Simek <michal.simek@xilinx.com>

allOf:
  - $ref: spi-controller.yaml#

properties:
  compatible:
    enum:
      - xlnx,versal-qspi-1.0
      - xlnx,zynqmp-qspi-1.0

  reg:
    maxItems: 2

  interrupts:
    maxItems: 1

  clock-names:
    items:
      - const: ref_clk
      - const: pclk

  clocks:
    maxItems: 2

  iommus:
    maxItems: 1

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clock-names
  - clocks

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      qspi: spi@ff0f0000 {
        compatible = "xlnx,zynqmp-qspi-1.0";
        clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
        clock-names = "ref_clk", "pclk";
        interrupts = <0 15 4>;
        interrupt-parent = <&gic>;
        reg = <0x0 0xff0f0000 0x0 0x1000>,
              <0x0 0xc0000000 0x0 0x8000000>;
      };
    };