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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,ipq8074-qmp-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm QMP PHY controller (PCIe, IPQ8074)
maintainers:
- Vinod Koul <vkoul@kernel.org>
description:
QMP PHY controller supports physical layer functionality for a number of
controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
properties:
compatible:
enum:
- qcom,ipq6018-qmp-pcie-phy
- qcom,ipq8074-qmp-gen3-pcie-phy
- qcom,ipq8074-qmp-pcie-phy
reg:
items:
- description: serdes
clocks:
maxItems: 3
clock-names:
items:
- const: aux
- const: cfg_ahb
- const: pipe
resets:
maxItems: 2
reset-names:
items:
- const: phy
- const: common
"#clock-cells":
const: 0
clock-output-names:
maxItems: 1
"#phy-cells":
const: 0
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- "#clock-cells"
- clock-output-names
- "#phy-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-ipq6018.h>
#include <dt-bindings/reset/qcom,gcc-ipq6018.h>
phy@84000 {
compatible = "qcom,ipq6018-qmp-pcie-phy";
reg = <0x0 0x00084000 0x0 0x1000>;
clocks = <&gcc GCC_PCIE0_AUX_CLK>,
<&gcc GCC_PCIE0_AHB_CLK>,
<&gcc GCC_PCIE0_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"pipe";
clock-output-names = "gcc_pcie0_pipe_clk_src";
#clock-cells = <0>;
#phy-cells = <0>;
resets = <&gcc GCC_PCIE0_PHY_BCR>,
<&gcc GCC_PCIE0PHY_PHY_BCR>;
reset-names = "phy",
"common";
};
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