path: root/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt

NVIDIA Tegra PCIe controller

Required properties:
- compatible: For Tegra20, must contain "nvidia,tegra20-pcie".  For Tegra30,
  "nvidia,tegra30-pcie".  For Tegra124, must contain "nvidia,tegra124-pcie".
  Otherwise, must contain "nvidia,<chip>-pcie", plus one of the above, where
  <chip> is tegra132 or tegra210.
- device_type: Must be "pci"
- reg: A list of physical base address and length for each set of controller
  registers. Must contain an entry for each entry in the reg-names property.
- reg-names: Must include the following entries:
  "pads": PADS registers
  "afi": AFI registers
  "cs": configuration space region
- interrupts: A list of interrupt outputs of the controller. Must contain an
  entry for each entry in the interrupt-names property.
- interrupt-names: Must include the following entries:
  "intr": The Tegra interrupt that is asserted for controller interrupts
  "msi": The Tegra interrupt that is asserted when an MSI is received
- bus-range: Range of bus numbers associated with this controller
- #address-cells: Address representation for root ports (must be 3)
  - cell 0 specifies the bus and device numbers of the root port:
    [23:16]: bus number
    [15:11]: device number
  - cell 1 denotes the upper 32 address bits and should be 0
  - cell 2 contains the lower 32 address bits and is used to translate to the
    CPU address space
- #size-cells: Size representation for root ports (must be 2)
- ranges: Describes the translation of addresses for root ports and standard
  PCI regions. The entries must be 6 cells each, where the first three cells
  correspond to the address as described for the #address-cells property
  above, the fourth cell is the physical CPU address to translate to and the
  fifth and six cells are as described for the #size-cells property above.
  - The first two entries are expected to translate the addresses for the root
    port registers, which are referenced by the assigned-addresses property of
    the root port nodes (see below).
  - The remaining entries setup the mapping for the standard I/O, memory and
    prefetchable PCI regions. The first cell determines the type of region
    that is setup:
    - 0x81000000: I/O memory region
    - 0x82000000: non-prefetchable memory region
    - 0xc2000000: prefetchable memory region
  Please refer to the standard PCI bus binding document for a more detailed
  explanation.
- #interrupt-cells: Size representation for interrupts (must be 1)
- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
  Please refer to the standard PCI bus binding document for a more detailed
  explanation.
- clocks: Must contain an entry for each entry in clock-names.
  See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
  - pex
  - afi
  - pll_e
  - cml (not required for Tegra20)
- resets: Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
  - pex
  - afi
  - pcie_x

Required properties on Tegra124 and later (deprecated):
- phys: Must contain an entry for each entry in phy-names.
- phy-names: Must include the following entries:
  - pcie

These properties are deprecated in favour of per-lane PHYs define in each of
the root ports (see below).

Power supplies for Tegra20:
- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
  supply 1.05 V.
- avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
  supply 1.05 V.
- vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V.

Power supplies for Tegra30:
- Required:
  - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
    supply 1.05 V.
  - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
    supply 1.05 V.
  - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
    supply 1.8 V.
  - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
    Must supply 3.3 V.
- Optional:
  - If lanes 0 to 3 are used:
    - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
    - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
  - If lanes 4 or 5 are used:
    - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
    - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.

Power supplies for Tegra124:
- Required:
  - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
  - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
  - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
    supply 1.05 V.
  - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
    Must supply 3.3 V.
  - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
    Must supply 3.3 V.
  - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
    supply 2.8-3.3 V.
  - avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must
    supply 1.05 V.

Root ports are defined as subnodes of the PCIe controller node.

Required properties:
- device_type: Must be "pci"
- assigned-addresses: Address and size of the port configuration registers
- reg: PCI bus address of the root port
- #address-cells: Must be 3
- #size-cells: Must be 2
- ranges: Sub-ranges distributed from the PCIe controller node. An empty
  property is sufficient.
- nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
  are:
  - Root port 0 uses 4 lanes, root port 1 is unused.
  - Both root ports use 2 lanes.

Required properties for Tegra124 and later:
- phys: Must contain an phandle to a PHY for each entry in phy-names.
- phy-names: Must include an entry for each active lane. Note that the number
  of entries does not have to (though usually will) be equal to the specified
  number of lanes in the nvidia,num-lanes property. Entries are of the form
  "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.

Examples:
=========

Tegra20:
--------

SoC DTSI:

	pcie-controller@80003000 {
		compatible = "nvidia,tegra20-pcie";
		device_type = "pci";
		reg = <0x80003000 0x00000800   /* PADS registers */
		       0x80003800 0x00000200   /* AFI registers */
		       0x90000000 0x10000000>; /* configuration space */
		reg-names = "pads", "afi", "cs";
		interrupts = <0 98 0x04   /* controller interrupt */
		              0 99 0x04>; /* MSI interrupt */
		interrupt-names = "intr", "msi";

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

		bus-range = <0x00 0xff>;
		#address-cells = <3>;
		#size-cells = <2>;

		ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */
			  0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */
			  0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */
			  0x82000000 0 0xa0000000 0xa0000000 0 0x10000000   /* non-prefetchable memory */
			  0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */

		clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
		clock-names = "pex", "afi", "pll_e";
		resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
		reset-names = "pex", "afi", "pcie_x";
		status = "disabled";

		pci@1,0 {
			device_type = "pci";
			assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
			reg = <0x000800 0 0 0 0>;
			status = "disabled";

			#address-cells = <3>;
			#size-cells = <2>;

			ranges;

			nvidia,num-lanes = <2>;
		};

		pci@2,0 {
			device_type = "pci";
			assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
			reg = <0x001000 0 0 0 0>;
			status = "disabled";

			#address-cells = <3>;
			#size-cells = <2>;

			ranges;

			nvidia,num-lanes = <2>;
		};
	};

Board DTS:

	pcie-controller@80003000 {
		status = "okay";

		vdd-supply = <&pci_vdd_reg>;
		pex-clk-supply = <&pci_clk_reg>;

		/* root port 00:01.0 */
		pci@1,0 {
			status = "okay";

			/* bridge 01:00.0 (optional) */
			pci@0,0 {
				reg = <0x010000 0 0 0 0>;

				#address-cells = <3>;
				#size-cells = <2>;

				device_type = "pci";

				/* endpoint 02:00.0 */
				pci@0,0 {
					reg = <0x020000 0 0 0 0>;
				};
			};
		};
	};

Note that devices on the PCI bus are dynamically discovered using PCI's bus
enumeration and therefore don't need corresponding device nodes in DT. However
if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
device nodes need to be added in order to allow the bus' children to be
instantiated at the proper location in the operating system's device tree (as
illustrated by the optional nodes in the example above).

Tegra30:
--------

SoC DTSI:

	pcie-controller@00003000 {
		compatible = "nvidia,tegra30-pcie";
		device_type = "pci";
		reg = <0x00003000 0x00000800   /* PADS registers */
		       0x00003800 0x00000200   /* AFI registers */
		       0x10000000 0x10000000>; /* configuration space */
		reg-names = "pads", "afi", "cs";
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
			      GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
		interrupt-names = "intr", "msi";

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

		bus-range = <0x00 0xff>;
		#address-cells = <3>;
		#size-cells = <2>;

		ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
			  0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
			  0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
			  0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
			  0x82000000 0 0x20000000 0x20000000 0 0x08000000   /* non-prefetchable memory */
			  0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */

		clocks = <&tegra_car TEGRA30_CLK_PCIE>,
			 <&tegra_car TEGRA30_CLK_AFI>,
			 <&tegra_car TEGRA30_CLK_PLL_E>,
			 <&tegra_car TEGRA30_CLK_CML0>;
		clock-names = "pex", "afi", "pll_e", "cml";
		resets = <&tegra_car 70>,
			 <&tegra_car 72>,
			 <&tegra_car 74>;
		reset-names = "pex", "afi", "pcie_x";
		status = "disabled";

		pci@1,0 {
			device_type = "pci";
			assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
			reg = <0x000800 0 0 0 0>;
			status = "disabled";

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			nvidia,num-lanes = <2>;
		};

		pci@2,0 {
			device_type = "pci";
			assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
			reg = <0x001000 0 0 0 0>;
			status = "disabled";

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			nvidia,num-lanes = <2>;
		};

		pci@3,0 {
			device_type = "pci";
			assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
			reg = <0x001800 0 0 0 0>;
			status = "disabled";

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			nvidia,num-lanes = <2>;
		};
	};

Board DTS:

	pcie-controller@00003000 {
		status = "okay";

		avdd-pexa-supply = <&ldo1_reg>;
		vdd-pexa-supply = <&ldo1_reg>;
		avdd-pexb-supply = <&ldo1_reg>;
		vdd-pexb-supply = <&ldo1_reg>;
		avdd-pex-pll-supply = <&ldo1_reg>;
		avdd-plle-supply = <&ldo1_reg>;
		vddio-pex-ctl-supply = <&sys_3v3_reg>;
		hvdd-pex-supply = <&sys_3v3_pexs_reg>;

		pci@1,0 {
			status = "okay";
		};

		pci@3,0 {
			status = "okay";
		};
	};

Tegra124:
---------

SoC DTSI:

	pcie-controller@01003000 {
		compatible = "nvidia,tegra124-pcie";
		device_type = "pci";
		reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
		       0x0 0x01003800 0x0 0x00000800   /* AFI registers */
		       0x0 0x02000000 0x0 0x10000000>; /* configuration space */
		reg-names = "pads", "afi", "cs";
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
		interrupt-names = "intr", "msi";

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

		bus-range = <0x00 0xff>;
		#address-cells = <3>;
		#size-cells = <2>;

		ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
			  0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
			  0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
			  0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
			  0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */

		clocks = <&tegra_car TEGRA124_CLK_PCIE>,
			 <&tegra_car TEGRA124_CLK_AFI>,
			 <&tegra_car TEGRA124_CLK_PLL_E>,
			 <&tegra_car TEGRA124_CLK_CML0>;
		clock-names = "pex", "afi", "pll_e", "cml";
		resets = <&tegra_car 70>,
			 <&tegra_car 72>,
			 <&tegra_car 74>;
		reset-names = "pex", "afi", "pcie_x";
		status = "disabled";

		pci@1,0 {
			device_type = "pci";
			assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
			reg = <0x000800 0 0 0 0>;
			status = "disabled";

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			nvidia,num-lanes = <2>;
		};

		pci@2,0 {
			device_type = "pci";
			assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
			reg = <0x001000 0 0 0 0>;
			status = "disabled";

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			nvidia,num-lanes = <1>;
		};
	};

Board DTS:

	pcie-controller@01003000 {
		status = "okay";

		avddio-pex-supply = <&vdd_1v05_run>;
		dvddio-pex-supply = <&vdd_1v05_run>;
		avdd-pex-pll-supply = <&vdd_1v05_run>;
		hvdd-pex-supply = <&vdd_3v3_lp0>;
		hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
		vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
		avdd-pll-erefe-supply = <&avdd_1v05_run>;

		/* Mini PCIe */
		pci@1,0 {
			phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
			phy-names = "pcie-0";
			status = "okay";
		};

		/* Gigabit Ethernet */
		pci@2,0 {
			phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
			phy-names = "pcie-0";
			status = "okay";
		};
	};