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Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
Transceiver
Required properties:
- compatible : must be "sff,sfp"
Optional Properties:
- i2c-bus : phandle of an I2C bus controller for the SFP two wire serial
interface
- mod-def0-gpios : GPIO phandle and a specifier of the MOD-DEF0 (AKA Mod_ABS)
module presence input gpio signal, active (module absent) high
- los-gpios : GPIO phandle and a specifier of the Receiver Loss of Signal
Indication input gpio signal, active (signal lost) high
- tx-fault-gpios : GPIO phandle and a specifier of the Module Transmitter
Fault input gpio signal, active (fault condition) high
- tx-disable-gpios : GPIO phandle and a specifier of the Transmitter Disable
output gpio signal, active (Tx disable) high
- rate-select0-gpios : GPIO phandle and a specifier of the Rx Signaling Rate
Select (AKA RS0) output gpio signal, low: low Rx rate, high: high Rx rate
- rate-select1-gpios : GPIO phandle and a specifier of the Tx Signaling Rate
Select (AKA RS1) output gpio signal (SFP+ only), low: low Tx rate, high:
high Tx rate
Example #1: Direct serdes to SFP connection
sfp_eth3: sfp-eth3 {
compatible = "sff,sfp";
i2c-bus = <&sfp_1g_i2c>;
los-gpios = <&cpm_gpio2 22 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&cpm_gpio2 21 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&cpm_sfp_1g_pins &cps_sfp_1g_pins>;
tx-disable-gpios = <&cps_gpio1 24 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&cpm_gpio2 19 GPIO_ACTIVE_HIGH>;
};
&cps_emac3 {
phy-names = "comphy";
phys = <&cps_comphy5 0>;
sfp = <&sfp_eth3>;
};
Example #2: Serdes to PHY to SFP connection
sfp_eth0: sfp-eth0 {
compatible = "sff,sfp";
i2c-bus = <&sfpp0_i2c>;
los-gpios = <&cps_gpio1 28 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&cps_gpio1 27 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&cps_sfpp0_pins>;
tx-disable-gpios = <&cps_gpio1 29 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&cps_gpio1 26 GPIO_ACTIVE_HIGH>;
};
p0_phy: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
pinctrl-names = "default";
pinctrl-0 = <&cpm_phy0_pins &cps_phy0_pins>;
reg = <0>;
interrupt = <&cpm_gpio2 18 IRQ_TYPE_EDGE_FALLING>;
sfp = <&sfp_eth0>;
};
&cpm_eth0 {
phy = <&p0_phy>;
phy-mode = "10gbase-kr";
};
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