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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek-jpeg-decoder.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek JPEG Decoder
maintainers:
- Xia Jiang <xia.jiang@mediatek.com>
description: |-
Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs
properties:
compatible:
oneOf:
- items:
- enum:
- mediatek,mt8173-jpgdec
- mediatek,mt2701-jpgdec
- items:
- enum:
- mediatek,mt7623-jpgdec
- const: mediatek,mt2701-jpgdec
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 2
minItems: 2
clock-names:
items:
- const: jpgdec-smi
- const: jpgdec
power-domains:
maxItems: 1
iommus:
maxItems: 2
description: |
Points to the respective IOMMU block with master port as argument, see
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
Ports are according to the HW.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- power-domains
- iommus
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt2701-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/mt2701-larb-port.h>
#include <dt-bindings/power/mt2701-power.h>
jpegdec: jpegdec@15004000 {
compatible = "mediatek,mt2701-jpgdec";
reg = <0x15004000 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
<&imgsys CLK_IMG_JPGDEC>;
clock-names = "jpgdec-smi",
"jpgdec";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
};
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