blob: 53a67933840256ed8220bc127443a904ed2402cd (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Write DMA with Rotation
maintainers:
- Matthias Brugger <matthias.bgg@gmail.com>
- Moudy Ho <moudy.ho@mediatek.com>
description: |
One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.
properties:
compatible:
oneOf:
- enum:
- mediatek,mt8183-mdp3-wrot
- items:
- enum:
- mediatek,mt8195-mdp3-wrot
- const: mediatek,mt8183-mdp3-wrot
reg:
maxItems: 1
mediatek,gce-client-reg:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- description: phandle of GCE
- description: GCE subsys id
- description: register offset
- description: register size
description: The register of client driver can be configured by gce with
4 arguments defined in this property. Each GCE subsys id is mapping to
a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
mediatek,gce-events:
description:
The event id which is mapping to the specific hardware event signal
to gce. The event id is defined in the gce header
include/dt-bindings/gce/<chip>-gce.h of each chips.
$ref: /schemas/types.yaml#/definitions/uint32-array
power-domains:
maxItems: 1
clocks:
minItems: 1
iommus:
maxItems: 1
'#dma-cells':
const: 1
required:
- compatible
- reg
- mediatek,gce-client-reg
- mediatek,gce-events
- power-domains
- clocks
- iommus
- '#dma-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/gce/mt8183-gce.h>
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/memory/mt8183-larb-port.h>
dma-controller@14005000 {
compatible = "mediatek,mt8183-mdp3-wrot";
reg = <0x14005000 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
<CMDQ_EVENT_MDP_WROT0_EOF>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_WROT0>;
iommus = <&iommu>;
#dma-cells = <1>;
};
|
