blob: 7200095ef19e3cc6b1d1f258adc34a6fc67a51aa (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-vic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Video Image Composer
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^vic@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- nvidia,tegra124-vic
- nvidia,tegra210-vic
- nvidia,tegra186-vic
- nvidia,tegra194-vic
- nvidia,tegra234-vic
- items:
- const: nvidia,tegra132-vic
- const: nvidia,tegra124-vic
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: clock input for the VIC hardware
clock-names:
items:
- const: vic
resets:
items:
- description: module reset
reset-names:
items:
- const: vic
power-domains:
maxItems: 1
iommus:
maxItems: 1
interconnects:
description: Description of the interconnect paths for the VIC;
see ../interconnect/interconnect.txt for details.
items:
- description: memory read client for VIC
- description: memory write client for VIC
interconnect-names:
items:
- const: dma-mem # read
- const: write
dma-coherent: true
additionalProperties: false
|
