Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

Binding for a ST pre-divider clock driver.

This binding uses the common clock binding[1].
Base address is located to the parent node. See clock binding[2]

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt

Required properties:

- compatible : shall be:
	"st,clkgena-prediv-c65",	"st,clkgena-prediv"
	"st,clkgena-prediv-c32",	"st,clkgena-prediv"

- #clock-cells : From common clock binding; shall be set to 0.

- clocks : From common clock binding

- clock-output-names : From common clock binding.

Example:

	clockgenA@fd345000 {
		reg = <0xfd345000 0xb50>;

		CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
			#clock-cells = <0>;
			compatible = "st,clkgena-prediv-c32",
				     "st,clkgena-prediv";

			clocks = <&CLK_SYSIN>;

			clock-output-names = "CLK_M_A2_OSC_PREDIV";
		};
	};