blob: c55a7c494e013da52ffb5412a040af7fcda853bc (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas CPG DIV6 Clock
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
description:
The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
Generator (CPG). Their clock input is divided by a configurable factor from 1
to 64.
properties:
compatible:
items:
- enum:
- renesas,r8a73a4-div6-clock # R-Mobile APE6
- renesas,r8a7740-div6-clock # R-Mobile A1
- renesas,sh73a0-div6-clock # SH-Mobile AG5
- const: renesas,cpg-div6-clock
reg:
maxItems: 1
clocks:
oneOf:
- maxItems: 1
- maxItems: 4
- maxItems: 8
description:
For clocks with multiple parents, invalid settings must be specified as
"<0>".
'#clock-cells':
const: 0
clock-output-names: true
required:
- compatible
- reg
- clocks
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/r8a73a4-clock.h>
sdhi2_clk: sdhi2_clk@e615007c {
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
reg = <0xe615007c 4>;
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>,
<&extal2_clk>;
#clock-cells = <0>;
};
|
