/dts-v1/;

/include/ "tegra30.dtsi"

/ {
	model = "NVIDIA Tegra30 Cardhu evaluation board";
	compatible = "nvidia,cardhu", "nvidia,tegra30";

	memory {
		reg = < 0x80000000 0x40000000 >;
	};

	pinmux@70000000 {
		pinctrl-names = "default";
		pinctrl-0 = <&state_default>;

		state_default: pinmux {
			sdmmc1_clk_pz0 {
				nvidia,pins = "sdmmc1_clk_pz0";
				nvidia,function = "sdmmc1";
				nvidia,pull = <0>;
				nvidia,tristate = <0>;
			};
			sdmmc1_cmd_pz1 {
				nvidia,pins =	"sdmmc1_cmd_pz1",
						"sdmmc1_dat0_py7",
						"sdmmc1_dat1_py6",
						"sdmmc1_dat2_py5",
						"sdmmc1_dat3_py4";
				nvidia,function = "sdmmc1";
				nvidia,pull = <2>;
				nvidia,tristate = <0>;
			};
			sdmmc4_clk_pcc4 {
				nvidia,pins =	"sdmmc4_clk_pcc4",
						"sdmmc4_rst_n_pcc3";
				nvidia,function = "sdmmc4";
				nvidia,pull = <0>;
				nvidia,tristate = <0>;
			};
			sdmmc4_dat0_paa0 {
				nvidia,pins =	"sdmmc4_dat0_paa0",
						"sdmmc4_dat1_paa1",
						"sdmmc4_dat2_paa2",
						"sdmmc4_dat3_paa3",
						"sdmmc4_dat4_paa4",
						"sdmmc4_dat5_paa5",
						"sdmmc4_dat6_paa6",
						"sdmmc4_dat7_paa7";
				nvidia,function = "sdmmc4";
				nvidia,pull = <2>;
				nvidia,tristate = <0>;
			};
		};
	};

	serial@70006000 {
		clock-frequency = < 408000000 >;
	};

	serial@70006040 {
		status = "disable";
	};

	serial@70006200 {
		status = "disable";
	};

	serial@70006300 {
		status = "disable";
	};

	serial@70006400 {
		status = "disable";
	};

	i2c@7000c000 {
		clock-frequency = <100000>;
	};

	i2c@7000c400 {
		clock-frequency = <100000>;
	};

	i2c@7000c500 {
		clock-frequency = <100000>;
	};

	i2c@7000c700 {
		clock-frequency = <100000>;
	};

	i2c@7000d000 {
		clock-frequency = <100000>;
	};

	sdhci@78000000 {
		cd-gpios = <&gpio 69 0>; /* gpio PI5 */
		wp-gpios = <&gpio 155 0>; /* gpio PT3 */
		power-gpios = <&gpio 31 0>; /* gpio PD7 */
	};

	sdhci@78000200 {
		status = "disable";
	};

	sdhci@78000400 {
		status = "disable";
	};

	sdhci@78000400 {
		support-8bit;
	};
};