From bd348ca24d81cca2a27f8ffa12adc8f30f184275 Mon Sep 17 00:00:00 2001 From: Xingyu Wu Date: Mon, 17 Jul 2023 10:30:34 +0800 Subject: dt-bindings: clock: Add StarFive JH7110 PLL clock generator Add bindings for the PLL clock generator on the JH7110 RISC-V SoC. Reviewed-by: Conor Dooley Reviewed-by: Krzysztof Kozlowski Signed-off-by: Xingyu Wu Reviewed-by: Emil Renner Berthing Signed-off-by: Conor Dooley --- include/dt-bindings/clock/starfive,jh7110-crg.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h index 06257bfd9ac1..3fb5e31c3be4 100644 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h @@ -6,6 +6,12 @@ #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ +/* PLL clocks */ +#define JH7110_PLLCLK_PLL0_OUT 0 +#define JH7110_PLLCLK_PLL1_OUT 1 +#define JH7110_PLLCLK_PLL2_OUT 2 +#define JH7110_PLLCLK_END 3 + /* SYSCRG clocks */ #define JH7110_SYSCLK_CPU_ROOT 0 #define JH7110_SYSCLK_CPU_CORE 1 -- cgit v1.2.3