From 5d6fdcf2e524f95012b262eee6aa7f5ebe577766 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 2 Oct 2021 02:59:45 +0200 Subject: dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domains This adds the defines for the power domains provided by the VPU blk-ctrl. Signed-off-by: Lucas Stach Acked-by: Rob Herring Signed-off-by: Shawn Guo --- include/dt-bindings/power/imx8mm-power.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h index fc9c2e16aadc..38b0a56fd7d0 100644 --- a/include/dt-bindings/power/imx8mm-power.h +++ b/include/dt-bindings/power/imx8mm-power.h @@ -19,4 +19,8 @@ #define IMX8MM_POWER_DOMAIN_DISPMIX 10 #define IMX8MM_POWER_DOMAIN_MIPI 11 +#define IMX8MM_VPUBLK_PD_G1 0 +#define IMX8MM_VPUBLK_PD_G2 1 +#define IMX8MM_VPUBLK_PD_H1 2 + #endif -- cgit v1.2.3 From e66f2cd293bf7520d22853f251918f36b4ff740e Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 2 Oct 2021 02:59:48 +0200 Subject: dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domains This adds the defines for the power domains provided by the DISP blk-ctrl. Signed-off-by: Lucas Stach Acked-by: Rob Herring Signed-off-by: Shawn Guo --- include/dt-bindings/power/imx8mm-power.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h index 38b0a56fd7d0..648938f24c8e 100644 --- a/include/dt-bindings/power/imx8mm-power.h +++ b/include/dt-bindings/power/imx8mm-power.h @@ -23,4 +23,9 @@ #define IMX8MM_VPUBLK_PD_G2 1 #define IMX8MM_VPUBLK_PD_H1 2 +#define IMX8MM_DISPBLK_PD_CSI_BRIDGE 0 +#define IMX8MM_DISPBLK_PD_LCDIF 1 +#define IMX8MM_DISPBLK_PD_MIPI_DSI 2 +#define IMX8MM_DISPBLK_PD_MIPI_CSI 3 + #endif -- cgit v1.2.3 From f07c776f6d7ed5f8423863efd2445016e690aba1 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 30 Sep 2021 10:31:44 +0200 Subject: arm64: dts: mediatek: Move reset controller constants into common location The DT binding includes for reset controllers are located in include/dt-bindings/reset/. Move the Mediatek reset constants in there. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Guenter Roeck Reviewed-by: Matthias Brugger Link: https://lore.kernel.org/r/20210930103105.v4.1.I514d9aafff3a062f751b37d3fea7402f67595b86@changeid Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +- drivers/watchdog/mtk_wdt.c | 6 +- .../dt-bindings/reset-controller/mt2712-resets.h | 22 ----- .../dt-bindings/reset-controller/mt8183-resets.h | 98 ---------------------- .../dt-bindings/reset-controller/mt8192-resets.h | 30 ------- include/dt-bindings/reset/mt2712-resets.h | 22 +++++ include/dt-bindings/reset/mt8183-resets.h | 98 ++++++++++++++++++++++ include/dt-bindings/reset/mt8192-resets.h | 30 +++++++ 8 files changed, 154 insertions(+), 154 deletions(-) delete mode 100644 include/dt-bindings/reset-controller/mt2712-resets.h delete mode 100644 include/dt-bindings/reset-controller/mt8183-resets.h delete mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h create mode 100644 include/dt-bindings/reset/mt2712-resets.h create mode 100644 include/dt-bindings/reset/mt8183-resets.h create mode 100644 include/dt-bindings/reset/mt8192-resets.h (limited to 'include') diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 9ea4c5001b1e..de12f78c2ee0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 796fbb048cbe..3d208d627fb0 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -9,9 +9,9 @@ * Based on sunxi_wdt.c */ -#include -#include -#include +#include +#include +#include #include #include #include diff --git a/include/dt-bindings/reset-controller/mt2712-resets.h b/include/dt-bindings/reset-controller/mt2712-resets.h deleted file mode 100644 index 9e7ee762f076..000000000000 --- a/include/dt-bindings/reset-controller/mt2712-resets.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 MediaTek Inc. - * Author: Yong Liang - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712 -#define _DT_BINDINGS_RESET_CONTROLLER_MT2712 - -#define MT2712_TOPRGU_INFRA_SW_RST 0 -#define MT2712_TOPRGU_MM_SW_RST 1 -#define MT2712_TOPRGU_MFG_SW_RST 2 -#define MT2712_TOPRGU_VENC_SW_RST 3 -#define MT2712_TOPRGU_VDEC_SW_RST 4 -#define MT2712_TOPRGU_IMG_SW_RST 5 -#define MT2712_TOPRGU_INFRA_AO_SW_RST 8 -#define MT2712_TOPRGU_USB_SW_RST 9 -#define MT2712_TOPRGU_APMIXED_SW_RST 10 - -#define MT2712_TOPRGU_SW_RST_NUM 11 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */ diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset-controller/mt8183-resets.h deleted file mode 100644 index a1bbd41e0d12..000000000000 --- a/include/dt-bindings/reset-controller/mt8183-resets.h +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 MediaTek Inc. - * Author: Yong Liang - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8183 -#define _DT_BINDINGS_RESET_CONTROLLER_MT8183 - -/* INFRACFG AO resets */ -#define MT8183_INFRACFG_AO_THERM_SW_RST 0 -#define MT8183_INFRACFG_AO_USB_TOP_SW_RST 1 -#define MT8183_INFRACFG_AO_MM_IOMMU_SW_RST 3 -#define MT8183_INFRACFG_AO_MSDC3_SW_RST 4 -#define MT8183_INFRACFG_AO_MSDC2_SW_RST 5 -#define MT8183_INFRACFG_AO_MSDC1_SW_RST 6 -#define MT8183_INFRACFG_AO_MSDC0_SW_RST 7 -#define MT8183_INFRACFG_AO_APDMA_SW_RST 9 -#define MT8183_INFRACFG_AO_MIMP_D_SW_RST 10 -#define MT8183_INFRACFG_AO_BTIF_SW_RST 12 -#define MT8183_INFRACFG_AO_DISP_PWM_SW_RST 14 -#define MT8183_INFRACFG_AO_AUXADC_SW_RST 15 - -#define MT8183_INFRACFG_AO_IRTX_SW_RST 32 -#define MT8183_INFRACFG_AO_SPI0_SW_RST 33 -#define MT8183_INFRACFG_AO_I2C0_SW_RST 34 -#define MT8183_INFRACFG_AO_I2C1_SW_RST 35 -#define MT8183_INFRACFG_AO_I2C2_SW_RST 36 -#define MT8183_INFRACFG_AO_I2C3_SW_RST 37 -#define MT8183_INFRACFG_AO_UART0_SW_RST 38 -#define MT8183_INFRACFG_AO_UART1_SW_RST 39 -#define MT8183_INFRACFG_AO_UART2_SW_RST 40 -#define MT8183_INFRACFG_AO_PWM_SW_RST 41 -#define MT8183_INFRACFG_AO_SPI1_SW_RST 42 -#define MT8183_INFRACFG_AO_I2C4_SW_RST 43 -#define MT8183_INFRACFG_AO_DVFSP_SW_RST 44 -#define MT8183_INFRACFG_AO_SPI2_SW_RST 45 -#define MT8183_INFRACFG_AO_SPI3_SW_RST 46 -#define MT8183_INFRACFG_AO_UFSHCI_SW_RST 47 - -#define MT8183_INFRACFG_AO_PMIC_WRAP_SW_RST 64 -#define MT8183_INFRACFG_AO_SPM_SW_RST 65 -#define MT8183_INFRACFG_AO_USBSIF_SW_RST 66 -#define MT8183_INFRACFG_AO_KP_SW_RST 68 -#define MT8183_INFRACFG_AO_APXGPT_SW_RST 69 -#define MT8183_INFRACFG_AO_CLDMA_AO_SW_RST 70 -#define MT8183_INFRACFG_AO_UNIPRO_UFS_SW_RST 71 -#define MT8183_INFRACFG_AO_DX_CC_SW_RST 72 -#define MT8183_INFRACFG_AO_UFSPHY_SW_RST 73 - -#define MT8183_INFRACFG_AO_DX_CC_SEC_SW_RST 96 -#define MT8183_INFRACFG_AO_GCE_SW_RST 97 -#define MT8183_INFRACFG_AO_CLDMA_SW_RST 98 -#define MT8183_INFRACFG_AO_TRNG_SW_RST 99 -#define MT8183_INFRACFG_AO_AP_MD_CCIF_1_SW_RST 103 -#define MT8183_INFRACFG_AO_AP_MD_CCIF_SW_RST 104 -#define MT8183_INFRACFG_AO_I2C1_IMM_SW_RST 105 -#define MT8183_INFRACFG_AO_I2C1_ARB_SW_RST 106 -#define MT8183_INFRACFG_AO_I2C2_IMM_SW_RST 107 -#define MT8183_INFRACFG_AO_I2C2_ARB_SW_RST 108 -#define MT8183_INFRACFG_AO_I2C5_SW_RST 109 -#define MT8183_INFRACFG_AO_I2C5_IMM_SW_RST 110 -#define MT8183_INFRACFG_AO_I2C5_ARB_SW_RST 111 -#define MT8183_INFRACFG_AO_SPI4_SW_RST 112 -#define MT8183_INFRACFG_AO_SPI5_SW_RST 113 -#define MT8183_INFRACFG_AO_INFRA2MFGAXI_CBIP_CLAS_SW_RST 114 -#define MT8183_INFRACFG_AO_MFGAXI2INFRA_M0_CBIP_GLAS_OUT_SW_RST 115 -#define MT8183_INFRACFG_AO_MFGAXI2INFRA_M1_CBIP_GLAS_OUT_SW_RST 116 -#define MT8183_INFRACFG_AO_UFS_AES_SW_RST 117 -#define MT8183_INFRACFG_AO_CCU_I2C_IRQ_SW_RST 118 -#define MT8183_INFRACFG_AO_CCU_I2C_DMA_SW_RST 119 -#define MT8183_INFRACFG_AO_I2C6_SW_RST 120 -#define MT8183_INFRACFG_AO_CCU_GALS_SW_RST 121 -#define MT8183_INFRACFG_AO_IPU_GALS_SW_RST 122 -#define MT8183_INFRACFG_AO_CONN2AP_GALS_SW_RST 123 -#define MT8183_INFRACFG_AO_AP_MD_CCIF2_SW_RST 124 -#define MT8183_INFRACFG_AO_AP_MD_CCIF3_SW_RST 125 -#define MT8183_INFRACFG_AO_I2C7_SW_RST 126 -#define MT8183_INFRACFG_AO_I2C8_SW_RST 127 - -#define MT8183_INFRACFG_SW_RST_NUM 128 - -#define MT8183_TOPRGU_MM_SW_RST 1 -#define MT8183_TOPRGU_MFG_SW_RST 2 -#define MT8183_TOPRGU_VENC_SW_RST 3 -#define MT8183_TOPRGU_VDEC_SW_RST 4 -#define MT8183_TOPRGU_IMG_SW_RST 5 -#define MT8183_TOPRGU_MD_SW_RST 7 -#define MT8183_TOPRGU_CONN_SW_RST 9 -#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 -#define MT8183_TOPRGU_IPU0_SW_RST 14 -#define MT8183_TOPRGU_IPU1_SW_RST 15 -#define MT8183_TOPRGU_AUDIO_SW_RST 17 -#define MT8183_TOPRGU_CAMSYS_SW_RST 18 - -#define MT8183_TOPRGU_SW_RST_NUM 19 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */ diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h b/include/dt-bindings/reset-controller/mt8192-resets.h deleted file mode 100644 index be9a7ca245b9..000000000000 --- a/include/dt-bindings/reset-controller/mt8192-resets.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2020 MediaTek Inc. - * Author: Yong Liang - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 -#define _DT_BINDINGS_RESET_CONTROLLER_MT8192 - -#define MT8192_TOPRGU_MM_SW_RST 1 -#define MT8192_TOPRGU_MFG_SW_RST 2 -#define MT8192_TOPRGU_VENC_SW_RST 3 -#define MT8192_TOPRGU_VDEC_SW_RST 4 -#define MT8192_TOPRGU_IMG_SW_RST 5 -#define MT8192_TOPRGU_MD_SW_RST 7 -#define MT8192_TOPRGU_CONN_SW_RST 9 -#define MT8192_TOPRGU_CONN_MCU_SW_RST 12 -#define MT8192_TOPRGU_IPU0_SW_RST 14 -#define MT8192_TOPRGU_IPU1_SW_RST 15 -#define MT8192_TOPRGU_AUDIO_SW_RST 17 -#define MT8192_TOPRGU_CAMSYS_SW_RST 18 -#define MT8192_TOPRGU_MJC_SW_RST 19 -#define MT8192_TOPRGU_C2K_S2_SW_RST 20 -#define MT8192_TOPRGU_C2K_SW_RST 21 -#define MT8192_TOPRGU_PERI_SW_RST 22 -#define MT8192_TOPRGU_PERI_AO_SW_RST 23 - -#define MT8192_TOPRGU_SW_RST_NUM 23 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ diff --git a/include/dt-bindings/reset/mt2712-resets.h b/include/dt-bindings/reset/mt2712-resets.h new file mode 100644 index 000000000000..9e7ee762f076 --- /dev/null +++ b/include/dt-bindings/reset/mt2712-resets.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Yong Liang + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712 +#define _DT_BINDINGS_RESET_CONTROLLER_MT2712 + +#define MT2712_TOPRGU_INFRA_SW_RST 0 +#define MT2712_TOPRGU_MM_SW_RST 1 +#define MT2712_TOPRGU_MFG_SW_RST 2 +#define MT2712_TOPRGU_VENC_SW_RST 3 +#define MT2712_TOPRGU_VDEC_SW_RST 4 +#define MT2712_TOPRGU_IMG_SW_RST 5 +#define MT2712_TOPRGU_INFRA_AO_SW_RST 8 +#define MT2712_TOPRGU_USB_SW_RST 9 +#define MT2712_TOPRGU_APMIXED_SW_RST 10 + +#define MT2712_TOPRGU_SW_RST_NUM 11 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */ diff --git a/include/dt-bindings/reset/mt8183-resets.h b/include/dt-bindings/reset/mt8183-resets.h new file mode 100644 index 000000000000..a1bbd41e0d12 --- /dev/null +++ b/include/dt-bindings/reset/mt8183-resets.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Yong Liang + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8183 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8183 + +/* INFRACFG AO resets */ +#define MT8183_INFRACFG_AO_THERM_SW_RST 0 +#define MT8183_INFRACFG_AO_USB_TOP_SW_RST 1 +#define MT8183_INFRACFG_AO_MM_IOMMU_SW_RST 3 +#define MT8183_INFRACFG_AO_MSDC3_SW_RST 4 +#define MT8183_INFRACFG_AO_MSDC2_SW_RST 5 +#define MT8183_INFRACFG_AO_MSDC1_SW_RST 6 +#define MT8183_INFRACFG_AO_MSDC0_SW_RST 7 +#define MT8183_INFRACFG_AO_APDMA_SW_RST 9 +#define MT8183_INFRACFG_AO_MIMP_D_SW_RST 10 +#define MT8183_INFRACFG_AO_BTIF_SW_RST 12 +#define MT8183_INFRACFG_AO_DISP_PWM_SW_RST 14 +#define MT8183_INFRACFG_AO_AUXADC_SW_RST 15 + +#define MT8183_INFRACFG_AO_IRTX_SW_RST 32 +#define MT8183_INFRACFG_AO_SPI0_SW_RST 33 +#define MT8183_INFRACFG_AO_I2C0_SW_RST 34 +#define MT8183_INFRACFG_AO_I2C1_SW_RST 35 +#define MT8183_INFRACFG_AO_I2C2_SW_RST 36 +#define MT8183_INFRACFG_AO_I2C3_SW_RST 37 +#define MT8183_INFRACFG_AO_UART0_SW_RST 38 +#define MT8183_INFRACFG_AO_UART1_SW_RST 39 +#define MT8183_INFRACFG_AO_UART2_SW_RST 40 +#define MT8183_INFRACFG_AO_PWM_SW_RST 41 +#define MT8183_INFRACFG_AO_SPI1_SW_RST 42 +#define MT8183_INFRACFG_AO_I2C4_SW_RST 43 +#define MT8183_INFRACFG_AO_DVFSP_SW_RST 44 +#define MT8183_INFRACFG_AO_SPI2_SW_RST 45 +#define MT8183_INFRACFG_AO_SPI3_SW_RST 46 +#define MT8183_INFRACFG_AO_UFSHCI_SW_RST 47 + +#define MT8183_INFRACFG_AO_PMIC_WRAP_SW_RST 64 +#define MT8183_INFRACFG_AO_SPM_SW_RST 65 +#define MT8183_INFRACFG_AO_USBSIF_SW_RST 66 +#define MT8183_INFRACFG_AO_KP_SW_RST 68 +#define MT8183_INFRACFG_AO_APXGPT_SW_RST 69 +#define MT8183_INFRACFG_AO_CLDMA_AO_SW_RST 70 +#define MT8183_INFRACFG_AO_UNIPRO_UFS_SW_RST 71 +#define MT8183_INFRACFG_AO_DX_CC_SW_RST 72 +#define MT8183_INFRACFG_AO_UFSPHY_SW_RST 73 + +#define MT8183_INFRACFG_AO_DX_CC_SEC_SW_RST 96 +#define MT8183_INFRACFG_AO_GCE_SW_RST 97 +#define MT8183_INFRACFG_AO_CLDMA_SW_RST 98 +#define MT8183_INFRACFG_AO_TRNG_SW_RST 99 +#define MT8183_INFRACFG_AO_AP_MD_CCIF_1_SW_RST 103 +#define MT8183_INFRACFG_AO_AP_MD_CCIF_SW_RST 104 +#define MT8183_INFRACFG_AO_I2C1_IMM_SW_RST 105 +#define MT8183_INFRACFG_AO_I2C1_ARB_SW_RST 106 +#define MT8183_INFRACFG_AO_I2C2_IMM_SW_RST 107 +#define MT8183_INFRACFG_AO_I2C2_ARB_SW_RST 108 +#define MT8183_INFRACFG_AO_I2C5_SW_RST 109 +#define MT8183_INFRACFG_AO_I2C5_IMM_SW_RST 110 +#define MT8183_INFRACFG_AO_I2C5_ARB_SW_RST 111 +#define MT8183_INFRACFG_AO_SPI4_SW_RST 112 +#define MT8183_INFRACFG_AO_SPI5_SW_RST 113 +#define MT8183_INFRACFG_AO_INFRA2MFGAXI_CBIP_CLAS_SW_RST 114 +#define MT8183_INFRACFG_AO_MFGAXI2INFRA_M0_CBIP_GLAS_OUT_SW_RST 115 +#define MT8183_INFRACFG_AO_MFGAXI2INFRA_M1_CBIP_GLAS_OUT_SW_RST 116 +#define MT8183_INFRACFG_AO_UFS_AES_SW_RST 117 +#define MT8183_INFRACFG_AO_CCU_I2C_IRQ_SW_RST 118 +#define MT8183_INFRACFG_AO_CCU_I2C_DMA_SW_RST 119 +#define MT8183_INFRACFG_AO_I2C6_SW_RST 120 +#define MT8183_INFRACFG_AO_CCU_GALS_SW_RST 121 +#define MT8183_INFRACFG_AO_IPU_GALS_SW_RST 122 +#define MT8183_INFRACFG_AO_CONN2AP_GALS_SW_RST 123 +#define MT8183_INFRACFG_AO_AP_MD_CCIF2_SW_RST 124 +#define MT8183_INFRACFG_AO_AP_MD_CCIF3_SW_RST 125 +#define MT8183_INFRACFG_AO_I2C7_SW_RST 126 +#define MT8183_INFRACFG_AO_I2C8_SW_RST 127 + +#define MT8183_INFRACFG_SW_RST_NUM 128 + +#define MT8183_TOPRGU_MM_SW_RST 1 +#define MT8183_TOPRGU_MFG_SW_RST 2 +#define MT8183_TOPRGU_VENC_SW_RST 3 +#define MT8183_TOPRGU_VDEC_SW_RST 4 +#define MT8183_TOPRGU_IMG_SW_RST 5 +#define MT8183_TOPRGU_MD_SW_RST 7 +#define MT8183_TOPRGU_CONN_SW_RST 9 +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 +#define MT8183_TOPRGU_IPU0_SW_RST 14 +#define MT8183_TOPRGU_IPU1_SW_RST 15 +#define MT8183_TOPRGU_AUDIO_SW_RST 17 +#define MT8183_TOPRGU_CAMSYS_SW_RST 18 + +#define MT8183_TOPRGU_SW_RST_NUM 19 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */ diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h new file mode 100644 index 000000000000..be9a7ca245b9 --- /dev/null +++ b/include/dt-bindings/reset/mt8192-resets.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Yong Liang + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8192 + +#define MT8192_TOPRGU_MM_SW_RST 1 +#define MT8192_TOPRGU_MFG_SW_RST 2 +#define MT8192_TOPRGU_VENC_SW_RST 3 +#define MT8192_TOPRGU_VDEC_SW_RST 4 +#define MT8192_TOPRGU_IMG_SW_RST 5 +#define MT8192_TOPRGU_MD_SW_RST 7 +#define MT8192_TOPRGU_CONN_SW_RST 9 +#define MT8192_TOPRGU_CONN_MCU_SW_RST 12 +#define MT8192_TOPRGU_IPU0_SW_RST 14 +#define MT8192_TOPRGU_IPU1_SW_RST 15 +#define MT8192_TOPRGU_AUDIO_SW_RST 17 +#define MT8192_TOPRGU_CAMSYS_SW_RST 18 +#define MT8192_TOPRGU_MJC_SW_RST 19 +#define MT8192_TOPRGU_C2K_S2_SW_RST 20 +#define MT8192_TOPRGU_C2K_SW_RST 21 +#define MT8192_TOPRGU_PERI_SW_RST 22 +#define MT8192_TOPRGU_PERI_AO_SW_RST 23 + +#define MT8192_TOPRGU_SW_RST_NUM 23 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ -- cgit v1.2.3 From 7fdb1bc3d96e9c8860dd434dd725cc94603744fa Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 30 Sep 2021 10:31:47 +0200 Subject: arm64: dts: mt8173: Add the mmsys reset bit to reset the dsi0 Reset the DSI hardware is needed to prevent different settings between the bootloader and the kernel. Signed-off-by: Enric Balletbo i Serra Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210930103105.v4.4.I7bd7d9a8da5e2894711b700a1127e6902a2b2f1d@changeid Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++ include/dt-bindings/reset/mt8173-resets.h | 2 ++ 2 files changed, 4 insertions(+) (limited to 'include') diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index d9e005ae5bb0..dee66e5f054c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -996,6 +996,7 @@ assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; assigned-clock-rates = <400000000>; #clock-cells = <1>; + #reset-cells = <1>; mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, <&gce 1 CMDQ_THR_PRIO_HIGHEST>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; @@ -1222,6 +1223,7 @@ <&mmsys CLK_MM_DSI0_DIGITAL>, <&mipi_tx0>; clock-names = "engine", "digital", "hs"; + resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; phys = <&mipi_tx0>; phy-names = "dphy"; status = "disabled"; diff --git a/include/dt-bindings/reset/mt8173-resets.h b/include/dt-bindings/reset/mt8173-resets.h index ba8636eda5ae..6a60c7cecc4c 100644 --- a/include/dt-bindings/reset/mt8173-resets.h +++ b/include/dt-bindings/reset/mt8173-resets.h @@ -27,6 +27,8 @@ #define MT8173_INFRA_GCE_FAXI_RST 40 #define MT8173_INFRA_MMIOMMURST 47 +/* MMSYS resets */ +#define MT8173_MMSYS_SW0_RST_B_DISP_DSI0 25 /* PERICFG resets */ #define MT8173_PERI_UART0_SW_RST 0 -- cgit v1.2.3 From 4bdb00edbd2ae354471f8d37d976a864bf29b60f Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 30 Sep 2021 10:31:48 +0200 Subject: arm64: dts: mt8183: Add the mmsys reset bit to reset the dsi0 Reset the DSI hardware is needed to prevent different settings between the bootloader and the kernel. While here, also remove the undocumented and also not used 'mediatek,syscon-dsi' property. Signed-off-by: Enric Balletbo i Serra Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210930103105.v4.5.I933f1532d7a1b2910843a9644c86a7d94a4b44e1@changeid Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 ++- include/dt-bindings/reset/mt8183-resets.h | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index de12f78c2ee0..ba4584faca5a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1319,6 +1319,7 @@ compatible = "mediatek,mt8183-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, <&gce 1 CMDQ_THR_PRIO_HIGHEST>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; @@ -1433,11 +1434,11 @@ reg = <0 0x14014000 0 0x1000>; interrupts = ; power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; - mediatek,syscon-dsi = <&mmsys 0x140>; clocks = <&mmsys CLK_MM_DSI0_MM>, <&mmsys CLK_MM_DSI0_IF>, <&mipi_tx0>; clock-names = "engine", "digital", "hs"; + resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; phys = <&mipi_tx0>; phy-names = "dphy"; }; diff --git a/include/dt-bindings/reset/mt8183-resets.h b/include/dt-bindings/reset/mt8183-resets.h index a1bbd41e0d12..48c5d2de0a38 100644 --- a/include/dt-bindings/reset/mt8183-resets.h +++ b/include/dt-bindings/reset/mt8183-resets.h @@ -80,6 +80,9 @@ #define MT8183_INFRACFG_SW_RST_NUM 128 +/* MMSYS resets */ +#define MT8183_MMSYS_SW0_RST_B_DISP_DSI0 25 + #define MT8183_TOPRGU_MM_SW_RST 1 #define MT8183_TOPRGU_MFG_SW_RST 2 #define MT8183_TOPRGU_VENC_SW_RST 3 -- cgit v1.2.3