From 28c5d4e40752fc39507a647b20649c5ca1cf33b7 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 10 Jan 2024 01:14:50 +0000 Subject: of: Add for_each_reserved_child_of_node() We would like to use for_each loop for status = "reserved" nodes. Add for_each_reserved_child_of_node() for it. Signed-off-by: Kuninori Morimoto Tested-by: Yusuke Goda Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/87a5pegfau.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- include/linux/of.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include') diff --git a/include/linux/of.h b/include/linux/of.h index 6a9ddf20e79a..331e05918f11 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -294,6 +294,8 @@ extern struct device_node *of_get_next_child(const struct device_node *node, struct device_node *prev); extern struct device_node *of_get_next_available_child( const struct device_node *node, struct device_node *prev); +extern struct device_node *of_get_next_reserved_child( + const struct device_node *node, struct device_node *prev); extern struct device_node *of_get_compatible_child(const struct device_node *parent, const char *compatible); @@ -541,6 +543,12 @@ static inline struct device_node *of_get_next_available_child( return NULL; } +static inline struct device_node *of_get_next_reserved_child( + const struct device_node *node, struct device_node *prev) +{ + return NULL; +} + static inline struct device_node *of_find_node_with_property( struct device_node *from, const char *prop_name) { @@ -1431,6 +1439,9 @@ static inline int of_property_read_s32(const struct device_node *np, #define for_each_available_child_of_node(parent, child) \ for (child = of_get_next_available_child(parent, NULL); child != NULL; \ child = of_get_next_available_child(parent, child)) +#define for_each_reserved_child_of_node(parent, child) \ + for (child = of_get_next_reserved_child(parent, NULL); child != NULL; \ + child = of_get_next_reserved_child(parent, child)) #define for_each_of_cpu_node(cpu) \ for (cpu = of_get_next_cpu_node(NULL); cpu != NULL; \ -- cgit v1.2.3 From 8923149ffc77eefa16d5412e30cf0e9cf26a01ba Mon Sep 17 00:00:00 2001 From: Duy Nguyen Date: Thu, 25 Jan 2024 16:34:32 +0100 Subject: dt-bindings: power: Add r8a779h0 SYSC power domain definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add power domain indices for the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Duy Nguyen Signed-off-by: Hai Pham Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/c5cbef71178cada761e9da7bcbb6f21334f93ef8.1706194617.git.geert+renesas@glider.be Signed-off-by: Ulf Hansson --- include/dt-bindings/power/renesas,r8a779h0-sysc.h | 49 +++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 include/dt-bindings/power/renesas,r8a779h0-sysc.h (limited to 'include') diff --git a/include/dt-bindings/power/renesas,r8a779h0-sysc.h b/include/dt-bindings/power/renesas,r8a779h0-sysc.h new file mode 100644 index 000000000000..f27976f523e8 --- /dev/null +++ b/include/dt-bindings/power/renesas,r8a779h0-sysc.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ +#define __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ + +/* + * These power domain indices match the Power Domain Register Numbers (PDR) + */ + +#define R8A779H0_PD_A1E0D0C0 0 +#define R8A779H0_PD_A1E0D0C1 1 +#define R8A779H0_PD_A1E0D0C2 2 +#define R8A779H0_PD_A1E0D0C3 3 +#define R8A779H0_PD_A2E0D0 16 +#define R8A779H0_PD_A3CR0 21 +#define R8A779H0_PD_A3CR1 22 +#define R8A779H0_PD_A3CR2 23 +#define R8A779H0_PD_A33DGA 24 +#define R8A779H0_PD_A23DGB 25 +#define R8A779H0_PD_C4 31 +#define R8A779H0_PD_A1DSP0 33 +#define R8A779H0_PD_A2IMP01 34 +#define R8A779H0_PD_A2PSC 35 +#define R8A779H0_PD_A2CV0 36 +#define R8A779H0_PD_A2CV1 37 +#define R8A779H0_PD_A3IMR0 38 +#define R8A779H0_PD_A3IMR1 39 +#define R8A779H0_PD_A3VC 40 +#define R8A779H0_PD_A2CN0 42 +#define R8A779H0_PD_A1CN0 44 +#define R8A779H0_PD_A1DSP1 45 +#define R8A779H0_PD_A2DMA 47 +#define R8A779H0_PD_A2CV2 48 +#define R8A779H0_PD_A2CV3 49 +#define R8A779H0_PD_A3IMR2 50 +#define R8A779H0_PD_A3IMR3 51 +#define R8A779H0_PD_A3PCI 52 +#define R8A779H0_PD_A2PCIPHY 53 +#define R8A779H0_PD_A3VIP0 56 +#define R8A779H0_PD_A3VIP2 58 +#define R8A779H0_PD_A3ISP0 60 +#define R8A779H0_PD_A3DUL 62 + +/* Always-on power area */ +#define R8A779H0_PD_ALWAYS_ON 64 + +#endif /* __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ */ -- cgit v1.2.3 From 3bbdf8c3d32103e21d9a826e40340fa59fc579ea Mon Sep 17 00:00:00 2001 From: Duy Nguyen Date: Thu, 25 Jan 2024 16:34:30 +0100 Subject: dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Duy Nguyen Signed-off-by: Hai Pham Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/11acbd2a30b58607474e9c32eb798b3a00e85e73.1706194617.git.geert+renesas@glider.be --- .../dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h | 96 ++++++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h (limited to 'include') diff --git a/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h b/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h new file mode 100644 index 000000000000..7ab6cfbaf901 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ + +#include + +/* r8a779h0 CPG Core Clocks */ + +#define R8A779H0_CLK_ZX 0 +#define R8A779H0_CLK_ZD 1 +#define R8A779H0_CLK_ZS 2 +#define R8A779H0_CLK_ZT 3 +#define R8A779H0_CLK_ZTR 4 +#define R8A779H0_CLK_S0D2 5 +#define R8A779H0_CLK_S0D3 6 +#define R8A779H0_CLK_S0D4 7 +#define R8A779H0_CLK_S0D1_VIO 8 +#define R8A779H0_CLK_S0D2_VIO 9 +#define R8A779H0_CLK_S0D4_VIO 10 +#define R8A779H0_CLK_S0D8_VIO 11 +#define R8A779H0_CLK_VIOBUSD1 12 +#define R8A779H0_CLK_VIOBUSD2 13 +#define R8A779H0_CLK_S0D1_VC 14 +#define R8A779H0_CLK_S0D2_VC 15 +#define R8A779H0_CLK_S0D4_VC 16 +#define R8A779H0_CLK_VCBUSD1 17 +#define R8A779H0_CLK_VCBUSD2 18 +#define R8A779H0_CLK_S0D2_MM 19 +#define R8A779H0_CLK_S0D4_MM 20 +#define R8A779H0_CLK_S0D2_U3DG 21 +#define R8A779H0_CLK_S0D4_U3DG 22 +#define R8A779H0_CLK_S0D2_RT 23 +#define R8A779H0_CLK_S0D3_RT 24 +#define R8A779H0_CLK_S0D4_RT 25 +#define R8A779H0_CLK_S0D6_RT 26 +#define R8A779H0_CLK_S0D2_PER 27 +#define R8A779H0_CLK_S0D3_PER 28 +#define R8A779H0_CLK_S0D4_PER 29 +#define R8A779H0_CLK_S0D6_PER 30 +#define R8A779H0_CLK_S0D12_PER 31 +#define R8A779H0_CLK_S0D24_PER 32 +#define R8A779H0_CLK_S0D1_HSC 33 +#define R8A779H0_CLK_S0D2_HSC 34 +#define R8A779H0_CLK_S0D4_HSC 35 +#define R8A779H0_CLK_S0D8_HSC 36 +#define R8A779H0_CLK_SVD1_IR 37 +#define R8A779H0_CLK_SVD2_IR 38 +#define R8A779H0_CLK_IMPAD1 39 +#define R8A779H0_CLK_IMPAD4 40 +#define R8A779H0_CLK_IMPB 41 +#define R8A779H0_CLK_SVD1_VIP 42 +#define R8A779H0_CLK_SVD2_VIP 43 +#define R8A779H0_CLK_CL 44 +#define R8A779H0_CLK_CL16M 45 +#define R8A779H0_CLK_CL16M_MM 46 +#define R8A779H0_CLK_CL16M_RT 47 +#define R8A779H0_CLK_CL16M_PER 48 +#define R8A779H0_CLK_CL16M_HSC 49 +#define R8A779H0_CLK_ZC0 50 +#define R8A779H0_CLK_ZC1 51 +#define R8A779H0_CLK_ZC2 52 +#define R8A779H0_CLK_ZC3 53 +#define R8A779H0_CLK_ZB3 54 +#define R8A779H0_CLK_ZB3D2 55 +#define R8A779H0_CLK_ZB3D4 56 +#define R8A779H0_CLK_ZG 57 +#define R8A779H0_CLK_SD0H 58 +#define R8A779H0_CLK_SD0 59 +#define R8A779H0_CLK_RPC 60 +#define R8A779H0_CLK_RPCD2 61 +#define R8A779H0_CLK_MSO 62 +#define R8A779H0_CLK_CANFD 63 +#define R8A779H0_CLK_CSI 64 +#define R8A779H0_CLK_FRAY 65 +#define R8A779H0_CLK_IPC 66 +#define R8A779H0_CLK_SASYNCRT 67 +#define R8A779H0_CLK_SASYNCPERD1 68 +#define R8A779H0_CLK_SASYNCPERD2 69 +#define R8A779H0_CLK_SASYNCPERD4 70 +#define R8A779H0_CLK_DSIEXT 71 +#define R8A779H0_CLK_DSIREF 72 +#define R8A779H0_CLK_ADGH 73 +#define R8A779H0_CLK_OSC 74 +#define R8A779H0_CLK_ZR0 75 +#define R8A779H0_CLK_ZR1 76 +#define R8A779H0_CLK_ZR2 77 +#define R8A779H0_CLK_RGMII 78 +#define R8A779H0_CLK_CPEX 79 +#define R8A779H0_CLK_CP 80 +#define R8A779H0_CLK_CBFUSA 81 +#define R8A779H0_CLK_R 82 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ */ -- cgit v1.2.3