From 4c8081e4696c7afc61930e4a49a6fa55c545b7e0 Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 31 Jul 2007 21:47:03 +0100
Subject: [MIPS] Fix computation of PGDIR_SHIFT for 16K pagesize on 32-bit
 kernels.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
 include/asm-mips/pgtable-32.h | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

(limited to 'include')

diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index 2fbd47eba32d..ff2948513f8e 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -43,11 +43,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
  */
 
 /* PGDIR_SHIFT determines what a third-level page table entry can map */
-#ifdef CONFIG_64BIT_PHYS_ADDR
-#define PGDIR_SHIFT	21
-#else
-#define PGDIR_SHIFT	22
-#endif
+#define PGDIR_SHIFT	(2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
 #define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
 #define PGDIR_MASK	(~(PGDIR_SIZE-1))
 
-- 
cgit v1.2.3


From 5ff974720abec255c17af6f3732dd410d364e367 Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Wed, 1 Aug 2007 15:25:28 +0100
Subject: [MIPS] Fix computation of {PGD,PMD,PTE}_T_LOG2.

For the generation of asm-offset.h to work these need to be evaulatable
by gcc as a constant expression.  This issue did exist for a while but
didn't bite because they're only in asm-offset.h for debugging purposes.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
 include/asm-mips/pgtable.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'include')

diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index 2e2d70d13ff6..e2fb9dbac3fc 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -168,9 +168,9 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
 #define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0)
 #endif
 
-#define PGD_T_LOG2	ffz(~sizeof(pgd_t))
-#define PMD_T_LOG2	ffz(~sizeof(pmd_t))
-#define PTE_T_LOG2	ffz(~sizeof(pte_t))
+#define PGD_T_LOG2	(__builtin_ffs(sizeof(pgd_t)) - 1)
+#define PMD_T_LOG2	(__builtin_ffs(sizeof(pmd_t)) - 1)
+#define PTE_T_LOG2	(__builtin_ffs(sizeof(pte_t)) - 1)
 
 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 
-- 
cgit v1.2.3


From 99e480d81ca98c25918c460fdb5ca876d7df6178 Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Wed, 1 Aug 2007 15:46:18 +0100
Subject: [MIPS] Compute PGD_ORDER from the select page size.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
 include/asm-mips/pgtable-32.h | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

(limited to 'include')

diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index ff2948513f8e..59c865deb0c7 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -51,17 +51,11 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
  * Entries per page directory level: we use two-level, so
  * we don't really have any PUD/PMD directory physically.
  */
-#ifdef CONFIG_64BIT_PHYS_ADDR
-#define PGD_ORDER	1
-#define PUD_ORDER	aieeee_attempt_to_allocate_pud
-#define PMD_ORDER	1
-#define PTE_ORDER	0
-#else
-#define PGD_ORDER	0
+#define __PGD_ORDER	(32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
+#define PGD_ORDER	(__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
 #define PUD_ORDER	aieeee_attempt_to_allocate_pud
 #define PMD_ORDER	1
 #define PTE_ORDER	0
-#endif
 
 #define PTRS_PER_PGD	((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
 #define PTRS_PER_PTE	((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
-- 
cgit v1.2.3


From 8420fd00e88ef4f6082866aa151bc753b006b3b6 Mon Sep 17 00:00:00 2001
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Thu, 2 Aug 2007 23:35:53 +0900
Subject: [MIPS] The irq_chip for TX39/TX49 SoCs

Add generic irq_chip for TX39/TX49 SoCs.  This can be replace
jmr3927_irq_irc, tx4927_irq_pic_type and tx4938_irq_pic_type.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
 arch/mips/Kconfig           |   3 +
 arch/mips/kernel/Makefile   |   1 +
 arch/mips/kernel/irq_txx9.c | 196 ++++++++++++++++++++++++++++++++++++++++++++
 include/asm-mips/txx9irq.h  |  30 +++++++
 4 files changed, 230 insertions(+)
 create mode 100644 arch/mips/kernel/irq_txx9.c
 create mode 100644 include/asm-mips/txx9irq.h

(limited to 'include')

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 2775dd666320..cec0d8411269 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -767,6 +767,9 @@ config IRQ_MSP_SLP
 config IRQ_MSP_CIC
 	bool
 
+config IRQ_TXX9
+	bool
+
 config MIPS_BOARDS_GEN
 	bool
 
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 07344cb37596..2fd96d95a39c 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_IRQ_CPU)		+= irq_cpu.o
 obj-$(CONFIG_IRQ_CPU_RM7K)	+= irq-rm7000.o
 obj-$(CONFIG_IRQ_CPU_RM9K)	+= irq-rm9000.o
 obj-$(CONFIG_MIPS_BOARDS_GEN)	+= irq-msc01.o
+obj-$(CONFIG_IRQ_TXX9)		+= irq_txx9.o
 
 obj-$(CONFIG_32BIT)		+= scall32-o32.o
 obj-$(CONFIG_64BIT)		+= scall64-64.o
diff --git a/arch/mips/kernel/irq_txx9.c b/arch/mips/kernel/irq_txx9.c
new file mode 100644
index 000000000000..172e14b461df
--- /dev/null
+++ b/arch/mips/kernel/irq_txx9.c
@@ -0,0 +1,196 @@
+/*
+ * linux/arch/mips/kernel/irq_txx9.c
+ *
+ * Based on linux/arch/mips/jmr3927/rbhma3100/irq.c,
+ *          linux/arch/mips/tx4927/common/tx4927_irq.c,
+ *          linux/arch/mips/tx4938/common/irq.c
+ *
+ * Copyright 2001, 2003-2005 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         ahennessy@mvista.com
+ *         source@mvista.com
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <asm/txx9irq.h>
+
+struct txx9_irc_reg {
+	u32 cer;
+	u32 cr[2];
+	u32 unused0;
+	u32 ilr[8];
+	u32 unused1[4];
+	u32 imr;
+	u32 unused2[7];
+	u32 scr;
+	u32 unused3[7];
+	u32 ssr;
+	u32 unused4[7];
+	u32 csr;
+};
+
+/* IRCER : Int. Control Enable */
+#define TXx9_IRCER_ICE	0x00000001
+
+/* IRCR : Int. Control */
+#define TXx9_IRCR_LOW	0x00000000
+#define TXx9_IRCR_HIGH	0x00000001
+#define TXx9_IRCR_DOWN	0x00000002
+#define TXx9_IRCR_UP	0x00000003
+#define TXx9_IRCR_EDGE(cr)	((cr) & 0x00000002)
+
+/* IRSCR : Int. Status Control */
+#define TXx9_IRSCR_EIClrE	0x00000100
+#define TXx9_IRSCR_EIClr_MASK	0x0000000f
+
+/* IRCSR : Int. Current Status */
+#define TXx9_IRCSR_IF	0x00010000
+#define TXx9_IRCSR_ILV_MASK	0x00000700
+#define TXx9_IRCSR_IVL_MASK	0x0000001f
+
+#define irc_dlevel	0
+#define irc_elevel	1
+
+static struct txx9_irc_reg __iomem *txx9_ircptr __read_mostly;
+
+static struct {
+	unsigned char level;
+	unsigned char mode;
+} txx9irq[TXx9_MAX_IR] __read_mostly;
+
+static void txx9_irq_unmask(unsigned int irq)
+{
+	unsigned int irq_nr = irq - TXX9_IRQ_BASE;
+	u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16 ) / 2];
+	int ofs = irq_nr / 16 * 16 + (irq_nr & 1) * 8;
+
+	__raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
+		     | (txx9irq[irq_nr].level << ofs),
+		     ilrp);
+#ifdef CONFIG_CPU_TX39XX
+	/* update IRCSR */
+	__raw_writel(0, &txx9_ircptr->imr);
+	__raw_writel(irc_elevel, &txx9_ircptr->imr);
+#endif
+}
+
+static inline void txx9_irq_mask(unsigned int irq)
+{
+	unsigned int irq_nr = irq - TXX9_IRQ_BASE;
+	u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16) / 2];
+	int ofs = irq_nr / 16 * 16 + (irq_nr & 1) * 8;
+
+	__raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
+		     | (irc_dlevel << ofs),
+		     ilrp);
+#ifdef CONFIG_CPU_TX39XX
+	/* update IRCSR */
+	__raw_writel(0, &txx9_ircptr->imr);
+	__raw_writel(irc_elevel, &txx9_ircptr->imr);
+	/* flush write buffer */
+	__raw_readl(&txx9_ircptr->ssr);
+#else
+	mmiowb();
+#endif
+}
+
+static void txx9_irq_mask_ack(unsigned int irq)
+{
+	unsigned int irq_nr = irq - TXX9_IRQ_BASE;
+
+	txx9_irq_mask(irq);
+	if (TXx9_IRCR_EDGE(txx9irq[irq_nr].mode)) {
+		/* clear edge detection */
+		u32 cr = __raw_readl(&txx9_ircptr->cr[irq_nr / 8]);
+		cr = (cr >> ((irq_nr & (8 - 1)) * 2)) & 3;
+		__raw_writel(TXx9_IRSCR_EIClrE | irq_nr,
+			     &txx9_ircptr->scr);
+	}
+}
+
+static int txx9_irq_set_type(unsigned int irq, unsigned int flow_type)
+{
+	unsigned int irq_nr = irq - TXX9_IRQ_BASE;
+	u32 cr;
+	u32 __iomem *crp;
+	int ofs;
+	int mode;
+
+	if (flow_type & IRQF_TRIGGER_PROBE)
+		return 0;
+	switch (flow_type & IRQF_TRIGGER_MASK) {
+	case IRQF_TRIGGER_RISING:	mode = TXx9_IRCR_UP;	break;
+	case IRQF_TRIGGER_FALLING:	mode = TXx9_IRCR_DOWN;	break;
+	case IRQF_TRIGGER_HIGH:	mode = TXx9_IRCR_HIGH;	break;
+	case IRQF_TRIGGER_LOW:	mode = TXx9_IRCR_LOW;	break;
+	default:
+		return -EINVAL;
+	}
+	crp = &txx9_ircptr->cr[(unsigned int)irq_nr / 8];
+	cr = __raw_readl(crp);
+	ofs = (irq_nr & (8 - 1)) * 2;
+	cr &= ~(0x3 << ofs);
+	cr |= (mode & 0x3) << ofs;
+	__raw_writel(cr, crp);
+	txx9irq[irq_nr].mode = mode;
+	return 0;
+}
+
+static struct irq_chip txx9_irq_chip = {
+	.name		= "TXX9",
+	.ack		= txx9_irq_mask_ack,
+	.mask		= txx9_irq_mask,
+	.mask_ack	= txx9_irq_mask_ack,
+	.unmask		= txx9_irq_unmask,
+	.set_type	= txx9_irq_set_type,
+};
+
+void __init txx9_irq_init(unsigned long baseaddr)
+{
+	int i;
+
+	txx9_ircptr = ioremap(baseaddr, sizeof(struct txx9_irc_reg));
+	for (i = 0; i < TXx9_MAX_IR; i++) {
+		txx9irq[i].level = 4; /* middle level */
+		txx9irq[i].mode = TXx9_IRCR_LOW;
+		set_irq_chip_and_handler(TXX9_IRQ_BASE + i,
+					 &txx9_irq_chip, handle_level_irq);
+	}
+
+	/* mask all IRC interrupts */
+	__raw_writel(0, &txx9_ircptr->imr);
+	for (i = 0; i < 8; i++)
+		__raw_writel(0, &txx9_ircptr->ilr[i]);
+	/* setup IRC interrupt mode (Low Active) */
+	for (i = 0; i < 2; i++)
+		__raw_writel(0, &txx9_ircptr->cr[i]);
+	/* enable interrupt control */
+	__raw_writel(TXx9_IRCER_ICE, &txx9_ircptr->cer);
+	__raw_writel(irc_elevel, &txx9_ircptr->imr);
+}
+
+int __init txx9_irq_set_pri(int irc_irq, int new_pri)
+{
+	int old_pri;
+
+	if ((unsigned int)irc_irq >= TXx9_MAX_IR)
+		return 0;
+	old_pri = txx9irq[irc_irq].level;
+	txx9irq[irc_irq].level = new_pri;
+	return old_pri;
+}
+
+int txx9_irq(void)
+{
+	u32 csr = __raw_readl(&txx9_ircptr->csr);
+
+	if (likely(!(csr & TXx9_IRCSR_IF)))
+		return TXX9_IRQ_BASE + (csr & (TXx9_MAX_IR - 1));
+	return -1;
+}
diff --git a/include/asm-mips/txx9irq.h b/include/asm-mips/txx9irq.h
new file mode 100644
index 000000000000..1c439e51b875
--- /dev/null
+++ b/include/asm-mips/txx9irq.h
@@ -0,0 +1,30 @@
+/*
+ * include/asm-mips/txx9irq.h
+ * TX39/TX49 interrupt controller definitions.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9IRQ_H
+#define __ASM_TXX9IRQ_H
+
+#include <irq.h>
+
+#ifdef CONFIG_IRQ_CPU
+#define TXX9_IRQ_BASE	(MIPS_CPU_IRQ_BASE + 8)
+#else
+#define TXX9_IRQ_BASE	0
+#endif
+
+#ifdef CONFIG_CPU_TX39XX
+#define TXx9_MAX_IR 16
+#else
+#define TXx9_MAX_IR 32
+#endif
+
+void txx9_irq_init(unsigned long baseaddr);
+int txx9_irq(void);
+int txx9_irq_set_pri(int irc_irq, int new_pri);
+
+#endif /* __ASM_TXX9IRQ_H */
-- 
cgit v1.2.3


From c87abd75b35e8f991ff8ff1510d6fb62612c61fa Mon Sep 17 00:00:00 2001
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Thu, 2 Aug 2007 23:36:02 +0900
Subject: [MIPS] Cleanup TX39/TX49 irq code

Cleanup jmr3927, tx4927 and tx4938 irq codes, using common IRQ_CPU,
I8259 and IRQ_TXX9 irq routines.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
 arch/mips/Kconfig                                  |   8 +-
 arch/mips/jmr3927/rbhma3100/irq.c                  |  48 +--
 arch/mips/jmr3927/rbhma3100/setup.c                |  13 -
 arch/mips/tx4927/common/tx4927_irq.c               | 395 +--------------------
 .../tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c | 171 +--------
 .../toshiba_rbtx4927/toshiba_rbtx4927_setup.c      |  11 +-
 arch/mips/tx4938/common/irq.c                      | 279 +--------------
 arch/mips/tx4938/toshiba_rbtx4938/irq.c            |   2 +-
 arch/mips/tx4938/toshiba_rbtx4938/setup.c          |   9 +-
 include/asm-mips/jmr3927/jmr3927.h                 |   3 +-
 include/asm-mips/jmr3927/tx3927.h                  |  36 --
 include/asm-mips/tx4927/toshiba_rbtx4927.h         |   2 +-
 include/asm-mips/tx4927/tx4927.h                   |  49 +--
 include/asm-mips/tx4927/tx4927_pci.h               |  23 +-
 include/asm-mips/tx4938/rbtx4938.h                 |  25 +-
 include/asm-mips/tx4938/tx4938.h                   |  41 ---
 16 files changed, 55 insertions(+), 1060 deletions(-)

(limited to 'include')

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cec0d8411269..4b02d8acc15b 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -528,6 +528,7 @@ config TOSHIBA_JMR3927
 	select DMA_NONCOHERENT
 	select HW_HAS_PCI
 	select MIPS_TX3927
+	select IRQ_TXX9
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_TX39XX
 	select SYS_SUPPORTS_32BIT_KERNEL
@@ -540,7 +541,9 @@ config TOSHIBA_RBTX4927
 	select DMA_NONCOHERENT
 	select HAS_TXX9_SERIAL
 	select HW_HAS_PCI
-	select I8259
+	select IRQ_CPU
+	select IRQ_TXX9
+	select I8259 if TOSHIBA_FPCIB0
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_TX49XX
 	select SYS_SUPPORTS_32BIT_KERNEL
@@ -560,7 +563,8 @@ config TOSHIBA_RBTX4938
 	select GENERIC_ISA_DMA
 	select HAS_TXX9_SERIAL
 	select HW_HAS_PCI
-	select I8259
+	select IRQ_CPU
+	select IRQ_TXX9
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_TX49XX
 	select SYS_SUPPORTS_32BIT_KERNEL
diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c
index 1187b44a3dd4..d9efe692e551 100644
--- a/arch/mips/jmr3927/rbhma3100/irq.c
+++ b/arch/mips/jmr3927/rbhma3100/irq.c
@@ -45,9 +45,6 @@
 #error JMR3927_IRQ_END > NR_IRQS
 #endif
 
-#define irc_dlevel	0
-#define irc_elevel	1
-
 static unsigned char irc_level[TX3927_NUM_IR] = {
 	5, 5, 5, 5, 5, 5,	/* INT[5:0] */
 	7, 7,			/* SIO */
@@ -80,34 +77,6 @@ static void unmask_irq_ioc(unsigned int irq)
 	(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
 }
 
-static void mask_irq_irc(unsigned int irq)
-{
-	unsigned int irq_nr = irq - JMR3927_IRQ_IRC;
-	volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
-	if (irq_nr & 1)
-		*ilrp = (*ilrp & 0x00ff) | (irc_dlevel << 8);
-	else
-		*ilrp = (*ilrp & 0xff00) | irc_dlevel;
-	/* update IRCSR */
-	tx3927_ircptr->imr = 0;
-	tx3927_ircptr->imr = irc_elevel;
-	/* flush write buffer */
-	(void)tx3927_ircptr->ssr;
-}
-
-static void unmask_irq_irc(unsigned int irq)
-{
-	unsigned int irq_nr = irq - JMR3927_IRQ_IRC;
-	volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
-	if (irq_nr & 1)
-		*ilrp = (*ilrp & 0x00ff) | (irc_level[irq_nr] << 8);
-	else
-		*ilrp = (*ilrp & 0xff00) | irc_level[irq_nr];
-	/* update IRCSR */
-	tx3927_ircptr->imr = 0;
-	tx3927_ircptr->imr = irc_elevel;
-}
-
 asmlinkage void plat_irq_dispatch(void)
 {
 	unsigned long cp0_cause = read_c0_cause();
@@ -168,10 +137,6 @@ void __init arch_init_irq(void)
 	/* clear PCI Reset interrupts */
 	jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 
-	/* enable interrupt control */
-	tx3927_ircptr->cer = TX3927_IRCER_ICE;
-	tx3927_ircptr->imr = irc_elevel;
-
 	jmr3927_irq_init();
 
 	/* setup IOC interrupt 1 (PCI, MODEM) */
@@ -193,20 +158,13 @@ static struct irq_chip jmr3927_irq_ioc = {
 	.unmask = unmask_irq_ioc,
 };
 
-static struct irq_chip jmr3927_irq_irc = {
-	.name = "jmr3927_irc",
-	.ack = mask_irq_irc,
-	.mask = mask_irq_irc,
-	.mask_ack = mask_irq_irc,
-	.unmask = unmask_irq_irc,
-};
-
 static void __init jmr3927_irq_init(void)
 {
 	u32 i;
 
-	for (i = JMR3927_IRQ_IRC; i < JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC; i++)
-		set_irq_chip_and_handler(i, &jmr3927_irq_irc, handle_level_irq);
+	txx9_irq_init(TX3927_IRC_REG);
+	for (i = 0; i < TXx9_MAX_IR; i++)
+		txx9_irq_set_pri(i, irc_level[i]);
 	for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
 		set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
 }
diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c
index 8303001516d2..fde56e86c2ab 100644
--- a/arch/mips/jmr3927/rbhma3100/setup.c
+++ b/arch/mips/jmr3927/rbhma3100/setup.c
@@ -290,19 +290,6 @@ static void __init tx3927_setup(void)
 	       tx3927_ccfgptr->crir,
 	       tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
 
-	/* IRC */
-	/* disable interrupt control */
-	tx3927_ircptr->cer = 0;
-	/* mask all IRC interrupts */
-	tx3927_ircptr->imr = 0;
-	for (i = 0; i < TX3927_NUM_IR / 2; i++) {
-		tx3927_ircptr->ilr[i] = 0;
-	}
-	/* setup IRC interrupt mode (Low Active) */
-	for (i = 0; i < TX3927_NUM_IR / 8; i++) {
-		tx3927_ircptr->cr[i] = 0;
-	}
-
 	/* TMR */
 	/* disable all timers */
 	for (i = 0; i < TX3927_NR_TMR; i++) {
diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c
index 00b0b975f349..0aabd57fdad2 100644
--- a/arch/mips/tx4927/common/tx4927_irq.c
+++ b/arch/mips/tx4927/common/tx4927_irq.c
@@ -23,398 +23,20 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
-#include <linux/errno.h>
 #include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/types.h>
 #include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/timex.h>
-#include <linux/slab.h>
-#include <linux/random.h>
-#include <linux/irq.h>
-#include <linux/bitops.h>
-#include <asm/bootinfo.h>
-#include <asm/io.h>
-#include <asm/irq.h>
+#include <asm/irq_cpu.h>
 #include <asm/mipsregs.h>
-#include <asm/system.h>
 #include <asm/tx4927/tx4927.h>
 #ifdef CONFIG_TOSHIBA_RBTX4927
 #include <asm/tx4927/toshiba_rbtx4927.h>
 #endif
 
-/*
- * DEBUG
- */
-
-#undef TX4927_IRQ_DEBUG
-
-#ifdef TX4927_IRQ_DEBUG
-#define TX4927_IRQ_NONE        0x00000000
-
-#define TX4927_IRQ_INFO        ( 1 <<  0 )
-#define TX4927_IRQ_WARN        ( 1 <<  1 )
-#define TX4927_IRQ_EROR        ( 1 <<  2 )
-
-#define TX4927_IRQ_INIT        ( 1 <<  5 )
-#define TX4927_IRQ_NEST1       ( 1 <<  6 )
-#define TX4927_IRQ_NEST2       ( 1 <<  7 )
-#define TX4927_IRQ_NEST3       ( 1 <<  8 )
-#define TX4927_IRQ_NEST4       ( 1 <<  9 )
-
-#define TX4927_IRQ_CP0_INIT     ( 1 << 10 )
-#define TX4927_IRQ_CP0_ENABLE   ( 1 << 13 )
-#define TX4927_IRQ_CP0_DISABLE  ( 1 << 14 )
-
-#define TX4927_IRQ_PIC_INIT     ( 1 << 20 )
-#define TX4927_IRQ_PIC_ENABLE   ( 1 << 23 )
-#define TX4927_IRQ_PIC_DISABLE  ( 1 << 24 )
-
-#define TX4927_IRQ_ALL         0xffffffff
-#endif
-
-#ifdef TX4927_IRQ_DEBUG
-static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE
-					  | TX4927_IRQ_INFO
-					  | TX4927_IRQ_WARN | TX4927_IRQ_EROR
-//                                       | TX4927_IRQ_CP0_INIT
-//                                       | TX4927_IRQ_CP0_ENABLE
-//                                       | TX4927_IRQ_CP0_ENDIRQ
-//                                       | TX4927_IRQ_PIC_INIT
-//                                       | TX4927_IRQ_PIC_ENABLE
-//                                       | TX4927_IRQ_PIC_DISABLE
-//                                       | TX4927_IRQ_INIT
-//                                       | TX4927_IRQ_NEST1
-//                                       | TX4927_IRQ_NEST2
-//                                       | TX4927_IRQ_NEST3
-//                                       | TX4927_IRQ_NEST4
-    );
-#endif
-
-#ifdef TX4927_IRQ_DEBUG
-#define TX4927_IRQ_DPRINTK(flag,str...) \
-        if ( (tx4927_irq_debug_flag) & (flag) ) \
-        { \
-           char tmp[100]; \
-           sprintf( tmp, str ); \
-           printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
-        }
-#else
-#define TX4927_IRQ_DPRINTK(flag,str...)
-#endif
-
-/*
- * Forwad definitions for all pic's
- */
-
-static void tx4927_irq_cp0_enable(unsigned int irq);
-static void tx4927_irq_cp0_disable(unsigned int irq);
-
-static void tx4927_irq_pic_enable(unsigned int irq);
-static void tx4927_irq_pic_disable(unsigned int irq);
-
-/*
- * Kernel structs for all pic's
- */
-
-#define TX4927_CP0_NAME "TX4927-CP0"
-static struct irq_chip tx4927_irq_cp0_type = {
-	.name		= TX4927_CP0_NAME,
-	.ack		= tx4927_irq_cp0_disable,
-	.mask		= tx4927_irq_cp0_disable,
-	.mask_ack	= tx4927_irq_cp0_disable,
-	.unmask		= tx4927_irq_cp0_enable,
-};
-
-#define TX4927_PIC_NAME "TX4927-PIC"
-static struct irq_chip tx4927_irq_pic_type = {
-	.name		= TX4927_PIC_NAME,
-	.ack		= tx4927_irq_pic_disable,
-	.mask		= tx4927_irq_pic_disable,
-	.mask_ack	= tx4927_irq_pic_disable,
-	.unmask		= tx4927_irq_pic_enable,
-};
-
-#define TX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
-static struct irqaction tx4927_irq_pic_action =
-TX4927_PIC_ACTION(TX4927_PIC_NAME);
-
-#define CCP0_STATUS 12
-#define CCP0_CAUSE 13
-
-/*
- * Functions for cp0
- */
-
-#define tx4927_irq_cp0_mask(irq) ( 1 << ( irq-TX4927_IRQ_CP0_BEG+8 ) )
-
-static void
-tx4927_irq_cp0_modify(unsigned cp0_reg, unsigned clr_bits, unsigned set_bits)
-{
-	unsigned long val = 0;
-
-	switch (cp0_reg) {
-	case CCP0_STATUS:
-		val = read_c0_status();
-		break;
-
-	case CCP0_CAUSE:
-		val = read_c0_cause();
-		break;
-
-	}
-
-	val &= (~clr_bits);
-	val |= (set_bits);
-
-	switch (cp0_reg) {
-	case CCP0_STATUS:{
-			write_c0_status(val);
-			break;
-		}
-	case CCP0_CAUSE:{
-			write_c0_cause(val);
-			break;
-		}
-	}
-}
-
-static void __init tx4927_irq_cp0_init(void)
-{
-	int i;
-
-	TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_INIT, "beg=%d end=%d\n",
-			   TX4927_IRQ_CP0_BEG, TX4927_IRQ_CP0_END);
-
-	for (i = TX4927_IRQ_CP0_BEG; i <= TX4927_IRQ_CP0_END; i++)
-		set_irq_chip_and_handler(i, &tx4927_irq_cp0_type,
-					 handle_level_irq);
-}
-
-static void tx4927_irq_cp0_enable(unsigned int irq)
-{
-	TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENABLE, "irq=%d \n", irq);
-
-	tx4927_irq_cp0_modify(CCP0_STATUS, 0, tx4927_irq_cp0_mask(irq));
-}
-
-static void tx4927_irq_cp0_disable(unsigned int irq)
-{
-	TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_DISABLE, "irq=%d \n", irq);
-
-	tx4927_irq_cp0_modify(CCP0_STATUS, tx4927_irq_cp0_mask(irq), 0);
-}
-
-/*
- * Functions for pic
- */
-u32 tx4927_irq_pic_addr(int irq)
-{
-	/* MVMCP -- need to formulize this */
-	irq -= TX4927_IRQ_PIC_BEG;
-	switch (irq) {
-	case 17:
-	case 16:
-	case 1:
-	case 0:
-		return (0xff1ff610);
-
-	case 19:
-	case 18:
-	case 3:
-	case 2:
-		return (0xff1ff614);
-
-	case 21:
-	case 20:
-	case 5:
-	case 4:
-		return (0xff1ff618);
-
-	case 23:
-	case 22:
-	case 7:
-	case 6:
-		return (0xff1ff61c);
-
-	case 25:
-	case 24:
-	case 9:
-	case 8:
-		return (0xff1ff620);
-
-	case 27:
-	case 26:
-	case 11:
-	case 10:
-		return (0xff1ff624);
-
-	case 29:
-	case 28:
-	case 13:
-	case 12:
-		return (0xff1ff628);
-
-	case 31:
-	case 30:
-	case 15:
-	case 14:
-		return (0xff1ff62c);
-
-	}
-	return (0);
-}
-
-u32 tx4927_irq_pic_mask(int irq)
-{
-	/* MVMCP -- need to formulize this */
-	irq -= TX4927_IRQ_PIC_BEG;
-	switch (irq) {
-	case 31:
-	case 29:
-	case 27:
-	case 25:
-	case 23:
-	case 21:
-	case 19:
-	case 17:{
-			return (0x07000000);
-		}
-	case 30:
-	case 28:
-	case 26:
-	case 24:
-	case 22:
-	case 20:
-	case 18:
-	case 16:{
-			return (0x00070000);
-		}
-	case 15:
-	case 13:
-	case 11:
-	case 9:
-	case 7:
-	case 5:
-	case 3:
-	case 1:{
-			return (0x00000700);
-		}
-	case 14:
-	case 12:
-	case 10:
-	case 8:
-	case 6:
-	case 4:
-	case 2:
-	case 0:{
-			return (0x00000007);
-		}
-	}
-	return (0x00000000);
-}
-
-static void tx4927_irq_pic_modify(unsigned pic_reg, unsigned clr_bits,
-	unsigned set_bits)
-{
-	unsigned long val = 0;
-
-	val = TX4927_RD(pic_reg);
-	val &= (~clr_bits);
-	val |= (set_bits);
-	TX4927_WR(pic_reg, val);
-}
-
-static void __init tx4927_irq_pic_init(void)
-{
-	int i;
-
-	TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_INIT, "beg=%d end=%d\n",
-			   TX4927_IRQ_PIC_BEG, TX4927_IRQ_PIC_END);
-
-	for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++)
-		set_irq_chip_and_handler(i, &tx4927_irq_pic_type,
-					 handle_level_irq);
-
-	setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action);
-
-	TX4927_WR(0xff1ff640, 0x6);	/* irq level mask -- only accept hightest */
-	TX4927_WR(0xff1ff600, TX4927_RD(0xff1ff600) | 0x1);	/* irq enable */
-}
-
-static void tx4927_irq_pic_enable(unsigned int irq)
-{
-	TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENABLE, "irq=%d\n", irq);
-
-	tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), 0,
-			      tx4927_irq_pic_mask(irq));
-}
-
-static void tx4927_irq_pic_disable(unsigned int irq)
-{
-	TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_DISABLE, "irq=%d\n", irq);
-
-	tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq),
-			      tx4927_irq_pic_mask(irq), 0);
-}
-
-/*
- * Main init functions
- */
 void __init tx4927_irq_init(void)
 {
-	TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "-\n");
-
-	TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "=Calling tx4927_irq_cp0_init()\n");
-	tx4927_irq_cp0_init();
-
-	TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "=Calling tx4927_irq_pic_init()\n");
-	tx4927_irq_pic_init();
-
-	TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "+\n");
-}
-
-static int tx4927_irq_nested(void)
-{
-	int sw_irq = 0;
-	u32 level2;
-
-	TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST1, "-\n");
-
-	level2 = TX4927_RD(0xff1ff6a0);
-	TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST2, "=level2a=0x%x\n", level2);
-
-	if ((level2 & 0x10000) == 0) {
-		level2 &= 0x1f;
-		TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST3, "=level2b=0x%x\n", level2);
-
-		sw_irq = TX4927_IRQ_PIC_BEG + level2;
-		TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST3, "=sw_irq=%d\n", sw_irq);
-
-		if (sw_irq == 27) {
-			TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST4, "=irq-%d\n",
-					   sw_irq);
-
-#ifdef CONFIG_TOSHIBA_RBTX4927
-			{
-				sw_irq = toshiba_rbtx4927_irq_nested(sw_irq);
-			}
-#endif
-
-			TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST4, "=irq+%d\n",
-					   sw_irq);
-		}
-	}
-
-	TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST2, "=sw_irq=%d\n", sw_irq);
-
-	TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST1, "+\n");
-
-	return (sw_irq);
+	mips_cpu_irq_init();
+	txx9_irq_init(TX4927_IRC_REG);
+	set_irq_chained_handler(TX4927_IRQ_NEST_PIC_ON_CP0, handle_simple_irq);
 }
 
 asmlinkage void plat_irq_dispatch(void)
@@ -424,9 +46,12 @@ asmlinkage void plat_irq_dispatch(void)
 	if (pending & STATUSF_IP7)			/* cpu timer */
 		do_IRQ(TX4927_IRQ_CPU_TIMER);
 	else if (pending & STATUSF_IP2) {		/* tx4927 pic */
-		unsigned int irq = tx4927_irq_nested();
-
-		if (unlikely(irq == 0)) {
+		int irq = txx9_irq();
+#ifdef CONFIG_TOSHIBA_RBTX4927
+		if (irq == TX4927_IRQ_NEST_EXT_ON_PIC)
+			irq = toshiba_rbtx4927_irq_nested(irq);
+#endif
+		if (unlikely(irq < 0)) {
 			spurious_interrupt();
 			return;
 		}
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
index e265fcd31b60..9607ad5e734a 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
@@ -133,6 +133,7 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
 #include <linux/bootmem.h>
 #include <linux/blkdev.h>
 #ifdef CONFIG_TOSHIBA_FPCIB0
+#include <asm/i8259.h>
 #include <asm/tx4927/smsc_fdc37m81x.h>
 #endif
 #include <asm/tx4927/toshiba_rbtx4927.h>
@@ -151,11 +152,6 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
 #define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE    ( 1 << 13 )
 #define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE   ( 1 << 14 )
 
-#define TOSHIBA_RBTX4927_IRQ_ISA_INIT      ( 1 << 20 )
-#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE    ( 1 << 23 )
-#define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE   ( 1 << 24 )
-#define TOSHIBA_RBTX4927_IRQ_ISA_MASK      ( 1 << 25 )
-
 #define TOSHIBA_RBTX4927_SETUP_ALL         0xffffffff
 #endif
 
@@ -167,10 +163,6 @@ static const u32 toshiba_rbtx4927_irq_debug_flag =
 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_INIT
 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
 //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
-//                                                 | TOSHIBA_RBTX4927_IRQ_ISA_INIT
-//                                                 | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
-//                                                 | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
-//                                                 | TOSHIBA_RBTX4927_IRQ_ISA_MASK
     );
 #endif
 
@@ -196,33 +188,14 @@ static const u32 toshiba_rbtx4927_irq_debug_flag =
 #define TOSHIBA_RBTX4927_IRQ_IOC_BEG  ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG)	/* 56 */
 #define TOSHIBA_RBTX4927_IRQ_IOC_END  ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END)	/* 63 */
 
-
-#define TOSHIBA_RBTX4927_IRQ_ISA_BEG MI8259_IRQ_ISA_BEG
-#define TOSHIBA_RBTX4927_IRQ_ISA_END MI8259_IRQ_ISA_END
-#define TOSHIBA_RBTX4927_IRQ_ISA_MID ((TOSHIBA_RBTX4927_IRQ_ISA_BEG+TOSHIBA_RBTX4927_IRQ_ISA_END+1)/2)
-
-
 #define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC
 #define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2)
-#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA (TOSHIBA_RBTX4927_IRQ_ISA_BEG+2)
 
 extern int tx4927_using_backplane;
 
-#ifdef CONFIG_TOSHIBA_FPCIB0
-extern void enable_8259A_irq(unsigned int irq);
-extern void disable_8259A_irq(unsigned int irq);
-extern void mask_and_ack_8259A(unsigned int irq);
-#endif
-
 static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
 static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
 
-#ifdef CONFIG_TOSHIBA_FPCIB0
-static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq);
-static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq);
-static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq);
-#endif
-
 #define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
 static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
 	.name = TOSHIBA_RBTX4927_IOC_NAME,
@@ -235,18 +208,6 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
 #define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006
 
 
-#ifdef CONFIG_TOSHIBA_FPCIB0
-#define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA"
-static struct irq_chip toshiba_rbtx4927_irq_isa_type = {
-	.name = TOSHIBA_RBTX4927_ISA_NAME,
-	.ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
-	.mask = toshiba_rbtx4927_irq_isa_disable,
-	.mask_ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
-	.unmask = toshiba_rbtx4927_irq_isa_enable,
-};
-#endif
-
-
 u32 bit2num(u32 num)
 {
 	u32 i;
@@ -271,31 +232,10 @@ int toshiba_rbtx4927_irq_nested(int sw_irq)
 		}
 	}
 #ifdef CONFIG_TOSHIBA_FPCIB0
-	{
-		if (tx4927_using_backplane) {
-			u32 level4;
-			u32 level5;
-			outb(0x0A, 0x20);
-			level4 = inb(0x20) & 0xff;
-			if (level4) {
-				sw_irq =
-				    TOSHIBA_RBTX4927_IRQ_ISA_BEG +
-				    bit2num(level4);
-				if (sw_irq !=
-				    TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA) {
-					goto RETURN;
-				}
-			}
-
-			outb(0x0A, 0xA0);
-			level5 = inb(0xA0) & 0xff;
-			if (level5) {
-				sw_irq =
-				    TOSHIBA_RBTX4927_IRQ_ISA_MID +
-				    bit2num(level5);
-				goto RETURN;
-			}
-		}
+	if (tx4927_using_backplane) {
+		int irq = i8259_irq();
+		if (irq >= 0)
+			sw_irq = irq;
 	}
 #endif
 
@@ -307,12 +247,6 @@ int toshiba_rbtx4927_irq_nested(int sw_irq)
 #define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, IRQF_SHARED, CPU_MASK_NONE, s, NULL, NULL }
 static struct irqaction toshiba_rbtx4927_irq_ioc_action =
 TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME);
-#ifdef CONFIG_TOSHIBA_FPCIB0
-static struct irqaction toshiba_rbtx4927_irq_isa_master =
-TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/M");
-static struct irqaction toshiba_rbtx4927_irq_isa_slave =
-TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/S");
-#endif
 
 
 /**********************************************************************************/
@@ -378,92 +312,6 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
 }
 
 
-/**********************************************************************************/
-/* Functions for isa                                                              */
-/**********************************************************************************/
-
-
-#ifdef CONFIG_TOSHIBA_FPCIB0
-static void __init toshiba_rbtx4927_irq_isa_init(void)
-{
-	int i;
-
-	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_INIT,
-				     "beg=%d end=%d\n",
-				     TOSHIBA_RBTX4927_IRQ_ISA_BEG,
-				     TOSHIBA_RBTX4927_IRQ_ISA_END);
-
-	for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG;
-	     i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++)
-		set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_isa_type,
-					 handle_level_irq);
-
-	setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC,
-		  &toshiba_rbtx4927_irq_isa_master);
-	setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA,
-		  &toshiba_rbtx4927_irq_isa_slave);
-
-	/* make sure we are looking at IRR (not ISR) */
-	outb(0x0A, 0x20);
-	outb(0x0A, 0xA0);
-}
-#endif
-
-
-#ifdef CONFIG_TOSHIBA_FPCIB0
-static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq)
-{
-	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENABLE,
-				     "irq=%d\n", irq);
-
-	if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
-	    || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
-		TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
-					     "bad irq=%d\n", irq);
-		panic("\n");
-	}
-
-	enable_8259A_irq(irq);
-}
-#endif
-
-
-#ifdef CONFIG_TOSHIBA_FPCIB0
-static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq)
-{
-	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_DISABLE,
-				     "irq=%d\n", irq);
-
-	if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
-	    || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
-		TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
-					     "bad irq=%d\n", irq);
-		panic("\n");
-	}
-
-	disable_8259A_irq(irq);
-}
-#endif
-
-
-#ifdef CONFIG_TOSHIBA_FPCIB0
-static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq)
-{
-	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_MASK,
-				     "irq=%d\n", irq);
-
-	if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
-	    || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
-		TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
-					     "bad irq=%d\n", irq);
-		panic("\n");
-	}
-
-	mask_and_ack_8259A(irq);
-}
-#endif
-
-
 void __init arch_init_irq(void)
 {
 	extern void tx4927_irq_init(void);
@@ -471,12 +319,11 @@ void __init arch_init_irq(void)
 	tx4927_irq_init();
 	toshiba_rbtx4927_irq_ioc_init();
 #ifdef CONFIG_TOSHIBA_FPCIB0
-	{
-		if (tx4927_using_backplane) {
-			toshiba_rbtx4927_irq_isa_init();
-		}
-	}
+	if (tx4927_using_backplane)
+		init_i8259_irqs();
 #endif
+	/* Onboard 10M Ether: High Active */
+	set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH);
 
 	wbflush();
 }
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
index ea5a70b252a0..3e84237abe63 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
@@ -151,7 +151,6 @@ unsigned long mips_memory_upper;
 static int tx4927_ccfg_toeon = 1;
 static int tx4927_pcic_trdyto = 0;	/* default: disabled */
 unsigned long tx4927_ce_base[8];
-void tx4927_pci_setup(void);
 void tx4927_reset_pci_pcic(void);
 int tx4927_pci66 = 0;		/* 0:auto */
 #endif
@@ -442,7 +441,7 @@ arch_initcall(tx4927_pcibios_init);
 extern struct resource pci_io_resource;
 extern struct resource pci_mem_resource;
 
-void tx4927_pci_setup(void)
+void __init tx4927_pci_setup(void)
 {
 	static int called = 0;
 	extern unsigned int tx4927_get_mem_size(void);
@@ -748,12 +747,6 @@ void __init toshiba_rbtx4927_setup(void)
 	}
 #endif
 
-	/* setup irq stuff */
-	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
-				       ":Setting up tx4927 pic.\n");
-	TX4927_WR(0xff1ff604, 0x00000400);	/* irq trigger */
-	TX4927_WR(0xff1ff608, 0x00000000);	/* irq trigger */
-
 	/* setup serial stuff */
 	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 				       ":Setting up tx4927 sio.\n");
@@ -915,7 +908,7 @@ void __init toshiba_rbtx4927_setup(void)
 			req.iotype = UPIO_MEM;
 			req.membase = (char *)(0xff1ff300 + i * 0x100);
 			req.mapbase = 0xff1ff300 + i * 0x100;
-			req.irq = 32 + i;
+			req.irq = TX4927_IRQ_PIC_BEG + 8 + i;
 			req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
 			req.uartclk = 50000000;
 			early_serial_txx9_setup(&req);
diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c
index 3a2dbfc25014..c059b899d120 100644
--- a/arch/mips/tx4938/common/irq.c
+++ b/arch/mips/tx4938/common/irq.c
@@ -11,284 +11,21 @@
  *
  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  */
-#include <linux/errno.h>
 #include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/types.h>
 #include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/timex.h>
-#include <linux/slab.h>
-#include <linux/random.h>
-#include <linux/irq.h>
-#include <asm/bitops.h>
-#include <asm/bootinfo.h>
-#include <asm/io.h>
-#include <asm/irq.h>
+#include <asm/irq_cpu.h>
 #include <asm/mipsregs.h>
-#include <asm/system.h>
-#include <asm/wbflush.h>
 #include <asm/tx4938/rbtx4938.h>
 
-/**********************************************************************************/
-/* Forwad definitions for all pic's                                               */
-/**********************************************************************************/
-
-static void tx4938_irq_cp0_enable(unsigned int irq);
-static void tx4938_irq_cp0_disable(unsigned int irq);
-
-static void tx4938_irq_pic_enable(unsigned int irq);
-static void tx4938_irq_pic_disable(unsigned int irq);
-
-/**********************************************************************************/
-/* Kernel structs for all pic's                                                   */
-/**********************************************************************************/
-
-#define TX4938_CP0_NAME "TX4938-CP0"
-static struct irq_chip tx4938_irq_cp0_type = {
-	.name = TX4938_CP0_NAME,
-	.ack = tx4938_irq_cp0_disable,
-	.mask = tx4938_irq_cp0_disable,
-	.mask_ack = tx4938_irq_cp0_disable,
-	.unmask = tx4938_irq_cp0_enable,
-};
-
-#define TX4938_PIC_NAME "TX4938-PIC"
-static struct irq_chip tx4938_irq_pic_type = {
-	.name = TX4938_PIC_NAME,
-	.ack = tx4938_irq_pic_disable,
-	.mask = tx4938_irq_pic_disable,
-	.mask_ack = tx4938_irq_pic_disable,
-	.unmask = tx4938_irq_pic_enable,
-};
-
-static struct irqaction tx4938_irq_pic_action = {
-	.handler = no_action,
-	.flags = 0,
-	.mask = CPU_MASK_NONE,
-	.name = TX4938_PIC_NAME
-};
-
-/**********************************************************************************/
-/* Functions for cp0                                                              */
-/**********************************************************************************/
-
-#define tx4938_irq_cp0_mask(irq) ( 1 << ( irq-TX4938_IRQ_CP0_BEG+8 ) )
-
-static void __init
-tx4938_irq_cp0_init(void)
-{
-	int i;
-
-	for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++)
-		set_irq_chip_and_handler(i, &tx4938_irq_cp0_type,
-					 handle_level_irq);
-}
-
-static void
-tx4938_irq_cp0_enable(unsigned int irq)
-{
-	set_c0_status(tx4938_irq_cp0_mask(irq));
-}
-
-static void
-tx4938_irq_cp0_disable(unsigned int irq)
-{
-	clear_c0_status(tx4938_irq_cp0_mask(irq));
-}
-
-/**********************************************************************************/
-/* Functions for pic                                                              */
-/**********************************************************************************/
-
-u32
-tx4938_irq_pic_addr(int irq)
-{
-	/* MVMCP -- need to formulize this */
-	irq -= TX4938_IRQ_PIC_BEG;
-
-	switch (irq) {
-	case 17:
-	case 16:
-	case 1:
-	case 0:{
-			return (TX4938_MKA(TX4938_IRC_IRLVL0));
-		}
-	case 19:
-	case 18:
-	case 3:
-	case 2:{
-			return (TX4938_MKA(TX4938_IRC_IRLVL1));
-		}
-	case 21:
-	case 20:
-	case 5:
-	case 4:{
-			return (TX4938_MKA(TX4938_IRC_IRLVL2));
-		}
-	case 23:
-	case 22:
-	case 7:
-	case 6:{
-			return (TX4938_MKA(TX4938_IRC_IRLVL3));
-		}
-	case 25:
-	case 24:
-	case 9:
-	case 8:{
-			return (TX4938_MKA(TX4938_IRC_IRLVL4));
-		}
-	case 27:
-	case 26:
-	case 11:
-	case 10:{
-			return (TX4938_MKA(TX4938_IRC_IRLVL5));
-		}
-	case 29:
-	case 28:
-	case 13:
-	case 12:{
-			return (TX4938_MKA(TX4938_IRC_IRLVL6));
-		}
-	case 31:
-	case 30:
-	case 15:
-	case 14:{
-			return (TX4938_MKA(TX4938_IRC_IRLVL7));
-		}
-	}
-
-	return 0;
-}
-
-u32
-tx4938_irq_pic_mask(int irq)
-{
-	/* MVMCP -- need to formulize this */
-	irq -= TX4938_IRQ_PIC_BEG;
-
-	switch (irq) {
-	case 31:
-	case 29:
-	case 27:
-	case 25:
-	case 23:
-	case 21:
-	case 19:
-	case 17:{
-			return (0x07000000);
-		}
-	case 30:
-	case 28:
-	case 26:
-	case 24:
-	case 22:
-	case 20:
-	case 18:
-	case 16:{
-			return (0x00070000);
-		}
-	case 15:
-	case 13:
-	case 11:
-	case 9:
-	case 7:
-	case 5:
-	case 3:
-	case 1:{
-			return (0x00000700);
-		}
-	case 14:
-	case 12:
-	case 10:
-	case 8:
-	case 6:
-	case 4:
-	case 2:
-	case 0:{
-			return (0x00000007);
-		}
-	}
-	return 0x00000000;
-}
-
-static void
-tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits)
-{
-	unsigned long val = 0;
-
-	val = TX4938_RD(pic_reg);
-	val &= (~clr_bits);
-	val |= (set_bits);
-	TX4938_WR(pic_reg, val);
-	mmiowb();
-	TX4938_RD(pic_reg);
-}
-
-static void __init
-tx4938_irq_pic_init(void)
-{
-	int i;
-
-	for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++)
-		set_irq_chip_and_handler(i, &tx4938_irq_pic_type,
-					 handle_level_irq);
-
-	setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action);
-
-	TX4938_WR(0xff1ff640, 0x6);	/* irq level mask -- only accept hightest */
-	TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1);	/* irq enable */
-}
-
-static void
-tx4938_irq_pic_enable(unsigned int irq)
-{
-	tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0,
-			      tx4938_irq_pic_mask(irq));
-}
-
-static void
-tx4938_irq_pic_disable(unsigned int irq)
-{
-	tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq),
-			      tx4938_irq_pic_mask(irq), 0);
-}
-
-/**********************************************************************************/
-/* Main init functions                                                            */
-/**********************************************************************************/
-
 void __init
 tx4938_irq_init(void)
 {
-	tx4938_irq_cp0_init();
-	tx4938_irq_pic_init();
+	mips_cpu_irq_init();
+	txx9_irq_init(TX4938_IRC_REG);
+	set_irq_chained_handler(TX4938_IRQ_NEST_PIC_ON_CP0, handle_simple_irq);
 }
 
-int
-tx4938_irq_nested(void)
-{
-	int sw_irq = 0;
-	u32 level2;
-
-	level2 = TX4938_RD(0xff1ff6a0);
-	if ((level2 & 0x10000) == 0) {
-		level2 &= 0x1f;
-		sw_irq = TX4938_IRQ_PIC_BEG + level2;
-		if (sw_irq == 26) {
-			{
-				extern int toshiba_rbtx4938_irq_nested(int sw_irq);
-				sw_irq = toshiba_rbtx4938_irq_nested(sw_irq);
-			}
-		}
-	}
-
-	wbflush();
-	return sw_irq;
-}
+int toshiba_rbtx4938_irq_nested(int irq);
 
 asmlinkage void plat_irq_dispatch(void)
 {
@@ -297,8 +34,10 @@ asmlinkage void plat_irq_dispatch(void)
 	if (pending & STATUSF_IP7)
 		do_IRQ(TX4938_IRQ_CPU_TIMER);
 	else if (pending & STATUSF_IP2) {
-		int irq = tx4938_irq_nested();
-		if (irq)
+		int irq = txx9_irq();
+		if (irq == TX4938_IRQ_PIC_BEG + TX4938_IR_INT(0))
+			irq = toshiba_rbtx4938_irq_nested(irq);
+		if (irq >= 0)
 			do_IRQ(irq);
 		else
 			spurious_interrupt();
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
index 91aea7aff515..f00185017e80 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
@@ -181,7 +181,7 @@ void __init arch_init_irq(void)
 	tx4938_irq_init();
 	toshiba_rbtx4938_irq_ioc_init();
 	/* Onboard 10M Ether: High Active */
-	TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000040);
+	set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
 
 	wbflush();
 }
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
index f9ad482749e4..57f3c705d082 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
@@ -773,10 +773,6 @@ void __init tx4938_board_setup(void)
 		 txboard_add_phys_region(base, size);
 	}
 
-	/* IRC */
-	/* disable interrupt control */
-	tx4938_ircptr->cer = 0;
-
 	/* TMR */
 	/* disable all timers */
 	for (i = 0; i < TX4938_NR_TMR; i++) {
@@ -875,9 +871,6 @@ void __init toshiba_rbtx4938_setup(void)
 	if (txx9_master_clock == 0)
 		txx9_master_clock = 25000000; /* 25MHz */
 	tx4938_board_setup();
-	/* setup irq stuff */
-	TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000000);	/* irq trigger */
-	TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM1), 0x00000000);	/* irq trigger */
 	/* setup serial stuff */
 	TX4938_WR(0xff1ff314, 0x00000000);	/* h/w flow control off */
 	TX4938_WR(0xff1ff414, 0x00000000);	/* h/w flow control off */
@@ -897,7 +890,7 @@ void __init toshiba_rbtx4938_setup(void)
 			req.iotype = UPIO_MEM;
 			req.membase = (char *)(0xff1ff300 + i * 0x100);
 			req.mapbase = 0xff1ff300 + i * 0x100;
-			req.irq = 32 + i;
+			req.irq = RBTX4938_IRQ_IRC_SIO(i);
 			req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
 			req.uartclk = 50000000;
 			early_serial_txx9_setup(&req);
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h
index 958e29706e2d..b2dc35f56181 100644
--- a/include/asm-mips/jmr3927/jmr3927.h
+++ b/include/asm-mips/jmr3927/jmr3927.h
@@ -13,6 +13,7 @@
 #include <asm/jmr3927/tx3927.h>
 #include <asm/addrspace.h>
 #include <asm/system.h>
+#include <asm/txx9irq.h>
 
 /* CS */
 #define JMR3927_ROMCE0	0x1fc00000	/* 4M */
@@ -115,7 +116,7 @@
 #define JMR3927_NR_IRQ_IRC	16	/* On-Chip IRC */
 #define JMR3927_NR_IRQ_IOC	8	/* PCI/MODEM/INT[6:7] */
 
-#define JMR3927_IRQ_IRC	16
+#define JMR3927_IRQ_IRC	TXX9_IRQ_BASE
 #define JMR3927_IRQ_IOC	(JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
 #define JMR3927_IRQ_END	(JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
 
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h
index 0b9073bfb759..4be2f25f70dd 100644
--- a/include/asm-mips/jmr3927/tx3927.h
+++ b/include/asm-mips/jmr3927/tx3927.h
@@ -50,21 +50,6 @@ struct tx3927_dma_reg {
 	volatile unsigned long unused0;
 };
 
-struct tx3927_irc_reg {
-	volatile unsigned long cer;
-	volatile unsigned long cr[2];
-	volatile unsigned long unused0;
-	volatile unsigned long ilr[8];
-	volatile unsigned long unused1[4];
-	volatile unsigned long imr;
-	volatile unsigned long unused2[7];
-	volatile unsigned long scr;
-	volatile unsigned long unused3[7];
-	volatile unsigned long ssr;
-	volatile unsigned long unused4[7];
-	volatile unsigned long csr;
-};
-
 #include <asm/byteorder.h>
 
 #ifdef __BIG_ENDIAN
@@ -225,26 +210,6 @@ struct tx3927_ccfg_reg {
 /*
  * IRC
  */
-#define TX3927_IR_MAX_LEVEL	7
-
-/* IRCER : Int. Control Enable */
-#define TX3927_IRCER_ICE	0x00000001
-
-/* IRCR : Int. Control */
-#define TX3927_IRCR_LOW	0x00000000
-#define TX3927_IRCR_HIGH	0x00000001
-#define TX3927_IRCR_DOWN	0x00000002
-#define TX3927_IRCR_UP	0x00000003
-
-/* IRSCR : Int. Status Control */
-#define TX3927_IRSCR_EIClrE	0x00000100
-#define TX3927_IRSCR_EIClr_MASK	0x0000000f
-
-/* IRCSR : Int. Current Status */
-#define TX3927_IRCSR_IF	0x00010000
-#define TX3927_IRCSR_ILV_MASK	0x00000700
-#define TX3927_IRCSR_IVL_MASK	0x0000001f
-
 #define TX3927_IR_INT0	0
 #define TX3927_IR_INT1	1
 #define TX3927_IR_INT2	2
@@ -347,7 +312,6 @@ struct tx3927_ccfg_reg {
 #define tx3927_sdramcptr	((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
 #define tx3927_romcptr		((struct tx3927_romc_reg *)TX3927_ROMC_REG)
 #define tx3927_dmaptr		((struct tx3927_dma_reg *)TX3927_DMA_REG)
-#define tx3927_ircptr		((struct tx3927_irc_reg *)TX3927_IRC_REG)
 #define tx3927_pcicptr		((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
 #define tx3927_ccfgptr		((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
 #define tx3927_tmrptr(ch)	((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h
index 5dc40a867774..a60649569c2c 100644
--- a/include/asm-mips/tx4927/toshiba_rbtx4927.h
+++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h
@@ -50,7 +50,7 @@
 
 
 #define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET)
-#define RBTX4927_RTL_8019_IRQ  (29)
+#define RBTX4927_RTL_8019_IRQ  (TX4927_IRQ_PIC_BEG + 5)
 
 int toshiba_rbtx4927_irq_nested(int sw_irq);
 
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
index de85bd2245f7..4bd4368e188c 100644
--- a/include/asm-mips/tx4927/tx4927.h
+++ b/include/asm-mips/tx4927/tx4927.h
@@ -28,6 +28,7 @@
 #define __ASM_TX4927_TX4927_H
 
 #include <asm/tx4927/tx4927_mips.h>
+#include <asm/txx9irq.h>
 
 /*
  This register naming came from the integrated CPU/controller name TX4927
@@ -421,32 +422,6 @@
 #define TX4927_PIO_LIMIT                0xf50f
 
 
-/* TX4927 Interrupt Controller (32-bit registers) */
-#define TX4927_IRC_BASE                 0xf510
-#define TX4927_IRC_IRFLAG0              0xf510
-#define TX4927_IRC_IRFLAG1              0xf514
-#define TX4927_IRC_IRPOL                0xf518
-#define TX4927_IRC_IRRCNT               0xf51c
-#define TX4927_IRC_IRMASKINT            0xf520
-#define TX4927_IRC_IRMASKEXT            0xf524
-#define TX4927_IRC_IRDEN                0xf600
-#define TX4927_IRC_IRDM0                0xf604
-#define TX4927_IRC_IRDM1                0xf608
-#define TX4927_IRC_IRLVL0               0xf610
-#define TX4927_IRC_IRLVL1               0xf614
-#define TX4927_IRC_IRLVL2               0xf618
-#define TX4927_IRC_IRLVL3               0xf61c
-#define TX4927_IRC_IRLVL4               0xf620
-#define TX4927_IRC_IRLVL5               0xf624
-#define TX4927_IRC_IRLVL6               0xf628
-#define TX4927_IRC_IRLVL7               0xf62c
-#define TX4927_IRC_IRMSK                0xf640
-#define TX4927_IRC_IREDC                0xf660
-#define TX4927_IRC_IRPND                0xf680
-#define TX4927_IRC_IRCS                 0xf6a0
-#define TX4927_IRC_LIMIT                0xf6ff
-
-
 /* TX4927 AC-link controller (32-bit registers) */
 #define TX4927_ACLC_BASE                0xf700
 #define TX4927_ACLC_ACCTLEN             0xf700
@@ -493,25 +468,11 @@
 #define TX4927_WR( reg, val ) TX4927_WR32( reg, val )
 
 
+#define TX4927_IRQ_CP0_BEG  MIPS_CPU_IRQ_BASE
+#define TX4927_IRQ_CP0_END  (MIPS_CPU_IRQ_BASE + 8 - 1)
 
-
-
-#define MI8259_IRQ_ISA_RAW_BEG   0    /* optional backplane i8259 */
-#define MI8259_IRQ_ISA_RAW_END  15
-#define TX4927_IRQ_CP0_RAW_BEG   0    /* tx4927 cpu built-in cp0 */
-#define TX4927_IRQ_CP0_RAW_END   7
-#define TX4927_IRQ_PIC_RAW_BEG   0    /* tx4927 cpu build-in pic */
-#define TX4927_IRQ_PIC_RAW_END  31
-
-
-#define MI8259_IRQ_ISA_BEG                          MI8259_IRQ_ISA_RAW_BEG   /*  0 */
-#define MI8259_IRQ_ISA_END                          MI8259_IRQ_ISA_RAW_END   /* 15 */
-
-#define TX4927_IRQ_CP0_BEG  ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_BEG)  /* 16 */
-#define TX4927_IRQ_CP0_END  ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_END)  /* 23 */
-
-#define TX4927_IRQ_PIC_BEG  ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_BEG)  /* 24 */
-#define TX4927_IRQ_PIC_END  ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_END)  /* 55 */
+#define TX4927_IRQ_PIC_BEG  TXX9_IRQ_BASE
+#define TX4927_IRQ_PIC_END  (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
 
 
 #define TX4927_IRQ_USER0            (TX4927_IRQ_CP0_BEG+0)
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
index 66c064690f41..f98b2bb719d5 100644
--- a/include/asm-mips/tx4927/tx4927_pci.h
+++ b/include/asm-mips/tx4927/tx4927_pci.h
@@ -48,7 +48,7 @@
 #define TX4927_PCI_CLK_ACK      0x04
 #define TX4927_PCI_CLK_ACE      0x02
 #define TX4927_PCI_CLK_ENDIAN   0x01
-#define TX4927_NR_IRQ_LOCAL     (8+16)
+#define TX4927_NR_IRQ_LOCAL     TX4927_IRQ_PIC_BEG
 #define TX4927_NR_IRQ_IRC       32      /* On-Chip IRC */
 
 #define TX4927_IR_PCIC  	16
@@ -99,21 +99,6 @@ struct tx4927_ccfg_reg {
         volatile unsigned long long ramp;
 };
 
-struct tx4927_irc_reg {
-        volatile unsigned long cer;
-        volatile unsigned long cr[2];
-        volatile unsigned long unused0;
-        volatile unsigned long ilr[8];
-        volatile unsigned long unused1[4];
-        volatile unsigned long imr;
-        volatile unsigned long unused2[7];
-        volatile unsigned long scr;
-        volatile unsigned long unused3[7];
-        volatile unsigned long ssr;
-        volatile unsigned long unused4[7];
-        volatile unsigned long csr;
-};
-
 struct tx4927_pcic_reg {
         volatile unsigned long pciid;
         volatile unsigned long pcistatus;
@@ -182,11 +167,6 @@ struct tx4927_pcic_reg {
 
 #endif /* _LANGUAGE_ASSEMBLY */
 
-/* IRCSR : Int. Current Status */
-#define TX4927_IRCSR_IF         0x00010000
-#define TX4927_IRCSR_ILV_MASK   0x00000700
-#define TX4927_IRCSR_IVL_MASK   0x0000001f
-
 /*
  * PCIC
  */
@@ -278,7 +258,6 @@ struct tx4927_pcic_reg {
 #define tx4927_pcicptr          ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
 #define tx4927_ccfgptr          ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
 #define tx4927_ebuscptr         ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
-#define tx4927_ircptr           ((struct tx4927_irc_reg *)TX4927_IRC_REG)
 
 #endif /* _LANGUAGE_ASSEMBLY */
 
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h
index 74e7d8061e58..b14acb575be2 100644
--- a/include/asm-mips/tx4938/rbtx4938.h
+++ b/include/asm-mips/tx4938/rbtx4938.h
@@ -14,6 +14,7 @@
 
 #include <asm/addrspace.h>
 #include <asm/tx4938/tx4938.h>
+#include <asm/txx9irq.h>
 
 /* CS */
 #define RBTX4938_CE0	0x1c000000	/* 64M */
@@ -123,21 +124,11 @@
 #define RBTX4938_NR_IRQ_IRC	32	/* On-Chip IRC */
 #define RBTX4938_NR_IRQ_IOC	8
 
-#define MI8259_IRQ_ISA_RAW_BEG   0	/* optional backplane i8259 */
-#define MI8259_IRQ_ISA_RAW_END  15
-#define TX4938_IRQ_CP0_RAW_BEG   0	/* tx4938 cpu built-in cp0 */
-#define TX4938_IRQ_CP0_RAW_END   7
-#define TX4938_IRQ_PIC_RAW_BEG   0	/* tx4938 cpu build-in pic */
-#define TX4938_IRQ_PIC_RAW_END  31
+#define TX4938_IRQ_CP0_BEG  MIPS_CPU_IRQ_BASE
+#define TX4938_IRQ_CP0_END  (MIPS_CPU_IRQ_BASE + 8 - 1)
 
-#define MI8259_IRQ_ISA_BEG                          MI8259_IRQ_ISA_RAW_BEG	/*  0 */
-#define MI8259_IRQ_ISA_END                          MI8259_IRQ_ISA_RAW_END	/* 15 */
-
-#define TX4938_IRQ_CP0_BEG  ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_BEG)	/* 16 */
-#define TX4938_IRQ_CP0_END  ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_END)	/* 23 */
-
-#define TX4938_IRQ_PIC_BEG  ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_BEG)	/* 24 */
-#define TX4938_IRQ_PIC_END  ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_END)	/* 55 */
+#define TX4938_IRQ_PIC_BEG  TXX9_IRQ_BASE
+#define TX4938_IRQ_PIC_END  (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
 #define TX4938_IRQ_NEST_EXT_ON_PIC  (TX4938_IRQ_PIC_BEG+2)
 #define TX4938_IRQ_NEST_PIC_ON_CP0  (TX4938_IRQ_CP0_BEG+2)
 #define TX4938_IRQ_USER0            (TX4938_IRQ_CP0_BEG+0)
@@ -192,10 +183,4 @@
 #define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
 #define RBTX4938_RTL_8019_IRQ  (RBTX4938_IRQ_ETHER)
 
-/* IRCR : Int. Control */
-#define TX4938_IRCR_LOW  0x00000000
-#define TX4938_IRCR_HIGH 0x00000001
-#define TX4938_IRCR_DOWN 0x00000002
-#define TX4938_IRCR_UP   0x00000003
-
 #endif /* __ASM_TX_BOARDS_RBTX4938_H */
diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h
index e25b1a0975cb..afdb19813ca1 100644
--- a/include/asm-mips/tx4938/tx4938.h
+++ b/include/asm-mips/tx4938/tx4938.h
@@ -272,20 +272,6 @@ struct tx4938_pio_reg {
 	volatile unsigned long maskcpu;
 	volatile unsigned long maskext;
 };
-struct tx4938_irc_reg {
-	volatile unsigned long cer;
-	volatile unsigned long cr[2];
-	volatile unsigned long unused0;
-	volatile unsigned long ilr[8];
-	volatile unsigned long unused1[4];
-	volatile unsigned long imr;
-	volatile unsigned long unused2[7];
-	volatile unsigned long scr;
-	volatile unsigned long unused3[7];
-	volatile unsigned long ssr;
-	volatile unsigned long unused4[7];
-	volatile unsigned long csr;
-};
 
 struct tx4938_ndfmc_reg {
 	endian_def_l2(unused0, dtr);
@@ -646,39 +632,12 @@ struct tx4938_ccfg_reg {
 #define TX4938_DMA_CSR_DESERR	0x00000002
 #define TX4938_DMA_CSR_SORERR	0x00000001
 
-/* TX4938 Interrupt Controller (32-bit registers) */
-#define TX4938_IRC_BASE                 0xf510
-#define TX4938_IRC_IRFLAG0              0xf510
-#define TX4938_IRC_IRFLAG1              0xf514
-#define TX4938_IRC_IRPOL                0xf518
-#define TX4938_IRC_IRRCNT               0xf51c
-#define TX4938_IRC_IRMASKINT            0xf520
-#define TX4938_IRC_IRMASKEXT            0xf524
-#define TX4938_IRC_IRDEN                0xf600
-#define TX4938_IRC_IRDM0                0xf604
-#define TX4938_IRC_IRDM1                0xf608
-#define TX4938_IRC_IRLVL0               0xf610
-#define TX4938_IRC_IRLVL1               0xf614
-#define TX4938_IRC_IRLVL2               0xf618
-#define TX4938_IRC_IRLVL3               0xf61c
-#define TX4938_IRC_IRLVL4               0xf620
-#define TX4938_IRC_IRLVL5               0xf624
-#define TX4938_IRC_IRLVL6               0xf628
-#define TX4938_IRC_IRLVL7               0xf62c
-#define TX4938_IRC_IRMSK                0xf640
-#define TX4938_IRC_IREDC                0xf660
-#define TX4938_IRC_IRPND                0xf680
-#define TX4938_IRC_IRCS                 0xf6a0
-#define TX4938_IRC_LIMIT                0xf6ff
-
-
 #ifndef __ASSEMBLY__
 
 #define tx4938_sdramcptr	((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
 #define tx4938_ebuscptr         ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
 #define tx4938_dmaptr(ch)	((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
 #define tx4938_ndfmcptr		((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
-#define tx4938_ircptr		((struct tx4938_irc_reg *)TX4938_IRC_REG)
 #define tx4938_pcicptr		((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
 #define tx4938_pcic1ptr		((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
 #define tx4938_ccfgptr		((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
-- 
cgit v1.2.3


From e2286d755506afb5066740f251ae3bedc63f2ced Mon Sep 17 00:00:00 2001
From: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Date: Sat, 4 Aug 2007 23:26:53 +0900
Subject: [MIPS] SNI: remove unused pcimt_scache.c

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
 arch/mips/sni/pcimt_scache.c | 37 -------------------------------------
 include/asm-mips/bcache.h    |  1 -
 2 files changed, 38 deletions(-)
 delete mode 100644 arch/mips/sni/pcimt_scache.c

(limited to 'include')

diff --git a/arch/mips/sni/pcimt_scache.c b/arch/mips/sni/pcimt_scache.c
deleted file mode 100644
index a59d457fa8b1..000000000000
--- a/arch/mips/sni/pcimt_scache.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * arch/mips/sni/pcimt_scache.c
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 1997, 1998 by Ralf Baechle
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <asm/bcache.h>
-#include <asm/sni.h>
-
-#define cacheconf (*(volatile unsigned int *)PCIMT_CACHECONF)
-#define invspace (*(volatile unsigned int *)PCIMT_INVSPACE)
-
-void __init sni_pcimt_sc_init(void)
-{
-	unsigned int scsiz, sc_size;
-
-	scsiz = cacheconf & 7;
-	if (scsiz == 0) {
-		printk("Second level cache is deactived.\n");
-		return;
-	}
-	if (scsiz >= 6) {
-		printk("Invalid second level cache size configured, "
-		       "deactivating second level cache.\n");
-		cacheconf = 0;
-		return;
-	}
-
-	sc_size = 128 << scsiz;
-	printk("%dkb second level cache detected, deactivating.\n", sc_size);
-	cacheconf = 0;
-}
diff --git a/include/asm-mips/bcache.h b/include/asm-mips/bcache.h
index 3646a3f2ed38..0ba9d6ef76a7 100644
--- a/include/asm-mips/bcache.h
+++ b/include/asm-mips/bcache.h
@@ -21,7 +21,6 @@ struct bcache_ops {
 };
 
 extern void indy_sc_init(void);
-extern void sni_pcimt_sc_init(void);
 
 #ifdef CONFIG_BOARD_SCACHE
 
-- 
cgit v1.2.3


From 106e8028ce81305b93dfd6b809c196d62910feae Mon Sep 17 00:00:00 2001
From: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Date: Sat, 4 Aug 2007 23:34:17 +0900
Subject: [MIPS] remove unused gt64240.h

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
 include/asm-mips/gt64240.h | 1235 --------------------------------------------
 1 file changed, 1235 deletions(-)
 delete mode 100644 include/asm-mips/gt64240.h

(limited to 'include')

diff --git a/include/asm-mips/gt64240.h b/include/asm-mips/gt64240.h
deleted file mode 100644
index 8f9bd341ed49..000000000000
--- a/include/asm-mips/gt64240.h
+++ /dev/null
@@ -1,1235 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright - Galileo technology.
- * Copyright (C) 2004 by Ralf Baechle
- */
-#ifndef __ASM_MIPS_MV64240_H
-#define __ASM_MIPS_MV64240_H
-
-#include <asm/addrspace.h>
-#include <asm/marvell.h>
-
-/*
- * CPU Control Registers
- */
-
-#define CPU_CONFIGURATION					0x000
-#define CPU_MODE						0x120
-#define CPU_READ_RESPONSE_CROSSBAR_LOW				0x170
-#define CPU_READ_RESPONSE_CROSSBAR_HIGH				0x178
-
-/*
- * Processor Address Space
- */
-
-/* Sdram's BAR'S */
-#define SCS_0_LOW_DECODE_ADDRESS				0x008
-#define SCS_0_HIGH_DECODE_ADDRESS				0x010
-#define SCS_1_LOW_DECODE_ADDRESS				0x208
-#define SCS_1_HIGH_DECODE_ADDRESS				0x210
-#define SCS_2_LOW_DECODE_ADDRESS				0x018
-#define SCS_2_HIGH_DECODE_ADDRESS				0x020
-#define SCS_3_LOW_DECODE_ADDRESS				0x218
-#define SCS_3_HIGH_DECODE_ADDRESS				0x220
-/* Devices BAR'S */
-#define CS_0_LOW_DECODE_ADDRESS					0x028
-#define CS_0_HIGH_DECODE_ADDRESS				0x030
-#define CS_1_LOW_DECODE_ADDRESS					0x228
-#define CS_1_HIGH_DECODE_ADDRESS				0x230
-#define CS_2_LOW_DECODE_ADDRESS					0x248
-#define CS_2_HIGH_DECODE_ADDRESS				0x250
-#define CS_3_LOW_DECODE_ADDRESS					0x038
-#define CS_3_HIGH_DECODE_ADDRESS				0x040
-#define BOOTCS_LOW_DECODE_ADDRESS				0x238
-#define BOOTCS_HIGH_DECODE_ADDRESS				0x240
-
-#define PCI_0I_O_LOW_DECODE_ADDRESS				0x048
-#define PCI_0I_O_HIGH_DECODE_ADDRESS				0x050
-#define PCI_0MEMORY0_LOW_DECODE_ADDRESS				0x058
-#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS			0x060
-#define PCI_0MEMORY1_LOW_DECODE_ADDRESS				0x080
-#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS			0x088
-#define PCI_0MEMORY2_LOW_DECODE_ADDRESS				0x258
-#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS			0x260
-#define PCI_0MEMORY3_LOW_DECODE_ADDRESS				0x280
-#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS			0x288
-
-#define PCI_1I_O_LOW_DECODE_ADDRESS				0x090
-#define PCI_1I_O_HIGH_DECODE_ADDRESS				0x098
-#define PCI_1MEMORY0_LOW_DECODE_ADDRESS				0x0a0
-#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS			0x0a8
-#define PCI_1MEMORY1_LOW_DECODE_ADDRESS				0x0b0
-#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS			0x0b8
-#define PCI_1MEMORY2_LOW_DECODE_ADDRESS				0x2a0
-#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS			0x2a8
-#define PCI_1MEMORY3_LOW_DECODE_ADDRESS				0x2b0
-#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS			0x2b8
-
-#define INTERNAL_SPACE_DECODE					0x068
-
-#define CPU_0_LOW_DECODE_ADDRESS				0x290
-#define CPU_0_HIGH_DECODE_ADDRESS				0x298
-#define CPU_1_LOW_DECODE_ADDRESS				0x2c0
-#define CPU_1_HIGH_DECODE_ADDRESS				0x2c8
-
-#define PCI_0I_O_ADDRESS_REMAP					0x0f0
-#define PCI_0MEMORY0_ADDRESS_REMAP				0x0f8
-#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP				0x320
-#define PCI_0MEMORY1_ADDRESS_REMAP				0x100
-#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP				0x328
-#define PCI_0MEMORY2_ADDRESS_REMAP				0x2f8
-#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP				0x330
-#define PCI_0MEMORY3_ADDRESS_REMAP				0x300
-#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP				0x338
-
-#define PCI_1I_O_ADDRESS_REMAP					0x108
-#define PCI_1MEMORY0_ADDRESS_REMAP				0x110
-#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP				0x340
-#define PCI_1MEMORY1_ADDRESS_REMAP				0x118
-#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP				0x348
-#define PCI_1MEMORY2_ADDRESS_REMAP				0x310
-#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP				0x350
-#define PCI_1MEMORY3_ADDRESS_REMAP				0x318
-#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP				0x358
-
-/*
- * CPU Sync Barrier
- */
-
-#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER			0x0c0
-#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER			0x0c8
-
-
-/*
- * CPU Access Protect
- */
-
-#define CPU_LOW_PROTECT_ADDRESS_0				0X180
-#define CPU_HIGH_PROTECT_ADDRESS_0				0X188
-#define CPU_LOW_PROTECT_ADDRESS_1				0X190
-#define CPU_HIGH_PROTECT_ADDRESS_1				0X198
-#define CPU_LOW_PROTECT_ADDRESS_2				0X1a0
-#define CPU_HIGH_PROTECT_ADDRESS_2				0X1a8
-#define CPU_LOW_PROTECT_ADDRESS_3				0X1b0
-#define CPU_HIGH_PROTECT_ADDRESS_3				0X1b8
-#define CPU_LOW_PROTECT_ADDRESS_4				0X1c0
-#define CPU_HIGH_PROTECT_ADDRESS_4				0X1c8
-#define CPU_LOW_PROTECT_ADDRESS_5				0X1d0
-#define CPU_HIGH_PROTECT_ADDRESS_5				0X1d8
-#define CPU_LOW_PROTECT_ADDRESS_6				0X1e0
-#define CPU_HIGH_PROTECT_ADDRESS_6				0X1e8
-#define CPU_LOW_PROTECT_ADDRESS_7				0X1f0
-#define CPU_HIGH_PROTECT_ADDRESS_7				0X1f8
-
-
-/*
- * Snoop Control
- */
-
-#define SNOOP_BASE_ADDRESS_0					0x380
-#define SNOOP_TOP_ADDRESS_0					0x388
-#define SNOOP_BASE_ADDRESS_1					0x390
-#define SNOOP_TOP_ADDRESS_1					0x398
-#define SNOOP_BASE_ADDRESS_2					0x3a0
-#define SNOOP_TOP_ADDRESS_2					0x3a8
-#define SNOOP_BASE_ADDRESS_3					0x3b0
-#define SNOOP_TOP_ADDRESS_3					0x3b8
-
-/*
- * CPU Error Report
- */
-
-#define CPU_ERROR_ADDRESS_LOW					0x070
-#define CPU_ERROR_ADDRESS_HIGH					0x078
-#define CPU_ERROR_DATA_LOW					0x128
-#define CPU_ERROR_DATA_HIGH					0x130
-#define CPU_ERROR_PARITY					0x138
-#define CPU_ERROR_CAUSE						0x140
-#define CPU_ERROR_MASK						0x148
-
-/*
- * Pslave Debug
- */
-
-#define X_0_ADDRESS						0x360
-#define X_0_COMMAND_ID						0x368
-#define X_1_ADDRESS						0x370
-#define X_1_COMMAND_ID						0x378
-#define WRITE_DATA_LOW						0x3c0
-#define WRITE_DATA_HIGH						0x3c8
-#define WRITE_BYTE_ENABLE					0X3e0
-#define READ_DATA_LOW						0x3d0
-#define READ_DATA_HIGH						0x3d8
-#define READ_ID							0x3e8
-
-
-/*
- * SDRAM and Device Address Space
- */
-
-
-/*
- * SDRAM Configuration
- */
-
-#define SDRAM_CONFIGURATION					0x448
-#define SDRAM_OPERATION_MODE					0x474
-#define SDRAM_ADDRESS_DECODE					0x47C
-#define SDRAM_TIMING_PARAMETERS					0x4b4
-#define SDRAM_UMA_CONTROL					0x4a4
-#define SDRAM_CROSS_BAR_CONTROL_LOW				0x4a8
-#define SDRAM_CROSS_BAR_CONTROL_HIGH				0x4ac
-#define SDRAM_CROSS_BAR_TIMEOUT					0x4b0
-
-
-/*
- * SDRAM Parameters
- */
-
-#define SDRAM_BANK0PARAMETERS					0x44C
-#define SDRAM_BANK1PARAMETERS					0x450
-#define SDRAM_BANK2PARAMETERS					0x454
-#define SDRAM_BANK3PARAMETERS					0x458
-
-
-/*
- * SDRAM Error Report
- */
-
-#define SDRAM_ERROR_DATA_LOW					0x484
-#define SDRAM_ERROR_DATA_HIGH					0x480
-#define SDRAM_AND_DEVICE_ERROR_ADDRESS				0x490
-#define SDRAM_RECEIVED_ECC					0x488
-#define SDRAM_CALCULATED_ECC					0x48c
-#define SDRAM_ECC_CONTROL					0x494
-#define SDRAM_ECC_ERROR_COUNTER					0x498
-
-
-/*
- * SDunit Debug (for internal use)
- */
-
-#define X0_ADDRESS						0x500
-#define X0_COMMAND_AND_ID					0x504
-#define X0_WRITE_DATA_LOW					0x508
-#define X0_WRITE_DATA_HIGH					0x50c
-#define X0_WRITE_BYTE_ENABLE					0x518
-#define X0_READ_DATA_LOW					0x510
-#define X0_READ_DATA_HIGH					0x514
-#define X0_READ_ID						0x51c
-#define X1_ADDRESS						0x520
-#define X1_COMMAND_AND_ID					0x524
-#define X1_WRITE_DATA_LOW					0x528
-#define X1_WRITE_DATA_HIGH					0x52c
-#define X1_WRITE_BYTE_ENABLE					0x538
-#define X1_READ_DATA_LOW					0x530
-#define X1_READ_DATA_HIGH					0x534
-#define X1_READ_ID						0x53c
-#define X0_SNOOP_ADDRESS					0x540
-#define X0_SNOOP_COMMAND					0x544
-#define X1_SNOOP_ADDRESS					0x548
-#define X1_SNOOP_COMMAND					0x54c
-
-
-/*
- * Device Parameters
- */
-
-#define DEVICE_BANK0PARAMETERS					0x45c
-#define DEVICE_BANK1PARAMETERS					0x460
-#define DEVICE_BANK2PARAMETERS					0x464
-#define DEVICE_BANK3PARAMETERS					0x468
-#define DEVICE_BOOT_BANK_PARAMETERS				0x46c
-#define DEVICE_CONTROL						0x4c0
-#define DEVICE_CROSS_BAR_CONTROL_LOW				0x4c8
-#define DEVICE_CROSS_BAR_CONTROL_HIGH				0x4cc
-#define DEVICE_CROSS_BAR_TIMEOUT				0x4c4
-
-
-/*
- * Device Interrupt
- */
-
-#define DEVICE_INTERRUPT_CAUSE					0x4d0
-#define DEVICE_INTERRUPT_MASK					0x4d4
-#define DEVICE_ERROR_ADDRESS					0x4d8
-
-/*
- * DMA Record
- */
-
-#define CHANNEL0_DMA_BYTE_COUNT					0x800
-#define CHANNEL1_DMA_BYTE_COUNT					0x804
-#define CHANNEL2_DMA_BYTE_COUNT					0x808
-#define CHANNEL3_DMA_BYTE_COUNT					0x80C
-#define CHANNEL4_DMA_BYTE_COUNT					0x900
-#define CHANNEL5_DMA_BYTE_COUNT					0x904
-#define CHANNEL6_DMA_BYTE_COUNT					0x908
-#define CHANNEL7_DMA_BYTE_COUNT					0x90C
-#define CHANNEL0_DMA_SOURCE_ADDRESS				0x810
-#define CHANNEL1_DMA_SOURCE_ADDRESS				0x814
-#define CHANNEL2_DMA_SOURCE_ADDRESS				0x818
-#define CHANNEL3_DMA_SOURCE_ADDRESS				0x81C
-#define CHANNEL4_DMA_SOURCE_ADDRESS				0x910
-#define CHANNEL5_DMA_SOURCE_ADDRESS				0x914
-#define CHANNEL6_DMA_SOURCE_ADDRESS				0x918
-#define CHANNEL7_DMA_SOURCE_ADDRESS				0x91C
-#define CHANNEL0_DMA_DESTINATION_ADDRESS			0x820
-#define CHANNEL1_DMA_DESTINATION_ADDRESS			0x824
-#define CHANNEL2_DMA_DESTINATION_ADDRESS			0x828
-#define CHANNEL3_DMA_DESTINATION_ADDRESS			0x82C
-#define CHANNEL4_DMA_DESTINATION_ADDRESS			0x920
-#define CHANNEL5_DMA_DESTINATION_ADDRESS			0x924
-#define CHANNEL6_DMA_DESTINATION_ADDRESS			0x928
-#define CHANNEL7_DMA_DESTINATION_ADDRESS			0x92C
-#define CHANNEL0NEXT_RECORD_POINTER				0x830
-#define CHANNEL1NEXT_RECORD_POINTER				0x834
-#define CHANNEL2NEXT_RECORD_POINTER				0x838
-#define CHANNEL3NEXT_RECORD_POINTER				0x83C
-#define CHANNEL4NEXT_RECORD_POINTER				0x930
-#define CHANNEL5NEXT_RECORD_POINTER				0x934
-#define CHANNEL6NEXT_RECORD_POINTER				0x938
-#define CHANNEL7NEXT_RECORD_POINTER				0x93C
-#define CHANNEL0CURRENT_DESCRIPTOR_POINTER			0x870
-#define CHANNEL1CURRENT_DESCRIPTOR_POINTER			0x874
-#define CHANNEL2CURRENT_DESCRIPTOR_POINTER			0x878
-#define CHANNEL3CURRENT_DESCRIPTOR_POINTER			0x87C
-#define CHANNEL4CURRENT_DESCRIPTOR_POINTER			0x970
-#define CHANNEL5CURRENT_DESCRIPTOR_POINTER			0x974
-#define CHANNEL6CURRENT_DESCRIPTOR_POINTER			0x978
-#define CHANNEL7CURRENT_DESCRIPTOR_POINTER			0x97C
-#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS			0x890
-#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS			0x894
-#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS			0x898
-#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS			0x89c
-#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS			0x990
-#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS			0x994
-#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS			0x998
-#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS			0x99c
-#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x8a0
-#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x8a4
-#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x8a8
-#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x8ac
-#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x9a0
-#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x9a4
-#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x9a8
-#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS		0x9ac
-#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x8b0
-#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x8b4
-#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x8b8
-#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x8bc
-#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x9b0
-#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x9b4
-#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x9b8
-#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS	0x9bc
-
-/*
- * DMA Channel Control
- */
-
-#define CHANNEL0CONTROL						0x840
-#define CHANNEL0CONTROL_HIGH					0x880
-
-#define CHANNEL1CONTROL						0x844
-#define CHANNEL1CONTROL_HIGH					0x884
-
-#define CHANNEL2CONTROL						0x848
-#define CHANNEL2CONTROL_HIGH					0x888
-
-#define CHANNEL3CONTROL						0x84C
-#define CHANNEL3CONTROL_HIGH					0x88C
-
-#define CHANNEL4CONTROL						0x940
-#define CHANNEL4CONTROL_HIGH					0x980
-
-#define CHANNEL5CONTROL						0x944
-#define CHANNEL5CONTROL_HIGH					0x984
-
-#define CHANNEL6CONTROL						0x948
-#define CHANNEL6CONTROL_HIGH					0x988
-
-#define CHANNEL7CONTROL						0x94C
-#define CHANNEL7CONTROL_HIGH					0x98C
-
-
-/*
- * DMA Arbiter
- */
-
-#define ARBITER_CONTROL_0_3					0x860
-#define ARBITER_CONTROL_4_7					0x960
-
-
-/*
- * DMA Interrupt
- */
-
-#define CHANELS0_3_INTERRUPT_CAUSE				0x8c0
-#define CHANELS0_3_INTERRUPT_MASK				0x8c4
-#define CHANELS0_3_ERROR_ADDRESS				0x8c8
-#define CHANELS0_3_ERROR_SELECT					0x8cc
-#define CHANELS4_7_INTERRUPT_CAUSE				0x9c0
-#define CHANELS4_7_INTERRUPT_MASK				0x9c4
-#define CHANELS4_7_ERROR_ADDRESS				0x9c8
-#define CHANELS4_7_ERROR_SELECT					0x9cc
-
-
-/*
- * DMA Debug (for internal use)
- */
-
-#define DMA_X0_ADDRESS						0x8e0
-#define DMA_X0_COMMAND_AND_ID					0x8e4
-#define DMA_X0_WRITE_DATA_LOW					0x8e8
-#define DMA_X0_WRITE_DATA_HIGH					0x8ec
-#define DMA_X0_WRITE_BYTE_ENABLE				0x8f8
-#define DMA_X0_READ_DATA_LOW					0x8f0
-#define DMA_X0_READ_DATA_HIGH					0x8f4
-#define DMA_X0_READ_ID						0x8fc
-#define DMA_X1_ADDRESS						0x9e0
-#define DMA_X1_COMMAND_AND_ID					0x9e4
-#define DMA_X1_WRITE_DATA_LOW					0x9e8
-#define DMA_X1_WRITE_DATA_HIGH					0x9ec
-#define DMA_X1_WRITE_BYTE_ENABLE				0x9f8
-#define DMA_X1_READ_DATA_LOW					0x9f0
-#define DMA_X1_READ_DATA_HIGH					0x9f4
-#define DMA_X1_READ_ID						0x9fc
-
-/*
- * Timer_Counter
- */
-
-#define TIMER_COUNTER0						0x850
-#define TIMER_COUNTER1						0x854
-#define TIMER_COUNTER2						0x858
-#define TIMER_COUNTER3						0x85C
-#define TIMER_COUNTER_0_3_CONTROL				0x864
-#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE			0x868
-#define TIMER_COUNTER_0_3_INTERRUPT_MASK			0x86c
-#define TIMER_COUNTER4						0x950
-#define TIMER_COUNTER5						0x954
-#define TIMER_COUNTER6						0x958
-#define TIMER_COUNTER7						0x95C
-#define TIMER_COUNTER_4_7_CONTROL				0x964
-#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE			0x968
-#define TIMER_COUNTER_4_7_INTERRUPT_MASK			0x96c
-
-/*
- * PCI Slave Address Decoding
- */
-
-#define PCI_0SCS_0_BANK_SIZE					0xc08
-#define PCI_1SCS_0_BANK_SIZE					0xc88
-#define PCI_0SCS_1_BANK_SIZE					0xd08
-#define PCI_1SCS_1_BANK_SIZE					0xd88
-#define PCI_0SCS_2_BANK_SIZE					0xc0c
-#define PCI_1SCS_2_BANK_SIZE					0xc8c
-#define PCI_0SCS_3_BANK_SIZE					0xd0c
-#define PCI_1SCS_3_BANK_SIZE					0xd8c
-#define PCI_0CS_0_BANK_SIZE					0xc10
-#define PCI_1CS_0_BANK_SIZE					0xc90
-#define PCI_0CS_1_BANK_SIZE					0xd10
-#define PCI_1CS_1_BANK_SIZE					0xd90
-#define PCI_0CS_2_BANK_SIZE					0xd18
-#define PCI_1CS_2_BANK_SIZE					0xd98
-#define PCI_0CS_3_BANK_SIZE					0xc14
-#define PCI_1CS_3_BANK_SIZE					0xc94
-#define PCI_0CS_BOOT_BANK_SIZE					0xd14
-#define PCI_1CS_BOOT_BANK_SIZE					0xd94
-#define PCI_0P2P_MEM0_BAR_SIZE					0xd1c
-#define PCI_1P2P_MEM0_BAR_SIZE					0xd9c
-#define PCI_0P2P_MEM1_BAR_SIZE					0xd20
-#define PCI_1P2P_MEM1_BAR_SIZE					0xda0
-#define PCI_0P2P_I_O_BAR_SIZE					0xd24
-#define PCI_1P2P_I_O_BAR_SIZE					0xda4
-#define PCI_0CPU_BAR_SIZE					0xd28
-#define PCI_1CPU_BAR_SIZE					0xda8
-#define PCI_0DAC_SCS_0_BANK_SIZE				0xe00
-#define PCI_1DAC_SCS_0_BANK_SIZE				0xe80
-#define PCI_0DAC_SCS_1_BANK_SIZE				0xe04
-#define PCI_1DAC_SCS_1_BANK_SIZE				0xe84
-#define PCI_0DAC_SCS_2_BANK_SIZE				0xe08
-#define PCI_1DAC_SCS_2_BANK_SIZE				0xe88
-#define PCI_0DAC_SCS_3_BANK_SIZE				0xe0c
-#define PCI_1DAC_SCS_3_BANK_SIZE				0xe8c
-#define PCI_0DAC_CS_0_BANK_SIZE					0xe10
-#define PCI_1DAC_CS_0_BANK_SIZE					0xe90
-#define PCI_0DAC_CS_1_BANK_SIZE					0xe14
-#define PCI_1DAC_CS_1_BANK_SIZE					0xe94
-#define PCI_0DAC_CS_2_BANK_SIZE					0xe18
-#define PCI_1DAC_CS_2_BANK_SIZE					0xe98
-#define PCI_0DAC_CS_3_BANK_SIZE					0xe1c
-#define PCI_1DAC_CS_3_BANK_SIZE					0xe9c
-#define PCI_0DAC_BOOTCS_BANK_SIZE				0xe20
-#define PCI_1DAC_BOOTCS_BANK_SIZE				0xea0
-#define PCI_0DAC_P2P_MEM0_BAR_SIZE				0xe24
-#define PCI_1DAC_P2P_MEM0_BAR_SIZE				0xea4
-#define PCI_0DAC_P2P_MEM1_BAR_SIZE				0xe28
-#define PCI_1DAC_P2P_MEM1_BAR_SIZE				0xea8
-#define PCI_0DAC_CPU_BAR_SIZE					0xe2c
-#define PCI_1DAC_CPU_BAR_SIZE					0xeac
-#define PCI_0EXPANSION_ROM_BAR_SIZE				0xd2c
-#define PCI_1EXPANSION_ROM_BAR_SIZE				0xdac
-#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE			0xc3c
-#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE			0xcbc
-#define PCI_0SCS_0_BASE_ADDRESS_REMAP				0xc48
-#define PCI_1SCS_0_BASE_ADDRESS_REMAP				0xcc8
-#define PCI_0SCS_1_BASE_ADDRESS_REMAP				0xd48
-#define PCI_1SCS_1_BASE_ADDRESS_REMAP				0xdc8
-#define PCI_0SCS_2_BASE_ADDRESS_REMAP				0xc4c
-#define PCI_1SCS_2_BASE_ADDRESS_REMAP				0xccc
-#define PCI_0SCS_3_BASE_ADDRESS_REMAP				0xd4c
-#define PCI_1SCS_3_BASE_ADDRESS_REMAP				0xdcc
-#define PCI_0CS_0_BASE_ADDRESS_REMAP				0xc50
-#define PCI_1CS_0_BASE_ADDRESS_REMAP				0xcd0
-#define PCI_0CS_1_BASE_ADDRESS_REMAP				0xd50
-#define PCI_1CS_1_BASE_ADDRESS_REMAP				0xdd0
-#define PCI_0CS_2_BASE_ADDRESS_REMAP				0xd58
-#define PCI_1CS_2_BASE_ADDRESS_REMAP				0xdd8
-#define PCI_0CS_3_BASE_ADDRESS_REMAP				0xc54
-#define PCI_1CS_3_BASE_ADDRESS_REMAP				0xcd4
-#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP			0xd54
-#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP			0xdd4
-#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW			0xd5c
-#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW			0xddc
-#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH			0xd60
-#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH			0xde0
-#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW			0xd64
-#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW			0xde4
-#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH			0xd68
-#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH			0xde8
-#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP				0xd6c
-#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP				0xdec
-#define PCI_0CPU_BASE_ADDRESS_REMAP				0xd70
-#define PCI_1CPU_BASE_ADDRESS_REMAP				0xdf0
-#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP			0xf00
-#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP			0xff0
-#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP			0xf04
-#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP			0xf84
-#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP			0xf08
-#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP			0xf88
-#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP			0xf0c
-#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP			0xf8c
-#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP			0xf10
-#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP			0xf90
-#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP			0xf14
-#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP			0xf94
-#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP			0xf18
-#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP			0xf98
-#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP			0xf1c
-#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP			0xf9c
-#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP			0xf20
-#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP			0xfa0
-#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW		0xf24
-#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW		0xfa4
-#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH		0xf28
-#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH		0xfa8
-#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW		0xf2c
-#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW		0xfac
-#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH		0xf30
-#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH		0xfb0
-#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP				0xf34
-#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP				0xfb4
-#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP			0xf38
-#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP			0xfb8
-#define PCI_0ADDRESS_DECODE_CONTROL				0xd3c
-#define PCI_1ADDRESS_DECODE_CONTROL				0xdbc
-
-/*
- * PCI Control
- */
-
-#define PCI_0COMMAND						0xc00
-#define PCI_1COMMAND						0xc80
-#define PCI_0MODE						0xd00
-#define PCI_1MODE						0xd80
-#define PCI_0TIMEOUT_RETRY					0xc04
-#define PCI_1TIMEOUT_RETRY					0xc84
-#define PCI_0READ_BUFFER_DISCARD_TIMER				0xd04
-#define PCI_1READ_BUFFER_DISCARD_TIMER				0xd84
-#define MSI_0TRIGGER_TIMER					0xc38
-#define MSI_1TRIGGER_TIMER					0xcb8
-#define PCI_0ARBITER_CONTROL					0x1d00
-#define PCI_1ARBITER_CONTROL					0x1d80
-/* changing untill here */
-#define PCI_0CROSS_BAR_CONTROL_LOW				 0x1d08
-#define PCI_0CROSS_BAR_CONTROL_HIGH				 0x1d0c
-#define PCI_0CROSS_BAR_TIMEOUT					 0x1d04
-#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW		 0x1d18
-#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH		 0x1d1c
-#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER			 0x1d10
-#define PCI_0P2P_CONFIGURATION					 0x1d14
-#define PCI_0ACCESS_CONTROL_BASE_0_LOW				 0x1e00
-#define PCI_0ACCESS_CONTROL_BASE_0_HIGH				 0x1e04
-#define PCI_0ACCESS_CONTROL_TOP_0				 0x1e08
-#define PCI_0ACCESS_CONTROL_BASE_1_LOW				 0c1e10
-#define PCI_0ACCESS_CONTROL_BASE_1_HIGH				 0x1e14
-#define PCI_0ACCESS_CONTROL_TOP_1				 0x1e18
-#define PCI_0ACCESS_CONTROL_BASE_2_LOW				 0c1e20
-#define PCI_0ACCESS_CONTROL_BASE_2_HIGH				 0x1e24
-#define PCI_0ACCESS_CONTROL_TOP_2				 0x1e28
-#define PCI_0ACCESS_CONTROL_BASE_3_LOW				 0c1e30
-#define PCI_0ACCESS_CONTROL_BASE_3_HIGH				 0x1e34
-#define PCI_0ACCESS_CONTROL_TOP_3				 0x1e38
-#define PCI_0ACCESS_CONTROL_BASE_4_LOW				 0c1e40
-#define PCI_0ACCESS_CONTROL_BASE_4_HIGH				 0x1e44
-#define PCI_0ACCESS_CONTROL_TOP_4				 0x1e48
-#define PCI_0ACCESS_CONTROL_BASE_5_LOW				 0c1e50
-#define PCI_0ACCESS_CONTROL_BASE_5_HIGH				 0x1e54
-#define PCI_0ACCESS_CONTROL_TOP_5				 0x1e58
-#define PCI_0ACCESS_CONTROL_BASE_6_LOW				 0c1e60
-#define PCI_0ACCESS_CONTROL_BASE_6_HIGH				 0x1e64
-#define PCI_0ACCESS_CONTROL_TOP_6				 0x1e68
-#define PCI_0ACCESS_CONTROL_BASE_7_LOW				 0c1e70
-#define PCI_0ACCESS_CONTROL_BASE_7_HIGH				 0x1e74
-#define PCI_0ACCESS_CONTROL_TOP_7				 0x1e78
-#define PCI_1CROSS_BAR_CONTROL_LOW				 0x1d88
-#define PCI_1CROSS_BAR_CONTROL_HIGH				 0x1d8c
-#define PCI_1CROSS_BAR_TIMEOUT					 0x1d84
-#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW		 0x1d98
-#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH		 0x1d9c
-#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER			 0x1d90
-#define PCI_1P2P_CONFIGURATION					 0x1d94
-#define PCI_1ACCESS_CONTROL_BASE_0_LOW				 0x1e80
-#define PCI_1ACCESS_CONTROL_BASE_0_HIGH				 0x1e84
-#define PCI_1ACCESS_CONTROL_TOP_0				 0x1e88
-#define PCI_1ACCESS_CONTROL_BASE_1_LOW				 0c1e90
-#define PCI_1ACCESS_CONTROL_BASE_1_HIGH				 0x1e94
-#define PCI_1ACCESS_CONTROL_TOP_1				 0x1e98
-#define PCI_1ACCESS_CONTROL_BASE_2_LOW				 0c1ea0
-#define PCI_1ACCESS_CONTROL_BASE_2_HIGH				 0x1ea4
-#define PCI_1ACCESS_CONTROL_TOP_2				 0x1ea8
-#define PCI_1ACCESS_CONTROL_BASE_3_LOW				 0c1eb0
-#define PCI_1ACCESS_CONTROL_BASE_3_HIGH				 0x1eb4
-#define PCI_1ACCESS_CONTROL_TOP_3				 0x1eb8
-#define PCI_1ACCESS_CONTROL_BASE_4_LOW				 0c1ec0
-#define PCI_1ACCESS_CONTROL_BASE_4_HIGH				 0x1ec4
-#define PCI_1ACCESS_CONTROL_TOP_4				 0x1ec8
-#define PCI_1ACCESS_CONTROL_BASE_5_LOW				 0c1ed0
-#define PCI_1ACCESS_CONTROL_BASE_5_HIGH				 0x1ed4
-#define PCI_1ACCESS_CONTROL_TOP_5				 0x1ed8
-#define PCI_1ACCESS_CONTROL_BASE_6_LOW				 0c1ee0
-#define PCI_1ACCESS_CONTROL_BASE_6_HIGH				 0x1ee4
-#define PCI_1ACCESS_CONTROL_TOP_6				 0x1ee8
-#define PCI_1ACCESS_CONTROL_BASE_7_LOW				 0c1ef0
-#define PCI_1ACCESS_CONTROL_BASE_7_HIGH				 0x1ef4
-#define PCI_1ACCESS_CONTROL_TOP_7				 0x1ef8
-
-/*
- * PCI Snoop Control
- */
-
-#define PCI_0SNOOP_CONTROL_BASE_0_LOW				 0x1f00
-#define PCI_0SNOOP_CONTROL_BASE_0_HIGH				 0x1f04
-#define PCI_0SNOOP_CONTROL_TOP_0				 0x1f08
-#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW				 0x1f10
-#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH			 0x1f14
-#define PCI_0SNOOP_CONTROL_TOP_1				 0x1f18
-#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW				 0x1f20
-#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH			 0x1f24
-#define PCI_0SNOOP_CONTROL_TOP_2				 0x1f28
-#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW				 0x1f30
-#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH			 0x1f34
-#define PCI_0SNOOP_CONTROL_TOP_3				 0x1f38
-#define PCI_1SNOOP_CONTROL_BASE_0_LOW				 0x1f80
-#define PCI_1SNOOP_CONTROL_BASE_0_HIGH				 0x1f84
-#define PCI_1SNOOP_CONTROL_TOP_0				 0x1f88
-#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW				 0x1f90
-#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH			 0x1f94
-#define PCI_1SNOOP_CONTROL_TOP_1				 0x1f98
-#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW				 0x1fa0
-#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH			 0x1fa4
-#define PCI_1SNOOP_CONTROL_TOP_2				 0x1fa8
-#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW				 0x1fb0
-#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH			 0x1fb4
-#define PCI_1SNOOP_CONTROL_TOP_3				 0x1fb8
-
-/*
- * PCI Configuration Address
- */
-
-#define PCI_0CONFIGURATION_ADDRESS				0xcf8
-#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER		0xcfc
-#define PCI_1CONFIGURATION_ADDRESS				0xc78
-#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER		0xc7c
-#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER		0xc34
-#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER		0xcb4
-
-/*
- * PCI Error Report
- */
-
-#define PCI_0SERR_MASK						 0xc28
-#define PCI_0ERROR_ADDRESS_LOW					 0x1d40
-#define PCI_0ERROR_ADDRESS_HIGH					 0x1d44
-#define PCI_0ERROR_DATA_LOW					 0x1d48
-#define PCI_0ERROR_DATA_HIGH					 0x1d4c
-#define PCI_0ERROR_COMMAND					 0x1d50
-#define PCI_0ERROR_CAUSE					 0x1d58
-#define PCI_0ERROR_MASK						 0x1d5c
-
-#define PCI_1SERR_MASK						 0xca8
-#define PCI_1ERROR_ADDRESS_LOW					 0x1dc0
-#define PCI_1ERROR_ADDRESS_HIGH					 0x1dc4
-#define PCI_1ERROR_DATA_LOW					 0x1dc8
-#define PCI_1ERROR_DATA_HIGH					 0x1dcc
-#define PCI_1ERROR_COMMAND					 0x1dd0
-#define PCI_1ERROR_CAUSE					 0x1dd8
-#define PCI_1ERROR_MASK						 0x1ddc
-
-
-/*
- * Lslave Debug	 (for internal use)
- */
-
-#define L_SLAVE_X0_ADDRESS					0x1d20
-#define L_SLAVE_X0_COMMAND_AND_ID				0x1d24
-#define L_SLAVE_X1_ADDRESS					0x1d28
-#define L_SLAVE_X1_COMMAND_AND_ID				0x1d2c
-#define L_SLAVE_WRITE_DATA_LOW					0x1d30
-#define L_SLAVE_WRITE_DATA_HIGH					0x1d34
-#define L_SLAVE_WRITE_BYTE_ENABLE				0x1d60
-#define L_SLAVE_READ_DATA_LOW					0x1d38
-#define L_SLAVE_READ_DATA_HIGH					0x1d3c
-#define L_SLAVE_READ_ID						0x1d64
-
-#if 0 /* Disabled because PCI_* namespace belongs to PCI subsystem ... */
-
-/*
- * PCI Configuration Function 0
- */
-
-#define PCI_DEVICE_AND_VENDOR_ID				0x000
-#define PCI_STATUS_AND_COMMAND					0x004
-#define PCI_CLASS_CODE_AND_REVISION_ID				0x008
-#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE		0x00C
-#define PCI_SCS_0_BASE_ADDRESS					0x010
-#define PCI_SCS_1_BASE_ADDRESS					0x014
-#define PCI_SCS_2_BASE_ADDRESS					0x018
-#define PCI_SCS_3_BASE_ADDRESS					0x01C
-#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS	0x020
-#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS		0x024
-#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID		0x02C
-#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER			0x030
-#define PCI_CAPABILTY_LIST_POINTER				0x034
-#define PCI_INTERRUPT_PIN_AND_LINE				0x03C
-#define PCI_POWER_MANAGEMENT_CAPABILITY				0x040
-#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL			0x044
-#define PCI_VPD_ADDRESS						0x048
-#define PCI_VPD_DATA						0X04c
-#define PCI_MSI_MESSAGE_CONTROL					0x050
-#define PCI_MSI_MESSAGE_ADDRESS					0x054
-#define PCI_MSI_MESSAGE_UPPER_ADDRESS				0x058
-#define PCI_MSI_MESSAGE_DATA					0x05c
-#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY			0x058
-
-/*
- * PCI Configuration Function 1
- */
-
-#define PCI_CS_0_BASE_ADDRESS					0x110
-#define PCI_CS_1_BASE_ADDRESS					0x114
-#define PCI_CS_2_BASE_ADDRESS					0x118
-#define PCI_CS_3_BASE_ADDRESS					0x11c
-#define PCI_BOOTCS_BASE_ADDRESS					0x120
-
-/*
- * PCI Configuration Function 2
- */
-
-#define PCI_P2P_MEM0_BASE_ADDRESS				0x210
-#define PCI_P2P_MEM1_BASE_ADDRESS				0x214
-#define PCI_P2P_I_O_BASE_ADDRESS				0x218
-#define PCI_CPU_BASE_ADDRESS					0x21c
-
-/*
- * PCI Configuration Function 4
- */
-
-#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW				0x410
-#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH				0x414
-#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW				0x418
-#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH				0x41c
-#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW			0x420
-#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH			0x424
-
-
-/*
- * PCI Configuration Function 5
- */
-
-#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW				0x510
-#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH				0x514
-#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW				0x518
-#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH				0x51c
-#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW			0x520
-#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH			0x524
-
-
-/*
- * PCI Configuration Function 6
- */
-
-#define PCI_DAC_CS_0_BASE_ADDRESS_LOW				0x610
-#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH				0x614
-#define PCI_DAC_CS_1_BASE_ADDRESS_LOW				0x618
-#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH				0x61c
-#define PCI_DAC_CS_2_BASE_ADDRESS_LOW				0x620
-#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH				0x624
-
-/*
- * PCI Configuration Function 7
- */
-
-#define PCI_DAC_CS_3_BASE_ADDRESS_LOW				0x710
-#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH				0x714
-#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW				0x718
-#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH			0x71c
-#define PCI_DAC_CPU_BASE_ADDRESS_LOW				0x720
-#define PCI_DAC_CPU_BASE_ADDRESS_HIGH				0x724
-#endif
-
-/*
- * Interrupts
- */
-
-#define LOW_INTERRUPT_CAUSE_REGISTER				0xc18
-#define HIGH_INTERRUPT_CAUSE_REGISTER				0xc68
-#define CPU_INTERRUPT_MASK_REGISTER_LOW				0xc1c
-#define CPU_INTERRUPT_MASK_REGISTER_HIGH			0xc6c
-#define CPU_SELECT_CAUSE_REGISTER				0xc70
-#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW			0xc24
-#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH			0xc64
-#define PCI_0SELECT_CAUSE					0xc74
-#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW			0xca4
-#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH			0xce4
-#define PCI_1SELECT_CAUSE					0xcf4
-#define CPU_INT_0_MASK						0xe60
-#define CPU_INT_1_MASK						0xe64
-#define CPU_INT_2_MASK						0xe68
-#define CPU_INT_3_MASK						0xe6c
-
-/*
- * I20 Support registers
- */
-
-#define INBOUND_MESSAGE_REGISTER0_PCI0_SIDE			0x010
-#define INBOUND_MESSAGE_REGISTER1_PCI0_SIDE			0x014
-#define OUTBOUND_MESSAGE_REGISTER0_PCI0_SIDE			0x018
-#define OUTBOUND_MESSAGE_REGISTER1_PCI0_SIDE			0x01C
-#define INBOUND_DOORBELL_REGISTER_PCI0_SIDE			0x020
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE		0x024
-#define INBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE		0x028
-#define OUTBOUND_DOORBELL_REGISTER_PCI0_SIDE			0x02C
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE		0x030
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE		0x034
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE		0x040
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE		0x044
-#define QUEUE_CONTROL_REGISTER_PCI0_SIDE			0x050
-#define QUEUE_BASE_ADDRESS_REGISTER_PCI0_SIDE			0x054
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE		0x060
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE		0x064
-#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE		0x068
-#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE		0x06C
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE		0x070
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE		0x074
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE		0x0F8
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE		0x0FC
-
-#define INBOUND_MESSAGE_REGISTER0_PCI1_SIDE			0x090
-#define INBOUND_MESSAGE_REGISTER1_PCI1_SIDE			0x094
-#define OUTBOUND_MESSAGE_REGISTER0_PCI1_SIDE			0x098
-#define OUTBOUND_MESSAGE_REGISTER1_PCI1_SIDE			0x09C
-#define INBOUND_DOORBELL_REGISTER_PCI1_SIDE			0x0A0
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE		0x0A4
-#define INBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE		0x0A8
-#define OUTBOUND_DOORBELL_REGISTER_PCI1_SIDE			0x0AC
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE		0x0B0
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE		0x0B4
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE		0x0C0
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE		0x0C4
-#define QUEUE_CONTROL_REGISTER_PCI1_SIDE			0x0D0
-#define QUEUE_BASE_ADDRESS_REGISTER_PCI1_SIDE			0x0D4
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE		0x0E0
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE		0x0E4
-#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE		0x0E8
-#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE		0x0EC
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE		0x0F0
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE		0x0F4
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE		0x078
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE		0x07C
-
-#define INBOUND_MESSAGE_REGISTER0_CPU0_SIDE			0X1C10
-#define INBOUND_MESSAGE_REGISTER1_CPU0_SIDE			0X1C14
-#define OUTBOUND_MESSAGE_REGISTER0_CPU0_SIDE			0X1C18
-#define OUTBOUND_MESSAGE_REGISTER1_CPU0_SIDE			0X1C1C
-#define INBOUND_DOORBELL_REGISTER_CPU0_SIDE			0X1C20
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE		0X1C24
-#define INBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE		0X1C28
-#define OUTBOUND_DOORBELL_REGISTER_CPU0_SIDE			0X1C2C
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE		0X1C30
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE		0X1C34
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE		0X1C40
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE		0X1C44
-#define QUEUE_CONTROL_REGISTER_CPU0_SIDE			0X1C50
-#define QUEUE_BASE_ADDRESS_REGISTER_CPU0_SIDE			0X1C54
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE		0X1C60
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE		0X1C64
-#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE		0X1C68
-#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE		0X1C6C
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE		0X1C70
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE		0X1C74
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE		0X1CF8
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE		0X1CFC
-
-#define INBOUND_MESSAGE_REGISTER0_CPU1_SIDE			0X1C90
-#define INBOUND_MESSAGE_REGISTER1_CPU1_SIDE			0X1C94
-#define OUTBOUND_MESSAGE_REGISTER0_CPU1_SIDE			0X1C98
-#define OUTBOUND_MESSAGE_REGISTER1_CPU1_SIDE			0X1C9C
-#define INBOUND_DOORBELL_REGISTER_CPU1_SIDE			0X1CA0
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE		0X1CA4
-#define INBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE		0X1CA8
-#define OUTBOUND_DOORBELL_REGISTER_CPU1_SIDE			0X1CAC
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE		0X1CB0
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE		0X1CB4
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE		0X1CC0
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE		0X1CC4
-#define QUEUE_CONTROL_REGISTER_CPU1_SIDE			0X1CD0
-#define QUEUE_BASE_ADDRESS_REGISTER_CPU1_SIDE			0X1CD4
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE		0X1CE0
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE		0X1CE4
-#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE		0X1CE8
-#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE		0X1CEC
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE		0X1CF0
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE		0X1CF4
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE		0X1C78
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE		0X1C7C
-
-/*
- * Communication Unit Registers
- */
-
-#define ETHERNET_0_ADDRESS_CONTROL_LOW
-#define ETHERNET_0_ADDRESS_CONTROL_HIGH				0xf204
-#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS		0xf208
-#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS		0xf20c
-#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf210
-#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf214
-#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS			0xf218
-#define ETHERNET_1_ADDRESS_CONTROL_LOW				0xf220
-#define ETHERNET_1_ADDRESS_CONTROL_HIGH				0xf224
-#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS		0xf228
-#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS		0xf22c
-#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf230
-#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf234
-#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS			0xf238
-#define ETHERNET_2_ADDRESS_CONTROL_LOW				0xf240
-#define ETHERNET_2_ADDRESS_CONTROL_HIGH				0xf244
-#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS		0xf248
-#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS		0xf24c
-#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf250
-#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf254
-#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS			0xf258
-#define MPSC_0_ADDRESS_CONTROL_LOW				0xf280
-#define MPSC_0_ADDRESS_CONTROL_HIGH				0xf284
-#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS			0xf288
-#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS			0xf28c
-#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf290
-#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf294
-#define MPSC_1_ADDRESS_CONTROL_LOW				0xf2a0
-#define MPSC_1_ADDRESS_CONTROL_HIGH				0xf2a4
-#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS			0xf2a8
-#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS			0xf2ac
-#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf2b0
-#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf2b4
-#define MPSC_2_ADDRESS_CONTROL_LOW				0xf2c0
-#define MPSC_2_ADDRESS_CONTROL_HIGH				0xf2c4
-#define MPSC_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS			0xf2c8
-#define MPSC_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS			0xf2cc
-#define MPSC_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf2d0
-#define MPSC_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS		0xf2d4
-#define SERIAL_INIT_PCI_HIGH_ADDRESS				0xf320
-#define SERIAL_INIT_LAST_DATA					0xf324
-#define SERIAL_INIT_STATUS_AND_CONTROL				0xf328
-#define COMM_UNIT_ARBITER_CONTROL				0xf300
-#define COMM_UNIT_CROSS_BAR_TIMEOUT				0xf304
-#define COMM_UNIT_INTERRUPT_CAUSE				0xf310
-#define COMM_UNIT_INTERRUPT_MASK				0xf314
-#define COMM_UNIT_ERROR_ADDRESS					0xf314
-
-/*
- * Cunit Debug	(for internal use)
- */
-
-#define CUNIT_ADDRESS						0xf340
-#define CUNIT_COMMAND_AND_ID					0xf344
-#define CUNIT_WRITE_DATA_LOW					0xf348
-#define CUNIT_WRITE_DATA_HIGH					0xf34c
-#define CUNIT_WRITE_BYTE_ENABLE					0xf358
-#define CUNIT_READ_DATA_LOW					0xf350
-#define CUNIT_READ_DATA_HIGH					0xf354
-#define CUNIT_READ_ID						0xf35c
-
-/*
- * Fast Ethernet Unit Registers
- */
-
-/* Ethernet */
-
-#define ETHERNET_PHY_ADDRESS_REGISTER				0x2000
-#define ETHERNET_SMI_REGISTER					0x2010
-
-/* Ethernet 0 */
-
-#define ETHERNET0_PORT_CONFIGURATION_REGISTER			0x2400
-#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER		0x2408
-#define ETHERNET0_PORT_COMMAND_REGISTER				0x2410
-#define ETHERNET0_PORT_STATUS_REGISTER				0x2418
-#define ETHERNET0_SERIAL_PARAMETRS_REGISTER			0x2420
-#define ETHERNET0_HASH_TABLE_POINTER_REGISTER			0x2428
-#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW		0x2430
-#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH		0x2438
-#define ETHERNET0_SDMA_CONFIGURATION_REGISTER			0x2440
-#define ETHERNET0_SDMA_COMMAND_REGISTER				0x2448
-#define ETHERNET0_INTERRUPT_CAUSE_REGISTER			0x2450
-#define ETHERNET0_INTERRUPT_MASK_REGISTER			0x2458
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0			0x2480
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1			0x2484
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2			0x2488
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3			0x248c
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0		0x24a0
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1		0x24a4
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2		0x24a8
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3		0x24ac
-#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0		0x24e0
-#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1		0x24e4
-#define ETHERNET0_MIB_COUNTER_BASE				0x2500
-
-/* Ethernet 1 */
-
-#define ETHERNET1_PORT_CONFIGURATION_REGISTER			0x2800
-#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER		0x2808
-#define ETHERNET1_PORT_COMMAND_REGISTER				0x2810
-#define ETHERNET1_PORT_STATUS_REGISTER				0x2818
-#define ETHERNET1_SERIAL_PARAMETRS_REGISTER			0x2820
-#define ETHERNET1_HASH_TABLE_POINTER_REGISTER			0x2828
-#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW		0x2830
-#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH		0x2838
-#define ETHERNET1_SDMA_CONFIGURATION_REGISTER			0x2840
-#define ETHERNET1_SDMA_COMMAND_REGISTER				0x2848
-#define ETHERNET1_INTERRUPT_CAUSE_REGISTER			0x2850
-#define ETHERNET1_INTERRUPT_MASK_REGISTER			0x2858
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0			0x2880
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1			0x2884
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2			0x2888
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3			0x288c
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0		0x28a0
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1		0x28a4
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2		0x28a8
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3		0x28ac
-#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0		0x28e0
-#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1		0x28e4
-#define ETHERNET1_MIB_COUNTER_BASE				0x2900
-
-/* Ethernet 2 */
-
-#define ETHERNET2_PORT_CONFIGURATION_REGISTER			0x2c00
-#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER		0x2c08
-#define ETHERNET2_PORT_COMMAND_REGISTER				0x2c10
-#define ETHERNET2_PORT_STATUS_REGISTER				0x2c18
-#define ETHERNET2_SERIAL_PARAMETRS_REGISTER			0x2c20
-#define ETHERNET2_HASH_TABLE_POINTER_REGISTER			0x2c28
-#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW		0x2c30
-#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH		0x2c38
-#define ETHERNET2_SDMA_CONFIGURATION_REGISTER			0x2c40
-#define ETHERNET2_SDMA_COMMAND_REGISTER				0x2c48
-#define ETHERNET2_INTERRUPT_CAUSE_REGISTER			0x2c50
-#define ETHERNET2_INTERRUPT_MASK_REGISTER			0x2c58
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0			0x2c80
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1			0x2c84
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2			0x2c88
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3			0x2c8c
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0		0x2ca0
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1		0x2ca4
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2		0x2ca8
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3		0x2cac
-#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0		0x2ce0
-#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1		0x2ce4
-#define ETHERNET2_MIB_COUNTER_BASE				0x2d00
-
-/*
- * SDMA Registers
- */
-
-#define SDMA_GROUP_CONFIGURATION_REGISTER			0xb1f0
-#define CHANNEL0_CONFIGURATION_REGISTER				0x4000
-#define CHANNEL0_COMMAND_REGISTER				0x4008
-#define CHANNEL0_RX_CMD_STATUS					0x4800
-#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES			0x4804
-#define CHANNEL0_RX_BUFFER_POINTER				0x4808
-#define CHANNEL0_RX_NEXT_POINTER				0x480c
-#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER			0x4810
-#define CHANNEL0_TX_CMD_STATUS					0x4C00
-#define CHANNEL0_TX_PACKET_SIZE					0x4C04
-#define CHANNEL0_TX_BUFFER_POINTER				0x4C08
-#define CHANNEL0_TX_NEXT_POINTER				0x4C0c
-#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER			0x4c10
-#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER			0x4c14
-#define CHANNEL1_CONFIGURATION_REGISTER				0x6000
-#define CHANNEL1_COMMAND_REGISTER				0x6008
-#define CHANNEL1_RX_CMD_STATUS					0x6800
-#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES			0x6804
-#define CHANNEL1_RX_BUFFER_POINTER				0x6808
-#define CHANNEL1_RX_NEXT_POINTER				0x680c
-#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER			0x6810
-#define CHANNEL1_TX_CMD_STATUS					0x6C00
-#define CHANNEL1_TX_PACKET_SIZE					0x6C04
-#define CHANNEL1_TX_BUFFER_POINTER				0x6C08
-#define CHANNEL1_TX_NEXT_POINTER				0x6C0c
-#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER			0x6810
-#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER			0x6c10
-#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER			0x6c14
-
-/* SDMA Interrupt */
-
-#define SDMA_CAUSE						0xb820
-#define SDMA_MASK						0xb8a0
-
-
-/*
- * Baude Rate Generators Registers
- */
-
-/* BRG 0 */
-
-#define BRG0_CONFIGURATION_REGISTER				0xb200
-#define BRG0_BAUDE_TUNING_REGISTER				0xb204
-
-/* BRG 1 */
-
-#define BRG1_CONFIGURATION_REGISTER				0xb208
-#define BRG1_BAUDE_TUNING_REGISTER				0xb20c
-
-/* BRG 2 */
-
-#define BRG2_CONFIGURATION_REGISTER				0xb210
-#define BRG2_BAUDE_TUNING_REGISTER				0xb214
-
-/* BRG Interrupts */
-
-#define BRG_CAUSE_REGISTER					0xb834
-#define BRG_MASK_REGISTER					0xb8b4
-
-/* MISC */
-
-#define MAIN_ROUTING_REGISTER					0xb400
-#define RECEIVE_CLOCK_ROUTING_REGISTER				0xb404
-#define TRANSMIT_CLOCK_ROUTING_REGISTER				0xb408
-#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER		0xb40c
-#define WATCHDOG_CONFIGURATION_REGISTER				0xb410
-#define WATCHDOG_VALUE_REGISTER					0xb414
-
-
-/*
- * Flex TDM Registers
- */
-
-/* FTDM Port */
-
-#define FLEXTDM_TRANSMIT_READ_POINTER				0xa800
-#define FLEXTDM_RECEIVE_READ_POINTER				0xa804
-#define FLEXTDM_CONFIGURATION_REGISTER				0xa808
-#define FLEXTDM_AUX_CHANNELA_TX_REGISTER			0xa80c
-#define FLEXTDM_AUX_CHANNELA_RX_REGISTER			0xa810
-#define FLEXTDM_AUX_CHANNELB_TX_REGISTER			0xa814
-#define FLEXTDM_AUX_CHANNELB_RX_REGISTER			0xa818
-
-/* FTDM Interrupts */
-
-#define FTDM_CAUSE_REGISTER					0xb830
-#define FTDM_MASK_REGISTER					0xb8b0
-
-
-/*
- * GPP Interface Registers
- */
-
-#define GPP_IO_CONTROL						0xf100
-#define GPP_LEVEL_CONTROL					0xf110
-#define GPP_VALUE						0xf104
-#define GPP_INTERRUPT_CAUSE					0xf108
-#define GPP_INTERRUPT_MASK					0xf10c
-
-#define MPP_CONTROL0						0xf000
-#define MPP_CONTROL1						0xf004
-#define MPP_CONTROL2						0xf008
-#define MPP_CONTROL3						0xf00c
-#define DEBUG_PORT_MULTIPLEX					0xf014
-#define SERIAL_PORT_MULTIPLEX					0xf010
-
-/*
- * I2C Registers
- */
-
-#define I2C_SLAVE_ADDRESS					0xc000
-#define I2C_EXTENDED_SLAVE_ADDRESS				0xc040
-#define I2C_DATA						0xc004
-#define I2C_CONTROL						0xc008
-#define I2C_STATUS_BAUDE_RATE					0xc00C
-#define I2C_SOFT_RESET						0xc01c
-
-/*
- * MPSC Registers
- */
-
-/*
- * MPSC0
- */
-
-#define MPSC0_MAIN_CONFIGURATION_LOW				0x8000
-#define MPSC0_MAIN_CONFIGURATION_HIGH				0x8004
-#define MPSC0_PROTOCOL_CONFIGURATION				0x8008
-#define CHANNEL0_REGISTER1					0x800c
-#define CHANNEL0_REGISTER2					0x8010
-#define CHANNEL0_REGISTER3					0x8014
-#define CHANNEL0_REGISTER4					0x8018
-#define CHANNEL0_REGISTER5					0x801c
-#define CHANNEL0_REGISTER6					0x8020
-#define CHANNEL0_REGISTER7					0x8024
-#define CHANNEL0_REGISTER8					0x8028
-#define CHANNEL0_REGISTER9					0x802c
-#define CHANNEL0_REGISTER10					0x8030
-#define CHANNEL0_REGISTER11					0x8034
-
-/*
- * MPSC1
- */
-
-#define MPSC1_MAIN_CONFIGURATION_LOW				0x9000
-#define MPSC1_MAIN_CONFIGURATION_HIGH				0x9004
-#define MPSC1_PROTOCOL_CONFIGURATION				0x9008
-#define CHANNEL1_REGISTER1					0x900c
-#define CHANNEL1_REGISTER2					0x9010
-#define CHANNEL1_REGISTER3					0x9014
-#define CHANNEL1_REGISTER4					0x9018
-#define CHANNEL1_REGISTER5					0x901c
-#define CHANNEL1_REGISTER6					0x9020
-#define CHANNEL1_REGISTER7					0x9024
-#define CHANNEL1_REGISTER8					0x9028
-#define CHANNEL1_REGISTER9					0x902c
-#define CHANNEL1_REGISTER10					0x9030
-#define CHANNEL1_REGISTER11					0x9034
-
-/*
- * MPSCs Interupts
- */
-
-#define MPSC0_CAUSE						0xb804
-#define MPSC0_MASK						0xb884
-#define MPSC1_CAUSE						0xb80c
-#define MPSC1_MASK						0xb88c
-
-#endif	/* __ASM_MIPS_MV64240_H */
-- 
cgit v1.2.3


From 48d365e22641f8e3881d62e56ecb9fe79513a0e7 Mon Sep 17 00:00:00 2001
From: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Date: Sat, 4 Aug 2007 23:35:47 +0900
Subject: [MIPS] remove unused marvell.h

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
 include/asm-mips/marvell.h | 59 ----------------------------------------------
 1 file changed, 59 deletions(-)
 delete mode 100644 include/asm-mips/marvell.h

(limited to 'include')

diff --git a/include/asm-mips/marvell.h b/include/asm-mips/marvell.h
deleted file mode 100644
index b6144bafc565..000000000000
--- a/include/asm-mips/marvell.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004 by Ralf Baechle
- */
-#ifndef __ASM_MIPS_MARVELL_H
-#define __ASM_MIPS_MARVELL_H
-
-#include <linux/pci.h>
-
-#include <asm/byteorder.h>
-
-extern unsigned long marvell_base;
-
-/*
- * Because of an error/peculiarity in the Galileo chip, we need to swap the
- * bytes when running bigendian.
- */
-#define __MV_READ(ofs)							\
-	(*(volatile u32 *)(marvell_base+(ofs)))
-#define __MV_WRITE(ofs, data)						\
-	do { *(volatile u32 *)(marvell_base+(ofs)) = (data); } while (0)
-
-#define MV_READ(ofs)		le32_to_cpu(__MV_READ(ofs))
-#define MV_WRITE(ofs, data)	__MV_WRITE(ofs, cpu_to_le32(data))
-
-#define MV_READ_16(ofs)							\
-        le16_to_cpu(*(volatile u16 *)(marvell_base+(ofs)))
-#define MV_WRITE_16(ofs, data)  \
-        *(volatile u16 *)(marvell_base+(ofs)) = cpu_to_le16(data)
-
-#define MV_READ_8(ofs)							\
-	*(volatile u8 *)(marvell_base+(ofs))
-#define MV_WRITE_8(ofs, data)						\
-	*(volatile u8 *)(marvell_base+(ofs)) = data
-
-#define MV_SET_REG_BITS(ofs, bits)					\
-	(*((volatile u32 *)(marvell_base + (ofs)))) |= ((u32)cpu_to_le32(bits))
-#define MV_RESET_REG_BITS(ofs, bits)					\
-	(*((volatile u32 *)(marvell_base + (ofs)))) &= ~((u32)cpu_to_le32(bits))
-
-extern struct pci_ops mv_pci_ops;
-
-struct mv_pci_controller {
-	struct pci_controller   pcic;
-
-	/*
-	 * GT-64240/MV-64340 specific, per host bus information
-	 */
-	unsigned long   config_addr;
-	unsigned long   config_vreg;
-};
-
-extern void ll_mv64340_irq(void);
-extern void mv64340_irq_init(unsigned int base);
-
-#endif	/* __ASM_MIPS_MARVELL_H */
-- 
cgit v1.2.3


From fe56b954eadefb8b93b7d6b9244af38a352c8799 Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Mon, 6 Aug 2007 16:35:23 +0100
Subject: [MIPS] SMTC: Move MIPS_CPU_IPI_IRQ definition into header.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
 arch/mips/kernel/smtc.c |  2 --
 include/asm-mips/smtc.h | 10 ++++++++++
 2 files changed, 10 insertions(+), 2 deletions(-)

(limited to 'include')

diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 16aa5d37117c..43826c16101d 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -28,8 +28,6 @@
  * This file should be built into the kernel only if CONFIG_MIPS_MT_SMTC is set.
  */
 
-#define MIPS_CPU_IPI_IRQ	1
-
 #define LOCK_MT_PRA() \
 	local_irq_save(flags); \
 	mtflags = dmt()
diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h
index 44dfa4adecf3..ff3e8936b493 100644
--- a/include/asm-mips/smtc.h
+++ b/include/asm-mips/smtc.h
@@ -55,4 +55,14 @@ extern void smtc_boot_secondary(int cpu, struct task_struct *t);
 
 #define PARKED_INDEX	((unsigned int)0x80000000)
 
+/*
+ * Define low-level interrupt mask for IPIs, if necessary.
+ * By default, use SW interrupt 1, which requires no external
+ * hardware support, but which works only for single-core
+ * MIPS MT systems.
+ */
+#ifndef MIPS_CPU_IPI_IRQ
+#define MIPS_CPU_IPI_IRQ 1
+#endif
+
 #endif /*  _ASM_SMTC_MT_H */
-- 
cgit v1.2.3


From de4b21474053513d9ad41994c95dade3e6b3362f Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 7 Aug 2007 15:02:55 +0100
Subject: [MIPS] Fix build error if CONFIG_KALLSYMS is undefined.

  CC      arch/mips/kernel/traps.o
arch/mips/kernel/traps.c: In function 'show_backtrace':
arch/mips/kernel/traps.c:110: warning: unused variable 'ra'

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
 include/asm-mips/stacktrace.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/asm-mips/stacktrace.h b/include/asm-mips/stacktrace.h
index 07f873351a86..87bd7caec1cf 100644
--- a/include/asm-mips/stacktrace.h
+++ b/include/asm-mips/stacktrace.h
@@ -9,7 +9,10 @@ extern unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
 				  unsigned long pc, unsigned long *ra);
 #else
 #define raw_show_trace 1
-#define unwind_stack(task, sp, pc, ra)	0
+static inline unsigned long unwind_stack(struct task_struct *task,
+	unsigned long *sp, unsigned long pc, unsigned long *ra)
+{
+}
 #endif
 
 static __always_inline void prepare_frametrace(struct pt_regs *regs)
-- 
cgit v1.2.3


From b5438582090406e2ccb4169d9b2df7c9939ae42b Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 7 Aug 2007 17:18:28 +0100
Subject: [MIPS] SMTC: Fix crash on bootup with idebus= command line argument.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
 include/asm-mips/mach-generic/ide.h | 76 ++++++++++++-------------------------
 1 file changed, 25 insertions(+), 51 deletions(-)

(limited to 'include')

diff --git a/include/asm-mips/mach-generic/ide.h b/include/asm-mips/mach-generic/ide.h
index 6eba2e576aaa..2b928577be5d 100644
--- a/include/asm-mips/mach-generic/ide.h
+++ b/include/asm-mips/mach-generic/ide.h
@@ -29,68 +29,42 @@
 
 #define IDE_ARCH_OBSOLETE_DEFAULTS
 
-static __inline__ int ide_probe_legacy(void)
-{
-#ifdef CONFIG_PCI
-	struct pci_dev *dev;
-	if ((dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL)) != NULL ||
-	    (dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL)) != NULL) {
-		pci_dev_put(dev);
-
-		return 1;
-	}
-	return 0;
-#elif defined(CONFIG_EISA) || defined(CONFIG_ISA)
-	return 1;
-#else
-	return 0;
-#endif
-}
-
 static __inline__ int ide_default_irq(unsigned long base)
 {
-	if (ide_probe_legacy())
-		switch (base) {
-		case 0x1f0:
-			return 14;
-		case 0x170:
-			return 15;
-		case 0x1e8:
-			return 11;
-		case 0x168:
-			return 10;
-		case 0x1e0:
-			return 8;
-		case 0x160:
-			return 12;
+	switch (base) {
+		case 0x1f0: return 14;
+		case 0x170: return 15;
+		case 0x1e8: return 11;
+		case 0x168: return 10;
+		case 0x1e0: return 8;
+		case 0x160: return 12;
 		default:
 			return 0;
-		}
-	else
-		return 0;
+	}
 }
 
 static __inline__ unsigned long ide_default_io_base(int index)
 {
-	if (ide_probe_legacy())
+	/*
+	 *      If PCI is present then it is not safe to poke around
+	 *      the other legacy IDE ports. Only 0x1f0 and 0x170 are
+	 *      defined compatibility mode ports for PCI. A user can
+	 *      override this using ide= but we must default safe.
+	 */
+	if (no_pci_devices()) {
 		switch (index) {
-		case 0:
-			return 0x1f0;
-		case 1:
-			return 0x170;
-		case 2:
-			return 0x1e8;
-		case 3:
-			return 0x168;
-		case 4:
-			return 0x1e0;
-		case 5:
-			return 0x160;
-		default:
-			return 0;
+		case 2: return 0x1e8;
+		case 3: return 0x168;
+		case 4: return 0x1e0;
+		case 5: return 0x160;
 		}
-	else
+	}
+	switch (index) {
+	case 0: return 0x1f0;
+	case 1: return 0x170;
+	default:
 		return 0;
+	}
 }
 
 #define IDE_ARCH_OBSOLETE_INIT
-- 
cgit v1.2.3


From a204458acb358c147618c749ba0fac8ef2c5d4e6 Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 7 Aug 2007 17:30:58 +0100
Subject: [MIPS] unwind_stack should return a value ...

And gcc 3.4 doesn't even warn out this, grrr.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
 include/asm-mips/stacktrace.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include')

diff --git a/include/asm-mips/stacktrace.h b/include/asm-mips/stacktrace.h
index 87bd7caec1cf..0bf82818aa53 100644
--- a/include/asm-mips/stacktrace.h
+++ b/include/asm-mips/stacktrace.h
@@ -12,6 +12,7 @@ extern unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
 static inline unsigned long unwind_stack(struct task_struct *task,
 	unsigned long *sp, unsigned long pc, unsigned long *ra)
 {
+	return 0;
 }
 #endif
 
-- 
cgit v1.2.3


From 9975e77df5428a1afff57fd8f76a1bc0bfc247fc Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Mon, 13 Aug 2007 12:44:41 +0100
Subject: [MIPS] Gcc 3.3 build fixes.

Work around gcc 3.3's unability to evaluate that certain expressions indeed
are constant.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
 arch/mips/mm/init.c        | 9 ++++++++-
 include/asm-mips/pgtable.h | 6 +++++-
 2 files changed, 13 insertions(+), 2 deletions(-)

(limited to 'include')

diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index b8cb0dde3af0..09d91505b90c 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -26,6 +26,7 @@
 #include <linux/proc_fs.h>
 #include <linux/pfn.h>
 
+#include <asm/asm-offsets.h>
 #include <asm/bootinfo.h>
 #include <asm/cachectl.h>
 #include <asm/cpu.h>
@@ -498,7 +499,13 @@ unsigned long pgd_current[NR_CPUS];
  * different layout ...
  */
 #define __page_aligned(order) __attribute__((__aligned__(PAGE_SIZE<<order)))
-pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned(PGD_ORDER);
+
+/*
+ * gcc 3.3 and older have trouble determining that PTRS_PER_PGD and PGD_ORDER
+ * are constants.  So we use the variants from asm-offset.h until that gcc
+ * will officially be retired.
+ */
+pgd_t swapper_pg_dir[_PTRS_PER_PGD] __page_aligned(_PGD_ORDER);
 #ifdef CONFIG_64BIT
 #ifdef MODULE_START
 pgd_t module_pg_dir[PTRS_PER_PGD] __page_aligned(PGD_ORDER);
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index e2fb9dbac3fc..d2ee28156743 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -172,7 +172,11 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
 #define PMD_T_LOG2	(__builtin_ffs(sizeof(pmd_t)) - 1)
 #define PTE_T_LOG2	(__builtin_ffs(sizeof(pte_t)) - 1)
 
-extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+/*
+ * We used to declare this array with size but gcc 3.3 and older are not able
+ * to find that this expression is a constant, so the size is dropped.
+ */
+extern pgd_t swapper_pg_dir[];
 
 /*
  * The following only work if pte_present() is true.
-- 
cgit v1.2.3


From 1bfa771e610bebb29d8051884ff3672845ac9c00 Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Wed, 22 Aug 2007 22:42:18 +0100
Subject: [MIPS] Polish <asm/edac.h>.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
 include/asm-mips/edac.h | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

(limited to 'include')

diff --git a/include/asm-mips/edac.h b/include/asm-mips/edac.h
index 83719eee2d13..4da0c1fe30d9 100644
--- a/include/asm-mips/edac.h
+++ b/include/asm-mips/edac.h
@@ -9,8 +9,7 @@ static inline void atomic_scrub(void *va, u32 size)
 	unsigned long temp;
 	u32 i;
 
-	for (i = 0; i < size / sizeof(unsigned long); i++, virt_addr++) {
-
+	for (i = 0; i < size / sizeof(unsigned long); i++) {
 		/*
 		 * Very carefully read and write to memory atomically
 		 * so we are interrupt, DMA and SMP safe.
@@ -19,16 +18,16 @@ static inline void atomic_scrub(void *va, u32 size)
 		 */
 
 		__asm__ __volatile__ (
-		"       .set    mips3                                   \n"
-		"1:     ll      %0, %1          # atomic_add            \n"
-		"       ll      %0, %1          # atomic_add            \n"
-		"       addu    %0, $0                                  \n"
-		"       sc      %0, %1                                  \n"
-		"       beqz    %0, 1b                                  \n"
-		"       .set    mips0                                   \n"
+		"	.set	mips2					\n"
+		"1:	ll	%0, %1		# atomic_scrub		\n"
+		"	addu	%0, $0					\n"
+		"	sc	%0, %1					\n"
+		"	beqz	%0, 1b					\n"
+		"	.set	mips0					\n"
 		: "=&r" (temp), "=m" (*virt_addr)
 		: "m" (*virt_addr));
 
+		virt_addr++;
 	}
 }
 
-- 
cgit v1.2.3