From 1c305ea86bc32b3f38413ef3dbb1f3c288da024e Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Fri, 12 May 2023 17:53:44 +0530 Subject: dt-bindings: clock: qcom: Add GCC clocks for SDX75 Add support for qcom global clock controller bindings for SDX75 platform. Signed-off-by: Imran Shaik Signed-off-by: Taniya Das Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230512122347.1219-3-quic_tdas@quicinc.com --- include/dt-bindings/clock/qcom,sdx75-gcc.h | 193 +++++++++++++++++++++++++++++ 1 file changed, 193 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,sdx75-gcc.h (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,sdx75-gcc.h b/include/dt-bindings/clock/qcom,sdx75-gcc.h new file mode 100644 index 000000000000..a470e8c4fd41 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sdx75-gcc.h @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GPLL4 2 +#define GPLL5 3 +#define GPLL6 4 +#define GPLL8 5 +#define GCC_AHB_PCIE_LINK_CLK 6 +#define GCC_BOOT_ROM_AHB_CLK 7 +#define GCC_EEE_EMAC0_CLK 8 +#define GCC_EEE_EMAC0_CLK_SRC 9 +#define GCC_EEE_EMAC1_CLK 10 +#define GCC_EEE_EMAC1_CLK_SRC 11 +#define GCC_EMAC0_AXI_CLK 12 +#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK 13 +#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC 14 +#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK 15 +#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC 16 +#define GCC_EMAC0_PHY_AUX_CLK 17 +#define GCC_EMAC0_PHY_AUX_CLK_SRC 18 +#define GCC_EMAC0_PTP_CLK 19 +#define GCC_EMAC0_PTP_CLK_SRC 20 +#define GCC_EMAC0_RGMII_CLK 21 +#define GCC_EMAC0_RGMII_CLK_SRC 22 +#define GCC_EMAC0_RPCS_RX_CLK 23 +#define GCC_EMAC0_RPCS_TX_CLK 24 +#define GCC_EMAC0_SGMIIPHY_MAC_RCLK_SRC 25 +#define GCC_EMAC0_SGMIIPHY_MAC_TCLK_SRC 26 +#define GCC_EMAC0_SLV_AHB_CLK 27 +#define GCC_EMAC0_XGXS_RX_CLK 28 +#define GCC_EMAC0_XGXS_TX_CLK 29 +#define GCC_EMAC1_AXI_CLK 30 +#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK 31 +#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC 32 +#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK 33 +#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC 34 +#define GCC_EMAC1_PHY_AUX_CLK 35 +#define GCC_EMAC1_PHY_AUX_CLK_SRC 36 +#define GCC_EMAC1_PTP_CLK 37 +#define GCC_EMAC1_PTP_CLK_SRC 38 +#define GCC_EMAC1_RGMII_CLK 39 +#define GCC_EMAC1_RGMII_CLK_SRC 40 +#define GCC_EMAC1_RPCS_RX_CLK 41 +#define GCC_EMAC1_RPCS_TX_CLK 42 +#define GCC_EMAC1_SGMIIPHY_MAC_RCLK_SRC 43 +#define GCC_EMAC1_SGMIIPHY_MAC_TCLK_SRC 44 +#define GCC_EMAC1_SLV_AHB_CLK 45 +#define GCC_EMAC1_XGXS_RX_CLK 46 +#define GCC_EMAC1_XGXS_TX_CLK 47 +#define GCC_EMAC_0_CLKREF_EN 48 +#define GCC_EMAC_1_CLKREF_EN 49 +#define GCC_GP1_CLK 50 +#define GCC_GP1_CLK_SRC 51 +#define GCC_GP2_CLK 52 +#define GCC_GP2_CLK_SRC 53 +#define GCC_GP3_CLK 54 +#define GCC_GP3_CLK_SRC 55 +#define GCC_PCIE_0_CLKREF_EN 56 +#define GCC_PCIE_1_AUX_CLK 57 +#define GCC_PCIE_1_AUX_PHY_CLK_SRC 58 +#define GCC_PCIE_1_CFG_AHB_CLK 59 +#define GCC_PCIE_1_CLKREF_EN 60 +#define GCC_PCIE_1_MSTR_AXI_CLK 61 +#define GCC_PCIE_1_PHY_RCHNG_CLK 62 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 63 +#define GCC_PCIE_1_PIPE_CLK 64 +#define GCC_PCIE_1_PIPE_CLK_SRC 65 +#define GCC_PCIE_1_PIPE_DIV2_CLK 66 +#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC 67 +#define GCC_PCIE_1_SLV_AXI_CLK 68 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 69 +#define GCC_PCIE_2_AUX_CLK 70 +#define GCC_PCIE_2_AUX_PHY_CLK_SRC 71 +#define GCC_PCIE_2_CFG_AHB_CLK 72 +#define GCC_PCIE_2_CLKREF_EN 73 +#define GCC_PCIE_2_MSTR_AXI_CLK 74 +#define GCC_PCIE_2_PHY_RCHNG_CLK 75 +#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC 76 +#define GCC_PCIE_2_PIPE_CLK 77 +#define GCC_PCIE_2_PIPE_CLK_SRC 78 +#define GCC_PCIE_2_PIPE_DIV2_CLK 79 +#define GCC_PCIE_2_PIPE_DIV2_CLK_SRC 80 +#define GCC_PCIE_2_SLV_AXI_CLK 81 +#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 82 +#define GCC_PCIE_AUX_CLK 83 +#define GCC_PCIE_AUX_CLK_SRC 84 +#define GCC_PCIE_AUX_PHY_CLK_SRC 85 +#define GCC_PCIE_CFG_AHB_CLK 86 +#define GCC_PCIE_MSTR_AXI_CLK 87 +#define GCC_PCIE_PIPE_CLK 88 +#define GCC_PCIE_PIPE_CLK_SRC 89 +#define GCC_PCIE_RCHNG_PHY_CLK 90 +#define GCC_PCIE_RCHNG_PHY_CLK_SRC 91 +#define GCC_PCIE_SLEEP_CLK 92 +#define GCC_PCIE_SLV_AXI_CLK 93 +#define GCC_PCIE_SLV_Q2A_AXI_CLK 94 +#define GCC_PDM2_CLK 95 +#define GCC_PDM2_CLK_SRC 96 +#define GCC_PDM_AHB_CLK 97 +#define GCC_PDM_XO4_CLK 98 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 99 +#define GCC_QUPV3_WRAP0_CORE_CLK 100 +#define GCC_QUPV3_WRAP0_S0_CLK 101 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 102 +#define GCC_QUPV3_WRAP0_S1_CLK 103 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 104 +#define GCC_QUPV3_WRAP0_S2_CLK 105 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 106 +#define GCC_QUPV3_WRAP0_S3_CLK 107 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 108 +#define GCC_QUPV3_WRAP0_S4_CLK 109 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 110 +#define GCC_QUPV3_WRAP0_S5_CLK 111 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 112 +#define GCC_QUPV3_WRAP0_S6_CLK 113 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 114 +#define GCC_QUPV3_WRAP0_S7_CLK 115 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 116 +#define GCC_QUPV3_WRAP0_S8_CLK 117 +#define GCC_QUPV3_WRAP0_S8_CLK_SRC 118 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 119 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 120 +#define GCC_SDCC1_AHB_CLK 121 +#define GCC_SDCC1_APPS_CLK 122 +#define GCC_SDCC1_APPS_CLK_SRC 123 +#define GCC_SDCC2_AHB_CLK 124 +#define GCC_SDCC2_APPS_CLK 125 +#define GCC_SDCC2_APPS_CLK_SRC 126 +#define GCC_USB2_CLKREF_EN 127 +#define GCC_USB30_MASTER_CLK 128 +#define GCC_USB30_MASTER_CLK_SRC 129 +#define GCC_USB30_MOCK_UTMI_CLK 130 +#define GCC_USB30_MOCK_UTMI_CLK_SRC 131 +#define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC 132 +#define GCC_USB30_MSTR_AXI_CLK 133 +#define GCC_USB30_SLEEP_CLK 134 +#define GCC_USB30_SLV_AHB_CLK 135 +#define GCC_USB3_PHY_AUX_CLK 136 +#define GCC_USB3_PHY_AUX_CLK_SRC 137 +#define GCC_USB3_PHY_PIPE_CLK 138 +#define GCC_USB3_PHY_PIPE_CLK_SRC 139 +#define GCC_USB3_PRIM_CLKREF_EN 140 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 141 +#define GCC_XO_PCIE_LINK_CLK 142 + +/* GCC power domains */ +#define GCC_EMAC0_GDSC 0 +#define GCC_EMAC1_GDSC 1 +#define GCC_PCIE_1_GDSC 2 +#define GCC_PCIE_1_PHY_GDSC 3 +#define GCC_PCIE_2_GDSC 4 +#define GCC_PCIE_2_PHY_GDSC 5 +#define GCC_PCIE_GDSC 6 +#define GCC_PCIE_PHY_GDSC 7 +#define GCC_USB30_GDSC 8 +#define GCC_USB3_PHY_GDSC 9 + +/* GCC resets */ +#define GCC_EMAC0_BCR 0 +#define GCC_EMAC1_BCR 1 +#define GCC_EMMC_BCR 2 +#define GCC_PCIE_1_BCR 3 +#define GCC_PCIE_1_LINK_DOWN_BCR 4 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 5 +#define GCC_PCIE_1_PHY_BCR 6 +#define GCC_PCIE_2_BCR 7 +#define GCC_PCIE_2_LINK_DOWN_BCR 8 +#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 9 +#define GCC_PCIE_2_PHY_BCR 10 +#define GCC_PCIE_BCR 11 +#define GCC_PCIE_LINK_DOWN_BCR 12 +#define GCC_PCIE_NOCSR_COM_PHY_BCR 13 +#define GCC_PCIE_PHY_BCR 14 +#define GCC_PCIE_PHY_CFG_AHB_BCR 15 +#define GCC_PCIE_PHY_COM_BCR 16 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 17 +#define GCC_QUSB2PHY_BCR 18 +#define GCC_TCSR_PCIE_BCR 19 +#define GCC_USB30_BCR 20 +#define GCC_USB3_PHY_BCR 21 +#define GCC_USB3PHY_PHY_BCR 22 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 +#define GCC_EMAC0_RGMII_CLK_ARES 24 + +#endif -- cgit v1.2.3 From 1e910b2ba0edd639cc89b5495a3a832b28f77c7f Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 24 May 2023 19:36:54 +0530 Subject: dt-bindings: clock: qcom: Add SM8450 video clock controller Add device tree bindings for the video clock controller on Qualcomm SM8450 platform. Signed-off-by: Taniya Das Reviewed-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230524140656.7076-2-quic_tdas@quicinc.com --- .../bindings/clock/qcom,sm8450-videocc.yaml | 77 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,sm8450-videocc.h | 38 +++++++++++ 2 files changed, 115 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm8450-videocc.h (limited to 'include') diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml new file mode 100644 index 000000000000..fe1fda77b835 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on SM8450 + +maintainers: + - Taniya Das + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on SM8450. + + See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h + +properties: + compatible: + const: qcom,sm8450-videocc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: Video AHB clock from GCC + + power-domains: + maxItems: 1 + description: + MMCX power domain. + + required-opps: + maxItems: 1 + description: + A phandle to an OPP node describing required MMCX performance point. + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - power-domains + - required-opps + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + #include + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8450-videocc"; + reg = <0x0aaf0000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd SM8450_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm8450-videocc.h b/include/dt-bindings/clock/qcom,sm8450-videocc.h new file mode 100644 index 000000000000..9d795adfe4eb --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8450-videocc.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_MVS0_CLK 0 +#define VIDEO_CC_MVS0_CLK_SRC 1 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 2 +#define VIDEO_CC_MVS0C_CLK 3 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS1_CLK 5 +#define VIDEO_CC_MVS1_CLK_SRC 6 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 7 +#define VIDEO_CC_MVS1C_CLK 8 +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9 +#define VIDEO_CC_PLL0 10 +#define VIDEO_CC_PLL1 11 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0C_GDSC 0 +#define VIDEO_CC_MVS0_GDSC 1 +#define VIDEO_CC_MVS1C_GDSC 2 +#define VIDEO_CC_MVS1_GDSC 3 + +/* VIDEO_CC resets */ +#define CVP_VIDEO_CC_INTERFACE_BCR 0 +#define CVP_VIDEO_CC_MVS0_BCR 1 +#define CVP_VIDEO_CC_MVS0C_BCR 2 +#define CVP_VIDEO_CC_MVS1_BCR 3 +#define CVP_VIDEO_CC_MVS1C_BCR 4 +#define VIDEO_CC_MVS0C_CLK_ARES 5 +#define VIDEO_CC_MVS1C_CLK_ARES 6 + +#endif -- cgit v1.2.3 From 2aae5eaa941e356b5f6e78c207c7dc3a93286622 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 20 Apr 2023 19:32:50 +0200 Subject: dt-bindings: clock: Add SM8350 VIDEOCC SM8350, like most recent higher-end chips has a separate clock controller block just for the Venus IP. Document it. The binding was separated as the driver, unlike the earlier ones, doesn't expect clock-names to keep it easier to maintain. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230413-topic-lahaina_vidcc-v4-1-86c714a66a81@linaro.org --- .../bindings/clock/qcom,sm8350-videocc.yaml | 68 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,sm8350-videocc.h | 35 +++++++++++ include/dt-bindings/reset/qcom,sm8350-videocc.h | 18 ++++++ 3 files changed, 121 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm8350-videocc.h create mode 100644 include/dt-bindings/reset/qcom,sm8350-videocc.h (limited to 'include') diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml new file mode 100644 index 000000000000..23505c8c3dbd --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8350-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 Video Clock & Reset Controller + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on Qualcomm SoCs. + + See also:: + include/dt-bindings/clock/qcom,videocc-sm8350.h + include/dt-bindings/reset/qcom,videocc-sm8350.h + +properties: + compatible: + const: qcom,sm8350-videocc + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Board sleep clock + + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + +required: + - compatible + - clocks + - power-domains + - required-opps + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + clock-controller@abf0000 { + compatible = "qcom,sm8350-videocc"; + reg = <0x0abf0000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd SM8350_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm8350-videocc.h b/include/dt-bindings/clock/qcom,sm8350-videocc.h new file mode 100644 index 000000000000..b6945a448676 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8350-videocc.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H + +/* Clocks */ +#define VIDEO_CC_AHB_CLK_SRC 0 +#define VIDEO_CC_MVS0_CLK 1 +#define VIDEO_CC_MVS0_CLK_SRC 2 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 3 +#define VIDEO_CC_MVS0C_CLK 4 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 5 +#define VIDEO_CC_MVS1_CLK 6 +#define VIDEO_CC_MVS1_CLK_SRC 7 +#define VIDEO_CC_MVS1_DIV2_CLK 8 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 9 +#define VIDEO_CC_MVS1C_CLK 10 +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 11 +#define VIDEO_CC_SLEEP_CLK 12 +#define VIDEO_CC_SLEEP_CLK_SRC 13 +#define VIDEO_CC_XO_CLK_SRC 14 +#define VIDEO_PLL0 15 +#define VIDEO_PLL1 16 + +/* GDSCs */ +#define MVS0C_GDSC 0 +#define MVS1C_GDSC 1 +#define MVS0_GDSC 2 +#define MVS1_GDSC 3 + +#endif diff --git a/include/dt-bindings/reset/qcom,sm8350-videocc.h b/include/dt-bindings/reset/qcom,sm8350-videocc.h new file mode 100644 index 000000000000..cd356b207a4a --- /dev/null +++ b/include/dt-bindings/reset/qcom,sm8350-videocc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H +#define _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H + +#define VIDEO_CC_CVP_INTERFACE_BCR 0 +#define VIDEO_CC_CVP_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_CLK_ARES 2 +#define VIDEO_CC_CVP_MVS0C_BCR 3 +#define VIDEO_CC_CVP_MVS1_BCR 4 +#define VIDEO_CC_MVS1C_CLK_ARES 5 +#define VIDEO_CC_CVP_MVS1C_BCR 6 + +#endif -- cgit v1.2.3 From 63f4e4b6f54cdde98ca9c484724d4012989e3454 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 17 May 2023 18:40:38 +0200 Subject: dt-bindings: clock: Add Qcom SM8450 GPUCC Add device tree bindings for the graphics clock controller on Qualcomm Technology Inc's SM8450 SoCs. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-1-4f40e282af1d@linaro.org --- .../bindings/clock/qcom,sm8450-gpucc.yaml | 73 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,sm8450-gpucc.h | 48 ++++++++++++++ include/dt-bindings/reset/qcom,sm8450-gpucc.h | 20 ++++++ 3 files changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm8450-gpucc.h create mode 100644 include/dt-bindings/reset/qcom,sm8450-gpucc.h (limited to 'include') diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml new file mode 100644 index 000000000000..ad913b2daf0c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM8450 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides the clocks, resets and power + domains on Qualcomm SoCs. + + See also:: + include/dt-bindings/clock/qcom,sm8450-gpucc.h + include/dt-bindings/reset/qcom,sm8450-gpucc.h + +properties: + compatible: + enum: + - qcom,sm8450-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@3d90000 { + compatible = "qcom,sm8450-gpucc"; + reg = <0 0x03d90000 0 0xa000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm8450-gpucc.h b/include/dt-bindings/clock/qcom,sm8450-gpucc.h new file mode 100644 index 000000000000..712b171503d6 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8450-gpucc.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H + +/* Clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_APB_CLK 2 +#define GPU_CC_CX_FF_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CX_SNOC_DVM_CLK 5 +#define GPU_CC_CXO_AON_CLK 6 +#define GPU_CC_CXO_CLK 7 +#define GPU_CC_DEMET_CLK 8 +#define GPU_CC_DEMET_DIV_CLK_SRC 9 +#define GPU_CC_FF_CLK_SRC 10 +#define GPU_CC_FREQ_MEASURE_CLK 11 +#define GPU_CC_GMU_CLK_SRC 12 +#define GPU_CC_GX_FF_CLK 13 +#define GPU_CC_GX_GFX3D_CLK 14 +#define GPU_CC_GX_GFX3D_RDVM_CLK 15 +#define GPU_CC_GX_GMU_CLK 16 +#define GPU_CC_GX_VSENSE_CLK 17 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 18 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 19 +#define GPU_CC_HUB_AON_CLK 20 +#define GPU_CC_HUB_CLK_SRC 21 +#define GPU_CC_HUB_CX_INT_CLK 22 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 23 +#define GPU_CC_MEMNOC_GFX_CLK 24 +#define GPU_CC_MND1X_0_GFX3D_CLK 25 +#define GPU_CC_MND1X_1_GFX3D_CLK 26 +#define GPU_CC_PLL0 27 +#define GPU_CC_PLL1 28 +#define GPU_CC_SLEEP_CLK 29 +#define GPU_CC_XO_CLK_SRC 30 +#define GPU_CC_XO_DIV_CLK_SRC 31 + +/* GDSCs */ +#define GPU_GX_GDSC 0 +#define GPU_CX_GDSC 1 + +#endif diff --git a/include/dt-bindings/reset/qcom,sm8450-gpucc.h b/include/dt-bindings/reset/qcom,sm8450-gpucc.h new file mode 100644 index 000000000000..58ba8f987107 --- /dev/null +++ b/include/dt-bindings/reset/qcom,sm8450-gpucc.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H +#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H + +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CX_BCR 1 +#define GPUCC_GPU_CC_FAST_HUB_BCR 2 +#define GPUCC_GPU_CC_FF_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 +#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 8 + +#endif -- cgit v1.2.3 From 778af143adc8813d8851be401f71dfb80b9144eb Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 24 May 2023 23:47:58 +0530 Subject: dt-bindings: clock: qcom: Add SM8550 graphics clock controller Add device tree bindings for the graphics clock controller on Qualcomm SM8550 platform. Signed-off-by: Jagadeesh Kona Acked-by: Conor Dooley Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230524181800.28717-2-quic_jkona@quicinc.com --- .../bindings/clock/qcom,sm8450-gpucc.yaml | 2 + include/dt-bindings/clock/qcom,sm8550-gpucc.h | 48 ++++++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,sm8550-gpucc.h (limited to 'include') diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index ad913b2daf0c..2320be920a5f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -15,12 +15,14 @@ description: | See also:: include/dt-bindings/clock/qcom,sm8450-gpucc.h + include/dt-bindings/clock/qcom,sm8550-gpucc.h include/dt-bindings/reset/qcom,sm8450-gpucc.h properties: compatible: enum: - qcom,sm8450-gpucc + - qcom,sm8550-gpucc clocks: items: diff --git a/include/dt-bindings/clock/qcom,sm8550-gpucc.h b/include/dt-bindings/clock/qcom,sm8550-gpucc.h new file mode 100644 index 000000000000..a6760547a3ab --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8550-gpucc.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_FF_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CXO_AON_CLK 4 +#define GPU_CC_CXO_CLK 5 +#define GPU_CC_DEMET_CLK 6 +#define GPU_CC_DEMET_DIV_CLK_SRC 7 +#define GPU_CC_FF_CLK_SRC 8 +#define GPU_CC_FREQ_MEASURE_CLK 9 +#define GPU_CC_GMU_CLK_SRC 10 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 11 +#define GPU_CC_HUB_AON_CLK 12 +#define GPU_CC_HUB_CLK_SRC 13 +#define GPU_CC_HUB_CX_INT_CLK 14 +#define GPU_CC_MEMNOC_GFX_CLK 15 +#define GPU_CC_MND1X_0_GFX3D_CLK 16 +#define GPU_CC_MND1X_1_GFX3D_CLK 17 +#define GPU_CC_PLL0 18 +#define GPU_CC_PLL1 19 +#define GPU_CC_SLEEP_CLK 20 +#define GPU_CC_XO_CLK_SRC 21 +#define GPU_CC_XO_DIV_CLK_SRC 22 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CX_BCR 1 +#define GPUCC_GPU_CC_FAST_HUB_BCR 2 +#define GPUCC_GPU_CC_FF_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 + +#endif -- cgit v1.2.3 From bfc43a9c0ce5f3fcf98c972d7b7f21a742b7c957 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 8 Jun 2023 13:53:10 +0100 Subject: dt-bindings: clock: Add LPASSCC and reset controller for SC8280XP The LPASS (Low Power Audio Subsystem) clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla Reviewed-by: Johan Hovold Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230608125315.11454-2-srinivas.kandagatla@linaro.org --- .../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 50 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h | 12 ++++++ 2 files changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml create mode 100644 include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h (limited to 'include') diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml new file mode 100644 index 000000000000..047cae91f443 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc8280xp-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core & Audio Clock Controller on SC8280XP + +maintainers: + - Srinivas Kandagatla + +description: | + Qualcomm LPASS core and audio clock control module provides the clocks, + and reset on SC8280XP. + + See also:: + include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h + +properties: + compatible: + enum: + - qcom,sc8280xp-lpasscc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + lpasscc: clock-controller@33e0000 { + compatible = "qcom,sc8280xp-lpasscc"; + reg = <0x033e0000 0x12000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h new file mode 100644 index 000000000000..df800ea2741c --- /dev/null +++ b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Linaro Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H +#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H + +/* LPASS TCSR */ +#define LPASS_AUDIO_SWR_TX_CGCR 0 + +#endif -- cgit v1.2.3 From 83da70da40c93f3515aebcd5f2b8ff6283f64ee3 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 8 Jun 2023 13:53:11 +0100 Subject: dt-bindings: clock: Add LPASS AUDIOCC and reset controller for SC8280XP The LPASS (Low Power Audio Subsystem) Audio clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla Reviewed-by: Johan Hovold Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230608125315.11454-3-srinivas.kandagatla@linaro.org --- .../devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml | 10 ++++++++++ include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h | 5 +++++ 2 files changed, 15 insertions(+) (limited to 'include') diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml index 047cae91f443..3326dcd6766c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml @@ -19,6 +19,7 @@ description: | properties: compatible: enum: + - qcom,sc8280xp-lpassaudiocc - qcom,sc8280xp-lpasscc reg: @@ -39,6 +40,15 @@ required: additionalProperties: false examples: + - | + #include + lpass_audiocc: clock-controller@32a9000 { + compatible = "qcom,sc8280xp-lpassaudiocc"; + reg = <0x032a9000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + - | #include lpasscc: clock-controller@33e0000 { diff --git a/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h index df800ea2741c..d190d57fc81a 100644 --- a/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h +++ b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h @@ -6,6 +6,11 @@ #ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H #define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H +/* LPASS AUDIO CC CSR */ +#define LPASS_AUDIO_SWR_RX_CGCR 0 +#define LPASS_AUDIO_SWR_WSA_CGCR 1 +#define LPASS_AUDIO_SWR_WSA2_CGCR 2 + /* LPASS TCSR */ #define LPASS_AUDIO_SWR_TX_CGCR 0 -- cgit v1.2.3 From 35e237b3d59941cff839de2d4089db60fac4679f Mon Sep 17 00:00:00 2001 From: Anusha Rao Date: Fri, 26 May 2023 21:41:26 +0530 Subject: dt-bindings: clock: Add crypto clock and reset definitions Add crypto clock and reset ID definitions for ipq9574. Acked-by: Krzysztof Kozlowski Reviewed-by: Bhupesh Sharma Signed-off-by: Anusha Rao Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526161129.1454-2-quic_anusha@quicinc.com --- include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 ++++ include/dt-bindings/reset/qcom,ipq9574-gcc.h | 1 + 2 files changed, 5 insertions(+) (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index 5a2961bfe893..b32a7aa65349 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -210,4 +210,8 @@ #define GCC_SNOC_PCIE1_1LANE_S_CLK 201 #define GCC_SNOC_PCIE2_2LANE_S_CLK 202 #define GCC_SNOC_PCIE3_2LANE_S_CLK 203 +#define GCC_CRYPTO_CLK_SRC 204 +#define GCC_CRYPTO_CLK 205 +#define GCC_CRYPTO_AXI_CLK 206 +#define GCC_CRYPTO_AHB_CLK 207 #endif diff --git a/include/dt-bindings/reset/qcom,ipq9574-gcc.h b/include/dt-bindings/reset/qcom,ipq9574-gcc.h index d01dc6a24cf1..c709d103673d 100644 --- a/include/dt-bindings/reset/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/reset/qcom,ipq9574-gcc.h @@ -160,5 +160,6 @@ #define GCC_WCSS_Q6_BCR 151 #define GCC_WCSS_Q6_TBU_BCR 152 #define GCC_TCSR_BCR 153 +#define GCC_CRYPTO_BCR 154 #endif -- cgit v1.2.3