From 1fb83132603c7c7c1b9431c4e98194a233613a2a Mon Sep 17 00:00:00 2001 From: Xuyang Dong Date: Tue, 3 Mar 2026 16:06:37 +0800 Subject: dt-bindings: clock: eswin: Documentation for eic7700 SoC Add device tree binding documentation for the ESWIN eic7700 clock controller module. Signed-off-by: Yifeng Huang Acked-by: Conor Dooley Acked-by: Troy Mitchell Tested-by: Marcel Ziswiler # ebc77 Signed-off-by: Xuyang Dong Signed-off-by: Stephen Boyd --- include/dt-bindings/clock/eswin,eic7700-clock.h | 285 ++++++++++++++++++++++++ 1 file changed, 285 insertions(+) create mode 100644 include/dt-bindings/clock/eswin,eic7700-clock.h (limited to 'include') diff --git a/include/dt-bindings/clock/eswin,eic7700-clock.h b/include/dt-bindings/clock/eswin,eic7700-clock.h new file mode 100644 index 000000000000..d7ef697d0f7a --- /dev/null +++ b/include/dt-bindings/clock/eswin,eic7700-clock.h @@ -0,0 +1,285 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * Device Tree binding constants for EIC7700 clock controller. + * + * Authors: + * Yifeng Huang + * Xuyang Dong + */ + +#ifndef _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ +#define _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ + +#define EIC7700_CLK_XTAL_32K 0 +#define EIC7700_CLK_PLL_CPU 1 +#define EIC7700_CLK_SPLL0_FOUT1 2 +#define EIC7700_CLK_SPLL0_FOUT2 3 +#define EIC7700_CLK_SPLL0_FOUT3 4 +#define EIC7700_CLK_SPLL1_FOUT1 5 +#define EIC7700_CLK_SPLL1_FOUT2 6 +#define EIC7700_CLK_SPLL1_FOUT3 7 +#define EIC7700_CLK_SPLL2_FOUT1 8 +#define EIC7700_CLK_SPLL2_FOUT2 9 +#define EIC7700_CLK_SPLL2_FOUT3 10 +#define EIC7700_CLK_VPLL_FOUT1 11 +#define EIC7700_CLK_VPLL_FOUT2 12 +#define EIC7700_CLK_VPLL_FOUT3 13 +#define EIC7700_CLK_APLL_FOUT1 14 +#define EIC7700_CLK_APLL_FOUT2 15 +#define EIC7700_CLK_APLL_FOUT3 16 +#define EIC7700_CLK_EXT_MCLK 17 +#define EIC7700_CLK_LPDDR_REF_BAK 18 +#define EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE 19 +#define EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE 20 +#define EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE 21 +#define EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE 22 +#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0 23 +#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1 24 +#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2 25 +#define EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE 26 +#define EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE 27 +#define EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE 28 +#define EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE 29 +#define EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE 30 +#define EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE 31 +#define EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1 32 +#define EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE 33 +#define EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE 34 +#define EIC7700_CLK_MUX_SATA_PHY_2MUX1 35 +#define EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE 36 +#define EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE 37 +#define EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE 38 +#define EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK 39 +#define EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE 40 +#define EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE 41 +#define EIC7700_CLK_MUX_RMII_REF_2MUX 42 +#define EIC7700_CLK_MUX_ETH_CORE_2MUX1 43 +#define EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1 44 +#define EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE 45 +#define EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE 46 +#define EIC7700_CLK_DIV_SYS_CFG_DYNM 47 +#define EIC7700_CLK_DIV_NOC_NSP_DYNM 48 +#define EIC7700_CLK_DIV_BOOTSPI_DYNM 49 +#define EIC7700_CLK_DIV_SCPU_CORE_DYNM 50 +#define EIC7700_CLK_DIV_LPCPU_CORE_DYNM 51 +#define EIC7700_CLK_DIV_GPU_ACLK_DYNM 52 +#define EIC7700_CLK_DIV_DSP_ACLK_DYNM 53 +#define EIC7700_CLK_DIV_D2D_ACLK_DYNM 54 +#define EIC7700_CLK_DIV_HSP_ACLK_DYNM 55 +#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0 56 +#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1 57 +#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_0 58 +#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_1 59 +#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_2 60 +#define EIC7700_CLK_DIV_PCIE_ACLK_DYNM 61 +#define EIC7700_CLK_DIV_NPU_ACLK_DYNM 62 +#define EIC7700_CLK_DIV_NPU_LLC_SRC0_DYNM 63 +#define EIC7700_CLK_DIV_NPU_LLC_SRC1_DYNM 64 +#define EIC7700_CLK_DIV_NPU_CORECLK_DYNM 65 +#define EIC7700_CLK_DIV_VI_ACLK_DYNM 66 +#define EIC7700_CLK_DIV_VI_DVP_DYNM 67 +#define EIC7700_CLK_DIV_VI_DIG_ISP_DYNM 68 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0 69 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1 70 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2 71 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3 72 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4 73 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5 74 +#define EIC7700_CLK_DIV_VO_ACLK_DYNM 75 +#define EIC7700_CLK_DIV_IESMCLK_DYNM 76 +#define EIC7700_CLK_DIV_VO_PIXEL_DYNM 77 +#define EIC7700_CLK_DIV_VO_MCLK_DYNM 78 +#define EIC7700_CLK_DIV_VC_ACLK_DYNM 79 +#define EIC7700_CLK_DIV_JD_DYNM 80 +#define EIC7700_CLK_DIV_JE_DYNM 81 +#define EIC7700_CLK_DIV_VE_DYNM 82 +#define EIC7700_CLK_DIV_VD_DYNM 83 +#define EIC7700_CLK_DIV_G2D_DYNM 84 +#define EIC7700_CLK_DIV_AONDMA_AXI_DYNM 85 +#define EIC7700_CLK_DIV_CRYPTO_DYNM 86 +#define EIC7700_CLK_DIV_VI_DW_DYNM 87 +#define EIC7700_CLK_DIV_NPU_E31_DYNM 88 +#define EIC7700_CLK_DIV_SATA_PHY_REF_DYNM 89 +#define EIC7700_CLK_DIV_DSP_0_ACLK_DYNM 90 +#define EIC7700_CLK_DIV_DSP_1_ACLK_DYNM 91 +#define EIC7700_CLK_DIV_DSP_2_ACLK_DYNM 92 +#define EIC7700_CLK_DIV_DSP_3_ACLK_DYNM 93 +#define EIC7700_CLK_DIV_DDR_ACLK_DYNM 94 +#define EIC7700_CLK_DIV_AON_RTC_DYNM 95 +#define EIC7700_CLK_DIV_U84_RTC_TOGGLE_DYNM 96 +#define EIC7700_CLK_DIV_VO_CEC_DYNM 97 +#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_0 98 +#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_1 99 +#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_2 100 +#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_3 101 +#define EIC7700_CLK_GATE_CPU_TRACE_CLK_0 102 +#define EIC7700_CLK_GATE_CPU_TRACE_CLK_1 103 +#define EIC7700_CLK_GATE_CPU_TRACE_CLK_2 104 +#define EIC7700_CLK_GATE_CPU_TRACE_CLK_3 105 +#define EIC7700_CLK_GATE_CPU_TRACE_COM_CLK 106 +#define EIC7700_CLK_GATE_SPLL0_FOUT2 107 +#define EIC7700_CLK_GATE_NOC_NSP_CLK 108 +#define EIC7700_CLK_GATE_BOOTSPI 109 +#define EIC7700_CLK_GATE_BOOTSPI_CFG 110 +#define EIC7700_CLK_GATE_SCPU_CORE 111 +#define EIC7700_CLK_GATE_SCPU_BUS 112 +#define EIC7700_CLK_GATE_LPCPU_CORE 113 +#define EIC7700_CLK_GATE_LPCPU_BUS 114 +#define EIC7700_CLK_GATE_GPU_ACLK 115 +#define EIC7700_CLK_GATE_GPU_GRAY_CLK 116 +#define EIC7700_CLK_GATE_GPU_CFG_CLK 117 +#define EIC7700_CLK_GATE_DSPT_ACLK 118 +#define EIC7700_CLK_GATE_DSPT_CFG_CLK 119 +#define EIC7700_CLK_GATE_D2D_ACLK 120 +#define EIC7700_CLK_GATE_D2D_CFG_CLK 121 +#define EIC7700_CLK_GATE_TCU_ACLK 122 +#define EIC7700_CLK_GATE_TCU_CFG_CLK 123 +#define EIC7700_CLK_GATE_DDRT_CFG_CLK 124 +#define EIC7700_CLK_GATE_DDRT0_P0_ACLK 125 +#define EIC7700_CLK_GATE_DDRT0_P1_ACLK 126 +#define EIC7700_CLK_GATE_DDRT0_P2_ACLK 127 +#define EIC7700_CLK_GATE_DDRT0_P3_ACLK 128 +#define EIC7700_CLK_GATE_DDRT0_P4_ACLK 129 +#define EIC7700_CLK_GATE_DDRT1_P0_ACLK 130 +#define EIC7700_CLK_GATE_DDRT1_P1_ACLK 131 +#define EIC7700_CLK_GATE_DDRT1_P2_ACLK 132 +#define EIC7700_CLK_GATE_DDRT1_P3_ACLK 133 +#define EIC7700_CLK_GATE_DDRT1_P4_ACLK 134 +#define EIC7700_CLK_GATE_TIMER_CLK_0 135 +#define EIC7700_CLK_GATE_TIMER_CLK_1 136 +#define EIC7700_CLK_GATE_TIMER_CLK_2 137 +#define EIC7700_CLK_GATE_TIMER_CLK_3 138 +#define EIC7700_CLK_GATE_TIMER_PCLK_0 139 +#define EIC7700_CLK_GATE_TIMER_PCLK_1 140 +#define EIC7700_CLK_GATE_TIMER_PCLK_2 141 +#define EIC7700_CLK_GATE_TIMER_PCLK_3 142 +#define EIC7700_CLK_GATE_TIMER3_CLK8 143 +#define EIC7700_CLK_GATE_PCIET_ACLK 144 +#define EIC7700_CLK_GATE_PCIET_CFG_CLK 145 +#define EIC7700_CLK_GATE_PCIET_CR_CLK 146 +#define EIC7700_CLK_GATE_PCIET_AUX_CLK 147 +#define EIC7700_CLK_GATE_NPU_ACLK 148 +#define EIC7700_CLK_GATE_NPU_CFG_CLK 149 +#define EIC7700_CLK_GATE_NPU_LLC_ACLK 150 +#define EIC7700_CLK_GATE_NPU_CLK 151 +#define EIC7700_CLK_GATE_NPU_E31_CLK 152 +#define EIC7700_CLK_GATE_VI_ACLK 153 +#define EIC7700_CLK_GATE_VI_DVP_CLK 154 +#define EIC7700_CLK_GATE_VI_CFG_CLK 155 +#define EIC7700_CLK_GATE_VI_DIG_DW_CLK 156 +#define EIC7700_CLK_GATE_VI_DIG_ISP_CLK 157 +#define EIC7700_CLK_GATE_VI_SHUTTER_0 158 +#define EIC7700_CLK_GATE_VI_SHUTTER_1 159 +#define EIC7700_CLK_GATE_VI_SHUTTER_2 160 +#define EIC7700_CLK_GATE_VI_SHUTTER_3 161 +#define EIC7700_CLK_GATE_VI_SHUTTER_4 162 +#define EIC7700_CLK_GATE_VI_SHUTTER_5 163 +#define EIC7700_CLK_GATE_VI_PHY_TXCLKESC 164 +#define EIC7700_CLK_GATE_VI_PHY_CFG 165 +#define EIC7700_CLK_GATE_VO_ACLK 166 +#define EIC7700_CLK_GATE_VO_CFG_CLK 167 +#define EIC7700_CLK_GATE_VO_HDMI_IESMCLK 168 +#define EIC7700_CLK_GATE_VO_PIXEL_CLK 169 +#define EIC7700_CLK_GATE_VO_I2S_MCLK 170 +#define EIC7700_CLK_GATE_HSP_CFG_CLK 171 +#define EIC7700_CLK_GATE_VC_ACLK 172 +#define EIC7700_CLK_GATE_VC_CFG_CLK 173 +#define EIC7700_CLK_GATE_VC_JE_CLK 174 +#define EIC7700_CLK_GATE_VC_JD_CLK 175 +#define EIC7700_CLK_GATE_VC_VE_CLK 176 +#define EIC7700_CLK_GATE_VC_VD_CLK 177 +#define EIC7700_CLK_GATE_G2D_CFG_CLK 178 +#define EIC7700_CLK_GATE_G2D_CLK 179 +#define EIC7700_CLK_GATE_G2D_ACLK 180 +#define EIC7700_CLK_GATE_AONDMA_CFG 181 +#define EIC7700_CLK_GATE_AONDMA_ACLK 182 +#define EIC7700_CLK_GATE_AON_ACLK 183 +#define EIC7700_CLK_GATE_HSP_SATA_RBC_CLK 184 +#define EIC7700_CLK_GATE_VO_CR_CLK 185 +#define EIC7700_CLK_GATE_HSP_ACLK 186 +#define EIC7700_CLK_GATE_HSP_SATA_OOB_CLK 187 +#define EIC7700_CLK_GATE_RTC_CFG 188 +#define EIC7700_CLK_GATE_RTC 189 +#define EIC7700_CLK_GATE_HSP_MSHC0_CORE_CLK 190 +#define EIC7700_CLK_GATE_HSP_MSHC1_CORE_CLK 191 +#define EIC7700_CLK_GATE_HSP_MSHC2_CORE_CLK 192 +#define EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK 193 +#define EIC7700_CLK_GATE_HSP_ETH1_CORE_CLK 194 +#define EIC7700_CLK_GATE_HSP_RMII_REF_0 195 +#define EIC7700_CLK_GATE_HSP_RMII_REF_1 196 +#define EIC7700_CLK_GATE_PKA_CFG 197 +#define EIC7700_CLK_GATE_SPACC_CFG 198 +#define EIC7700_CLK_GATE_CRYPTO 199 +#define EIC7700_CLK_GATE_TRNG_CFG 200 +#define EIC7700_CLK_GATE_OTP_CFG 201 +#define EIC7700_CLK_GATE_MAILBOX_0 202 +#define EIC7700_CLK_GATE_MAILBOX_1 203 +#define EIC7700_CLK_GATE_MAILBOX_2 204 +#define EIC7700_CLK_GATE_MAILBOX_3 205 +#define EIC7700_CLK_GATE_MAILBOX_4 206 +#define EIC7700_CLK_GATE_MAILBOX_5 207 +#define EIC7700_CLK_GATE_MAILBOX_6 208 +#define EIC7700_CLK_GATE_MAILBOX_7 209 +#define EIC7700_CLK_GATE_MAILBOX_8 210 +#define EIC7700_CLK_GATE_MAILBOX_9 211 +#define EIC7700_CLK_GATE_MAILBOX_10 212 +#define EIC7700_CLK_GATE_MAILBOX_11 213 +#define EIC7700_CLK_GATE_MAILBOX_12 214 +#define EIC7700_CLK_GATE_MAILBOX_13 215 +#define EIC7700_CLK_GATE_MAILBOX_14 216 +#define EIC7700_CLK_GATE_MAILBOX_15 217 +#define EIC7700_CLK_GATE_LSP_I2C0_PCLK 218 +#define EIC7700_CLK_GATE_LSP_I2C1_PCLK 219 +#define EIC7700_CLK_GATE_LSP_I2C2_PCLK 220 +#define EIC7700_CLK_GATE_LSP_I2C3_PCLK 221 +#define EIC7700_CLK_GATE_LSP_I2C4_PCLK 222 +#define EIC7700_CLK_GATE_LSP_I2C5_PCLK 223 +#define EIC7700_CLK_GATE_LSP_I2C6_PCLK 224 +#define EIC7700_CLK_GATE_LSP_I2C7_PCLK 225 +#define EIC7700_CLK_GATE_LSP_I2C8_PCLK 226 +#define EIC7700_CLK_GATE_LSP_I2C9_PCLK 227 +#define EIC7700_CLK_GATE_LSP_WDT0_PCLK 228 +#define EIC7700_CLK_GATE_LSP_WDT1_PCLK 229 +#define EIC7700_CLK_GATE_LSP_WDT2_PCLK 230 +#define EIC7700_CLK_GATE_LSP_WDT3_PCLK 231 +#define EIC7700_CLK_GATE_LSP_SSI0_PCLK 232 +#define EIC7700_CLK_GATE_LSP_SSI1_PCLK 233 +#define EIC7700_CLK_GATE_LSP_PVT_PCLK 234 +#define EIC7700_CLK_GATE_AON_I2C0_PCLK 235 +#define EIC7700_CLK_GATE_AON_I2C1_PCLK 236 +#define EIC7700_CLK_GATE_LSP_UART0_PCLK 237 +#define EIC7700_CLK_GATE_LSP_UART1_PCLK 238 +#define EIC7700_CLK_GATE_LSP_UART2_PCLK 239 +#define EIC7700_CLK_GATE_LSP_UART3_PCLK 240 +#define EIC7700_CLK_GATE_LSP_UART4_PCLK 241 +#define EIC7700_CLK_GATE_LSP_TIMER_PCLK 242 +#define EIC7700_CLK_GATE_LSP_FAN_PCLK 243 +#define EIC7700_CLK_GATE_LSP_PVT0_CLK 244 +#define EIC7700_CLK_GATE_LSP_PVT1_CLK 245 +#define EIC7700_CLK_GATE_VC_JE_PCLK 246 +#define EIC7700_CLK_GATE_VC_JD_PCLK 247 +#define EIC7700_CLK_GATE_VC_VE_PCLK 248 +#define EIC7700_CLK_GATE_VC_VD_PCLK 249 +#define EIC7700_CLK_GATE_VC_MON_PCLK 250 +#define EIC7700_CLK_GATE_HSP_DMA0_CLK 251 +#define EIC7700_CLK_GATE_HSP_DMA0_CLK_TEST 252 +#define EIC7700_CLK_FIXED_FACTOR_CPU_DIV2 253 +#define EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24 254 +#define EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10 255 +#define EIC7700_CLK_FIXED_FACTOR_U84_CORE_LP_DIV2 256 +#define EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2 257 +#define EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2 258 +#define EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2 259 +#define EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4 260 +#define EIC7700_CLK_FIXED_FACTOR_PVT_DIV20 261 +#define EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6 262 +#define EIC7700_CLK_DIV_NOC_WDREF_DYNM 263 +#define EIC7700_CLK_GATE_DDR0_TRACE 264 +#define EIC7700_CLK_GATE_DDR1_TRACE 265 +#define EIC7700_CLK_GATE_RNOC_NSP 266 +#define EIC7700_CLK_GATE_NOC_WDREF 267 + +#endif /* _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ */ -- cgit v1.2.3 From 8add6d87dc69c0620c7e60bdc6be6b3b0092d9fa Mon Sep 17 00:00:00 2001 From: Xuyang Dong Date: Tue, 3 Mar 2026 16:06:55 +0800 Subject: clk: divider: Add devm_clk_hw_register_divider_parent_data Add the devres variant of clk_hw_register_divider_parent_data() for registering a divider clock with parent clk data instead of parent name. Reviewed-by: Brian Masney Signed-off-by: Xuyang Dong Signed-off-by: Stephen Boyd --- include/linux/clk-provider.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'include') diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 630705a47129..64967ac1b1df 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -947,6 +947,26 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, (parent_hw), NULL, (flags), (reg), \ (shift), (width), (clk_divider_flags), \ NULL, (lock)) +/** + * devm_clk_hw_register_divider_parent_data - register a divider clock with the + * clock framework + * @dev: device registering this clock + * @name: name of this clock + * @parent_data: parent clk data + * @flags: framework-specific flags + * @reg: register address to adjust divider + * @shift: number of bits to shift the bitfield + * @width: width of the bitfield + * @clk_divider_flags: divider-specific flags for this clock + * @lock: shared register lock for this clock + */ +#define devm_clk_hw_register_divider_parent_data(dev, name, parent_data, \ + flags, reg, shift, width, \ + clk_divider_flags, lock) \ + __devm_clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \ + (parent_data), (flags), (reg), (shift), \ + (width), (clk_divider_flags), NULL, \ + (lock)) /** * devm_clk_hw_register_divider_table - register a table based divider clock * with the clock framework (devres variant) -- cgit v1.2.3 From 35af99f7482673bf5f5391fd33caf266f4f62aeb Mon Sep 17 00:00:00 2001 From: Caleb James DeLisle Date: Thu, 12 Mar 2026 16:24:48 +0000 Subject: dt-bindings: clock, reset: Add econet EN751221 Add clock and reset bindings for EN751221 as well as a "chip-scu" which is an additional regmap that is used by the clock driver as well as others. This split of the SCU across two register areas is the same as the Airoha AN758x family. Signed-off-by: Caleb James DeLisle Reviewed-by: Rob Herring (Arm) Signed-off-by: Stephen Boyd --- .../bindings/clock/airoha,en7523-scu.yaml | 6 ++- Documentation/devicetree/bindings/mfd/syscon.yaml | 2 + MAINTAINERS | 2 + include/dt-bindings/clock/econet,en751221-scu.h | 12 ++++++ include/dt-bindings/reset/econet,en751221-scu.h | 49 ++++++++++++++++++++++ 5 files changed, 70 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/clock/econet,en751221-scu.h create mode 100644 include/dt-bindings/reset/econet,en751221-scu.h (limited to 'include') diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml index a8471367175b..eb24a5687639 100644 --- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -32,6 +32,7 @@ properties: - enum: - airoha,en7523-scu - airoha,en7581-scu + - econet,en751221-scu reg: items: @@ -67,7 +68,9 @@ allOf: - if: properties: compatible: - const: airoha,en7581-scu + enum: + - airoha,en7581-scu + - econet,en751221-scu then: properties: reg: @@ -98,3 +101,4 @@ examples: #reset-cells = <1>; }; }; + diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index e57add2bacd3..e22867088063 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -61,6 +61,7 @@ select: - cirrus,ep7209-syscon2 - cirrus,ep7209-syscon3 - cnxt,cx92755-uc + - econet,en751221-chip-scu - freecom,fsg-cs2-system-controller - fsl,imx93-aonmix-ns-syscfg - fsl,imx93-wakeupmix-syscfg @@ -173,6 +174,7 @@ properties: - cirrus,ep7209-syscon2 - cirrus,ep7209-syscon3 - cnxt,cx92755-uc + - econet,en751221-chip-scu - freecom,fsg-cs2-system-controller - fsl,imx93-aonmix-ns-syscfg - fsl,imx93-wakeupmix-syscfg diff --git a/MAINTAINERS b/MAINTAINERS index 7d10988cbc62..8895a43d68de 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9096,6 +9096,8 @@ F: arch/mips/boot/dts/econet/ F: arch/mips/econet/ F: drivers/clocksource/timer-econet-en751221.c F: drivers/irqchip/irq-econet-en751221.c +F: include/dt-bindings/clock/econet,en751221-scu.h +F: include/dt-bindings/reset/econet,en751221-scu.h ECRYPT FILE SYSTEM M: Tyler Hicks diff --git a/include/dt-bindings/clock/econet,en751221-scu.h b/include/dt-bindings/clock/econet,en751221-scu.h new file mode 100644 index 000000000000..318ec8a4670e --- /dev/null +++ b/include/dt-bindings/clock/econet,en751221-scu.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_ +#define _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_ + +#define EN751221_CLK_PCIE 0 +#define EN751221_CLK_SPI 1 +#define EN751221_CLK_BUS 2 +#define EN751221_CLK_CPU 3 +#define EN751221_CLK_GSW 4 + +#endif /* _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_ */ diff --git a/include/dt-bindings/reset/econet,en751221-scu.h b/include/dt-bindings/reset/econet,en751221-scu.h new file mode 100644 index 000000000000..bad499d4d50a --- /dev/null +++ b/include/dt-bindings/reset/econet,en751221-scu.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_ +#define __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_ + +#define EN751221_XPON_PHY_RST 0 +#define EN751221_PCM1_ZSI_ISI_RST 1 +#define EN751221_FE_QDMA1_RST 2 +#define EN751221_FE_QDMA2_RST 3 +#define EN751221_FE_UNZIP_RST 4 +#define EN751221_PCM2_RST 5 +#define EN751221_PTM_MAC_RST 6 +#define EN751221_CRYPTO_RST 7 +#define EN751221_SAR_RST 8 +#define EN751221_TIMER_RST 9 +#define EN751221_INTC_RST 10 +#define EN751221_BONDING_RST 11 +#define EN751221_PCM1_RST 12 +#define EN751221_UART_RST 13 +#define EN751221_GPIO_RST 14 +#define EN751221_GDMA_RST 15 +#define EN751221_I2C_MASTER_RST 16 +#define EN751221_PCM2_ZSI_ISI_RST 17 +#define EN751221_SFC_RST 18 +#define EN751221_UART2_RST 19 +#define EN751221_GDMP_RST 20 +#define EN751221_FE_RST 21 +#define EN751221_USB_HOST_P0_RST 22 +#define EN751221_GSW_RST 23 +#define EN751221_SFC2_PCM_RST 24 +#define EN751221_PCIE0_RST 25 +#define EN751221_PCIE1_RST 26 +#define EN751221_CPU_TIMER_RST 27 +#define EN751221_PCIE_HB_RST 28 +#define EN751221_SIMIF_RST 29 +#define EN751221_XPON_MAC_RST 30 +#define EN751221_GFAST_RST 31 +#define EN751221_CPU_TIMER2_RST 32 +#define EN751221_UART3_RST 33 +#define EN751221_UART4_RST 34 +#define EN751221_UART5_RST 35 +#define EN751221_I2C2_RST 36 +#define EN751221_XSI_MAC_RST 37 +#define EN751221_XSI_PHY_RST 38 +#define EN751221_DMT_RST 39 +#define EN751221_USB_PHY_P0_RST 40 +#define EN751221_USB_PHY_P1_RST 41 + +#endif /* __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_ */ -- cgit v1.2.3 From b822fb82505af4cc3f14fed05b8069c67d2ed5fb Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 24 Mar 2026 11:43:06 +0000 Subject: dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3L SoC Document the device tree bindings for the Renesas RZ/G3L SoC Clock Pulse Generator (CPG). RZ/G3L CPG is similar to RZ/G2L CPG but has 5 clocks compared to 1 clock on other SoCs. Also define RZ/G3L (R9A08G046) Clock Pulse Generator Core Clocks, as listed in section 4.4.4.1 ("Block Diagram of the Clock System"), module clock outputs, as listed in section 4.4.2 ("Clock List r1.00") and add Reset definitions referring to registers CPG_RST_* in Section 4.4.3 ("Register") of the RZ/G3L Hardware User's Manual (Rev.1.00 Oct, 2025). Acked-by: Conor Dooley Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260324114329.268249-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../bindings/clock/renesas,rzg2l-cpg.yaml | 40 ++- include/dt-bindings/clock/renesas,r9a08g046-cpg.h | 342 +++++++++++++++++++++ 2 files changed, 377 insertions(+), 5 deletions(-) create mode 100644 include/dt-bindings/clock/renesas,r9a08g046-cpg.h (limited to 'include') diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml index 8c18616e5c4d..c0ce687d83ee 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -28,19 +28,30 @@ properties: - renesas,r9a07g044-cpg # RZ/G2{L,LC} - renesas,r9a07g054-cpg # RZ/V2L - renesas,r9a08g045-cpg # RZ/G3S + - renesas,r9a08g046-cpg # RZ/G3L - renesas,r9a09g011-cpg # RZ/V2M reg: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + items: + - description: Clock source to CPG can be either from external clock + input (EXCLK) or crystal oscillator (XIN/XOUT). + - description: ETH0 TXC clock input + - description: ETH0 RXC clock input + - description: ETH1 TXC clock input + - description: ETH1 RXC clock input clock-names: - description: - Clock source to CPG can be either from external clock input (EXCLK) or - crystal oscillator (XIN/XOUT). - const: extal + minItems: 1 + items: + - const: extal + - const: eth0_txc_tx_clk + - const: eth0_rxc_rx_clk + - const: eth1_txc_tx_clk + - const: eth1_rxc_rx_clk '#clock-cells': description: | @@ -74,6 +85,25 @@ required: - '#power-domain-cells' - '#reset-cells' +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r9a08g046-cpg + then: + properties: + clocks: + minItems: 5 + clock-names: + minItems: 5 + else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + additionalProperties: false examples: diff --git a/include/dt-bindings/clock/renesas,r9a08g046-cpg.h b/include/dt-bindings/clock/renesas,r9a08g046-cpg.h new file mode 100644 index 000000000000..018b0a1e4340 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a08g046-cpg.h @@ -0,0 +1,342 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__ + +#include + +/* R9A08G046 CPG Core Clocks */ +#define R9A08G046_CLK_I 0 +#define R9A08G046_CLK_IC0 1 +#define R9A08G046_CLK_IC1 2 +#define R9A08G046_CLK_IC2 3 +#define R9A08G046_CLK_IC3 4 +#define R9A08G046_CLK_P0 5 +#define R9A08G046_CLK_P1 6 +#define R9A08G046_CLK_P2 7 +#define R9A08G046_CLK_P3 8 +#define R9A08G046_CLK_P4 9 +#define R9A08G046_CLK_P5 10 +#define R9A08G046_CLK_P6 11 +#define R9A08G046_CLK_P7 12 +#define R9A08G046_CLK_P8 13 +#define R9A08G046_CLK_P9 14 +#define R9A08G046_CLK_P10 15 +#define R9A08G046_CLK_P13 16 +#define R9A08G046_CLK_P14 17 +#define R9A08G046_CLK_P15 18 +#define R9A08G046_CLK_P16 19 +#define R9A08G046_CLK_P17 20 +#define R9A08G046_CLK_P18 21 +#define R9A08G046_CLK_P19 22 +#define R9A08G046_CLK_P20 23 +#define R9A08G046_CLK_M0 24 +#define R9A08G046_CLK_M1 25 +#define R9A08G046_CLK_M2 26 +#define R9A08G046_CLK_M3 27 +#define R9A08G046_CLK_M4 28 +#define R9A08G046_CLK_M5 29 +#define R9A08G046_CLK_M6 30 +#define R9A08G046_CLK_AT 31 +#define R9A08G046_CLK_B 32 +#define R9A08G046_CLK_ETHTX01 33 +#define R9A08G046_CLK_ETHTX02 34 +#define R9A08G046_CLK_ETHRX01 35 +#define R9A08G046_CLK_ETHRX02 36 +#define R9A08G046_CLK_ETHRM0 37 +#define R9A08G046_CLK_ETHTX11 38 +#define R9A08G046_CLK_ETHTX12 39 +#define R9A08G046_CLK_ETHRX11 40 +#define R9A08G046_CLK_ETHRX12 41 +#define R9A08G046_CLK_ETHRM1 42 +#define R9A08G046_CLK_G 43 +#define R9A08G046_CLK_HP 44 +#define R9A08G046_CLK_SD0 45 +#define R9A08G046_CLK_SD1 46 +#define R9A08G046_CLK_SD2 47 +#define R9A08G046_CLK_SPI0 48 +#define R9A08G046_CLK_SPI1 49 +#define R9A08G046_CLK_S0 50 +#define R9A08G046_CLK_SWD 51 +#define R9A08G046_OSCCLK 52 +#define R9A08G046_OSCCLK2 53 +#define R9A08G046_MIPI_DSI_PLLCLK 54 +#define R9A08G046_USB_SCLK 55 + +/* R9A08G046 Module Clocks */ +#define R9A08G046_CA55_SCLK 0 +#define R9A08G046_CA55_PCLK 1 +#define R9A08G046_CA55_ATCLK 2 +#define R9A08G046_CA55_GICCLK 3 +#define R9A08G046_CA55_PERICLK 4 +#define R9A08G046_CA55_ACLK 5 +#define R9A08G046_CA55_TSCLK 6 +#define R9A08G046_CA55_CORECLK0 7 +#define R9A08G046_CA55_CORECLK1 8 +#define R9A08G046_CA55_CORECLK2 9 +#define R9A08G046_CA55_CORECLK3 10 +#define R9A08G046_SRAM_ACPU_ACLK0 11 +#define R9A08G046_SRAM_ACPU_ACLK1 12 +#define R9A08G046_SRAM_ACPU_ACLK2 13 +#define R9A08G046_GIC600_GICCLK 14 +#define R9A08G046_IA55_CLK 15 +#define R9A08G046_IA55_PCLK 16 +#define R9A08G046_MHU_PCLK 17 +#define R9A08G046_SYC_CNT_CLK 18 +#define R9A08G046_DMAC_ACLK 19 +#define R9A08G046_DMAC_PCLK 20 +#define R9A08G046_OSTM0_PCLK 21 +#define R9A08G046_OSTM1_PCLK 22 +#define R9A08G046_OSTM2_PCLK 23 +#define R9A08G046_MTU_X_MCK_MTU3 24 +#define R9A08G046_POE3_CLKM_POE 25 +#define R9A08G046_GPT_PCLK 26 +#define R9A08G046_POEG_A_CLKP 27 +#define R9A08G046_POEG_B_CLKP 28 +#define R9A08G046_POEG_C_CLKP 29 +#define R9A08G046_POEG_D_CLKP 30 +#define R9A08G046_WDT0_PCLK 31 +#define R9A08G046_WDT0_CLK 32 +#define R9A08G046_WDT1_PCLK 33 +#define R9A08G046_WDT1_CLK 34 +#define R9A08G046_WDT2_PCLK 35 +#define R9A08G046_WDT2_CLK 36 +#define R9A08G046_XSPI_HCLK 37 +#define R9A08G046_XSPI_ACLK 38 +#define R9A08G046_XSPI_CLK 39 +#define R9A08G046_XSPI_CLKX2 40 +#define R9A08G046_SDHI0_IMCLK 41 +#define R9A08G046_SDHI0_IMCLK2 42 +#define R9A08G046_SDHI0_CLK_HS 43 +#define R9A08G046_SDHI0_IACLKS 44 +#define R9A08G046_SDHI0_IACLKM 45 +#define R9A08G046_SDHI1_IMCLK 46 +#define R9A08G046_SDHI1_IMCLK2 47 +#define R9A08G046_SDHI1_CLK_HS 48 +#define R9A08G046_SDHI1_IACLKS 49 +#define R9A08G046_SDHI1_IACLKM 50 +#define R9A08G046_SDHI2_IMCLK 51 +#define R9A08G046_SDHI2_IMCLK2 52 +#define R9A08G046_SDHI2_CLK_HS 53 +#define R9A08G046_SDHI2_IACLKS 54 +#define R9A08G046_SDHI2_IACLKM 55 +#define R9A08G046_GE3D_CLK 56 +#define R9A08G046_GE3D_AXI_CLK 57 +#define R9A08G046_GE3D_ACE_CLK 58 +#define R9A08G046_ISU_ACLK 59 +#define R9A08G046_ISU_PCLK 60 +#define R9A08G046_H264_CLK_A 61 +#define R9A08G046_H264_CLK_P 62 +#define R9A08G046_CRU_SYSCLK 63 +#define R9A08G046_CRU_VCLK 64 +#define R9A08G046_CRU_PCLK 65 +#define R9A08G046_CRU_ACLK 66 +#define R9A08G046_MIPI_DSI_SYSCLK 67 +#define R9A08G046_MIPI_DSI_ACLK 68 +#define R9A08G046_MIPI_DSI_PCLK 69 +#define R9A08G046_MIPI_DSI_VCLK 70 +#define R9A08G046_MIPI_DSI_LPCLK 71 +#define R9A08G046_LVDS_PLLCLK 72 +#define R9A08G046_LVDS_CLK_DOT0 73 +#define R9A08G046_LCDC_CLK_A 74 +#define R9A08G046_LCDC_CLK_D 75 +#define R9A08G046_LCDC_CLK_P 76 +#define R9A08G046_SSI0_PCLK2 77 +#define R9A08G046_SSI0_PCLK_SFR 78 +#define R9A08G046_SSI1_PCLK2 79 +#define R9A08G046_SSI1_PCLK_SFR 80 +#define R9A08G046_SSI2_PCLK2 81 +#define R9A08G046_SSI2_PCLK_SFR 82 +#define R9A08G046_SSI3_PCLK2 83 +#define R9A08G046_SSI3_PCLK_SFR 84 +#define R9A08G046_USB_U2H0_HCLK 85 +#define R9A08G046_USB_U2H1_HCLK 86 +#define R9A08G046_USB_U2P0_EXR_CPUCLK 87 +#define R9A08G046_USB_U2P1_EXR_CPUCLK 88 +#define R9A08G046_USB_PCLK 89 +#define R9A08G046_ETH0_CLK_AXI 90 +#define R9A08G046_ETH0_CLK_CHI 91 +#define R9A08G046_ETH0_CLK_TX_I 92 +#define R9A08G046_ETH0_CLK_RX_I 93 +#define R9A08G046_ETH0_CLK_TX_180_I 94 +#define R9A08G046_ETH0_CLK_RX_180_I 95 +#define R9A08G046_ETH0_CLK_RMII_I 96 +#define R9A08G046_ETH0_CLK_PTP_REF_I 97 +#define R9A08G046_ETH0_CLK_TX_I_RMII 98 +#define R9A08G046_ETH0_CLK_RX_I_RMII 99 +#define R9A08G046_ETH1_CLK_AXI 100 +#define R9A08G046_ETH1_CLK_CHI 101 +#define R9A08G046_ETH1_CLK_TX_I 102 +#define R9A08G046_ETH1_CLK_RX_I 103 +#define R9A08G046_ETH1_CLK_TX_180_I 104 +#define R9A08G046_ETH1_CLK_RX_180_I 105 +#define R9A08G046_ETH1_CLK_RMII_I 106 +#define R9A08G046_ETH1_CLK_PTP_REF_I 107 +#define R9A08G046_ETH1_CLK_TX_I_RMII 108 +#define R9A08G046_ETH1_CLK_RX_I_RMII 109 +#define R9A08G046_I2C0_PCLK 110 +#define R9A08G046_I2C1_PCLK 111 +#define R9A08G046_I2C2_PCLK 112 +#define R9A08G046_I2C3_PCLK 113 +#define R9A08G046_SCIF0_CLK_PCK 114 +#define R9A08G046_SCIF1_CLK_PCK 115 +#define R9A08G046_SCIF2_CLK_PCK 116 +#define R9A08G046_SCIF3_CLK_PCK 117 +#define R9A08G046_SCIF4_CLK_PCK 118 +#define R9A08G046_SCIF5_CLK_PCK 119 +#define R9A08G046_RSCI0_PCLK 120 +#define R9A08G046_RSCI0_TCLK 121 +#define R9A08G046_RSCI1_PCLK 122 +#define R9A08G046_RSCI1_TCLK 123 +#define R9A08G046_RSCI2_PCLK 124 +#define R9A08G046_RSCI2_TCLK 125 +#define R9A08G046_RSCI3_PCLK 126 +#define R9A08G046_RSCI3_TCLK 127 +#define R9A08G046_RSPI0_PCLK 128 +#define R9A08G046_RSPI0_TCLK 129 +#define R9A08G046_RSPI1_PCLK 130 +#define R9A08G046_RSPI1_TCLK 131 +#define R9A08G046_RSPI2_PCLK 132 +#define R9A08G046_RSPI2_TCLK 133 +#define R9A08G046_CANFD_PCLK 134 +#define R9A08G046_CANFD_CLK_RAM 135 +#define R9A08G046_GPIO_HCLK 136 +#define R9A08G046_ADC0_ADCLK 137 +#define R9A08G046_ADC0_PCLK 138 +#define R9A08G046_ADC1_ADCLK 139 +#define R9A08G046_ADC1_PCLK 140 +#define R9A08G046_TSU_PCLK 141 +#define R9A08G046_PDM_PCLK 142 +#define R9A08G046_PDM_CCLK 143 +#define R9A08G046_PCI_ACLK 144 +#define R9A08G046_PCI_CLKL1PM 145 +#define R9A08G046_PCI_CLK_PMU 146 +#define R9A08G046_SPDIF_PCLK 147 +#define R9A08G046_I3C_TCLK 148 +#define R9A08G046_I3C_PCLK 149 +#define R9A08G046_VBAT_BCLK 150 +#define R9A08G046_BSC_X_BCK_BSC 151 + +/* R9A08G046 Resets */ +#define R9A08G046_CA55_RST0_0 0 +#define R9A08G046_CA55_RST0_1 1 +#define R9A08G046_CA55_RST0_2 2 +#define R9A08G046_CA55_RST0_3 3 +#define R9A08G046_CA55_RST4_0 4 +#define R9A08G046_CA55_RST4_1 5 +#define R9A08G046_CA55_RST4_2 6 +#define R9A08G046_CA55_RST4_3 7 +#define R9A08G046_CA55_RST8 8 +#define R9A08G046_CA55_RST9 9 +#define R9A08G046_CA55_RST10 10 +#define R9A08G046_CA55_RST11 11 +#define R9A08G046_CA55_RST12 12 +#define R9A08G046_CA55_RST13 13 +#define R9A08G046_CA55_RST14 14 +#define R9A08G046_CA55_RST15 15 +#define R9A08G046_CA55_RST16 16 +#define R9A08G046_SRAM_ACPU_ARESETN0 17 +#define R9A08G046_SRAM_ACPU_ARESETN1 18 +#define R9A08G046_SRAM_ACPU_ARESETN2 19 +#define R9A08G046_GIC600_GICRESET_N 20 +#define R9A08G046_GIC600_DBG_GICRESET_N 21 +#define R9A08G046_IA55_RESETN 22 +#define R9A08G046_MHU_RESETN 23 +#define R9A08G046_SYC_RESETN 24 +#define R9A08G046_DMAC_ARESETN 25 +#define R9A08G046_DMAC_RST_ASYNC 26 +#define R9A08G046_GTM0_PRESETZ 27 +#define R9A08G046_GTM1_PRESETZ 28 +#define R9A08G046_GTM2_PRESETZ 29 +#define R9A08G046_MTU_X_PRESET_MTU3 30 +#define R9A08G046_POE3_RST_M_REG 31 +#define R9A08G046_GPT_RST_C 32 +#define R9A08G046_POEG_A_RST 33 +#define R9A08G046_POEG_B_RST 34 +#define R9A08G046_POEG_C_RST 35 +#define R9A08G046_POEG_D_RST 36 +#define R9A08G046_WDT0_PRESETN 37 +#define R9A08G046_WDT1_PRESETN 38 +#define R9A08G046_WDT2_PRESETN 39 +#define R9A08G046_XSPI_HRESETN 40 +#define R9A08G046_XSPI_ARESETN 41 +#define R9A08G046_SDHI0_IXRST 42 +#define R9A08G046_SDHI1_IXRST 43 +#define R9A08G046_SDHI2_IXRST 44 +#define R9A08G046_SDHI0_IXRSTAXIM 45 +#define R9A08G046_SDHI0_IXRSTAXIS 46 +#define R9A08G046_SDHI1_IXRSTAXIM 47 +#define R9A08G046_SDHI1_IXRSTAXIS 48 +#define R9A08G046_SDHI2_IXRSTAXIM 49 +#define R9A08G046_SDHI2_IXRSTAXIS 50 +#define R9A08G046_GE3D_RESETN 51 +#define R9A08G046_GE3D_AXI_RESETN 52 +#define R9A08G046_GE3D_ACE_RESETN 53 +#define R9A08G046_ISU_ARESETN 54 +#define R9A08G046_ISU_PRESETN 55 +#define R9A08G046_H264_X_RESET_VCP 56 +#define R9A08G046_H264_CP_PRESET_P 57 +#define R9A08G046_CRU_CMN_RSTB 58 +#define R9A08G046_CRU_PRESETN 59 +#define R9A08G046_CRU_ARESETN 60 +#define R9A08G046_MIPI_DSI_CMN_RSTB 61 +#define R9A08G046_MIPI_DSI_ARESET_N 62 +#define R9A08G046_MIPI_DSI_PRESET_N 63 +#define R9A08G046_LCDC_RESET_N 64 +#define R9A08G046_SSI0_RST_M2_REG 65 +#define R9A08G046_SSI1_RST_M2_REG 66 +#define R9A08G046_SSI2_RST_M2_REG 67 +#define R9A08G046_SSI3_RST_M2_REG 68 +#define R9A08G046_USB_U2H0_HRESETN 69 +#define R9A08G046_USB_U2H1_HRESETN 70 +#define R9A08G046_USB_U2P0_EXL_SYSRST 71 +#define R9A08G046_USB_PRESETN 72 +#define R9A08G046_USB_U2P1_EXL_SYSRST 73 +#define R9A08G046_ETH0_ARESET_N 74 +#define R9A08G046_ETH1_ARESET_N 75 +#define R9A08G046_I2C0_MRST 76 +#define R9A08G046_I2C1_MRST 77 +#define R9A08G046_I2C2_MRST 78 +#define R9A08G046_I2C3_MRST 79 +#define R9A08G046_SCIF0_RST_SYSTEM_N 80 +#define R9A08G046_SCIF1_RST_SYSTEM_N 81 +#define R9A08G046_SCIF2_RST_SYSTEM_N 82 +#define R9A08G046_SCIF3_RST_SYSTEM_N 83 +#define R9A08G046_SCIF4_RST_SYSTEM_N 84 +#define R9A08G046_SCIF5_RST_SYSTEM_N 85 +#define R9A08G046_RSPI0_PRESETN 86 +#define R9A08G046_RSPI1_PRESETN 87 +#define R9A08G046_RSPI2_PRESETN 88 +#define R9A08G046_RSPI0_TRESETN 89 +#define R9A08G046_RSPI1_TRESETN 90 +#define R9A08G046_RSPI2_TRESETN 91 +#define R9A08G046_CANFD_RSTP_N 92 +#define R9A08G046_CANFD_RSTC_N 93 +#define R9A08G046_GPIO_RSTN 94 +#define R9A08G046_GPIO_PORT_RESETN 95 +#define R9A08G046_GPIO_SPARE_RESETN 96 +#define R9A08G046_ADC0_PRESETN 97 +#define R9A08G046_ADC0_ADRST_N 98 +#define R9A08G046_ADC1_PRESETN 99 +#define R9A08G046_ADC1_ADRST_N 100 +#define R9A08G046_TSU_PRESETN 101 +#define R9A08G046_PDM_PRESETN 102 +#define R9A08G046_PCI_ARESETN 103 +#define R9A08G046_SPDIF_RST 104 +#define R9A08G046_I3C_TRESETN 105 +#define R9A08G046_I3C_PRESETN 106 +#define R9A08G046_VBAT_BRESETN 107 +#define R9A08G046_RSCI0_PRESETN 108 +#define R9A08G046_RSCI1_PRESETN 109 +#define R9A08G046_RSCI2_PRESETN 110 +#define R9A08G046_RSCI3_PRESETN 111 +#define R9A08G046_RSCI0_TRESETN 112 +#define R9A08G046_RSCI1_TRESETN 113 +#define R9A08G046_RSCI2_TRESETN 114 +#define R9A08G046_RSCI3_TRESETN 115 +#define R9A08G046_LVDS_RESET_N 116 +#define R9A08G046_BSC_X_PRESET_BSC 117 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__ */ -- cgit v1.2.3