From 2b7a02c322922a37cc5fc15d055b794cc2193062 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 19 Dec 2025 21:52:08 +0800 Subject: clk: spacemit: prepare common ccu header In order to prepare adding clock driver for new K3 SoC, extract generic code to a separate common ccu header file, so they are not defined in K1 SoC-specific file, and then can be shared by all clock drivers. Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-1-badf635993d3@gentoo.org Reviewed-by: Alex Elder Signed-off-by: Yixun Lan --- include/soc/spacemit/ccu.h | 21 +++++++++++++++++++++ include/soc/spacemit/k1-syscon.h | 12 +----------- 2 files changed, 22 insertions(+), 11 deletions(-) create mode 100644 include/soc/spacemit/ccu.h (limited to 'include') diff --git a/include/soc/spacemit/ccu.h b/include/soc/spacemit/ccu.h new file mode 100644 index 000000000000..84dcdecccc05 --- /dev/null +++ b/include/soc/spacemit/ccu.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_SPACEMIT_CCU_H__ +#define __SOC_SPACEMIT_CCU_H__ + +#include +#include + +/* Auxiliary device used to represent a CCU reset controller */ +struct spacemit_ccu_adev { + struct auxiliary_device adev; + struct regmap *regmap; +}; + +static inline struct spacemit_ccu_adev * +to_spacemit_ccu_adev(struct auxiliary_device *adev) +{ + return container_of(adev, struct spacemit_ccu_adev, adev); +} + +#endif /* __SOC_SPACEMIT_CCU_H__ */ diff --git a/include/soc/spacemit/k1-syscon.h b/include/soc/spacemit/k1-syscon.h index 354751562c55..0be7a2e8d445 100644 --- a/include/soc/spacemit/k1-syscon.h +++ b/include/soc/spacemit/k1-syscon.h @@ -5,17 +5,7 @@ #ifndef __SOC_K1_SYSCON_H__ #define __SOC_K1_SYSCON_H__ -/* Auxiliary device used to represent a CCU reset controller */ -struct spacemit_ccu_adev { - struct auxiliary_device adev; - struct regmap *regmap; -}; - -static inline struct spacemit_ccu_adev * -to_spacemit_ccu_adev(struct auxiliary_device *adev) -{ - return container_of(adev, struct spacemit_ccu_adev, adev); -} +#include "ccu.h" /* APBS register offset */ #define APBS_PLL1_SWCR1 0x100 -- cgit v1.2.3 From efe897b557e211a09f51d749eae5eca933e8bf56 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Sat, 1 Nov 2025 20:56:42 +0800 Subject: dt-bindings: soc: spacemit: k3: add clock support Add compatible strings for clock drivers to support Spacemit K3 SoC, also includes all the defined clock IDs. The SpacemiT K3 SoC clock IP is scattered over several different blocks, which are APBC, APBS, APMU, DCIU, MPMU, all of them are capable of generating clock and reset signals. APMU and MPMU have additional Power Domain management functionality. Following is a brief list that shows devices managed in each block: APBC: UART, GPIO, PWM, SPI, TIMER, I2S, IR, DR, TSEN, IPC, CAN APBS: various PPL clocks control APMU: CCI, CPU, CSI, ISP, LCD, USB, QSPI, DMA, VPU, GPU, DSI, PCIe, EMAC.. DCID: SRAM, DMA, TCM MPMU: various PLL1 derived clocks, UART, WATCHDOG, I2S Link: https://lore.kernel.org/r/20260108-k3-clk-v5-1-42a11b74ad58@gentoo.org Reviewed-by: Krzysztof Kozlowski Signed-off-by: Yixun Lan --- .../devicetree/bindings/clock/spacemit,k1-pll.yaml | 9 +- .../bindings/soc/spacemit/spacemit,k1-syscon.yaml | 14 +- include/dt-bindings/clock/spacemit,k3-clocks.h | 390 +++++++++++++++++++++ 3 files changed, 408 insertions(+), 5 deletions(-) create mode 100644 include/dt-bindings/clock/spacemit,k3-clocks.h (limited to 'include') diff --git a/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml b/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml index 06bafd68c00a..cddf6a56dac0 100644 --- a/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml +++ b/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml @@ -4,14 +4,16 @@ $id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: SpacemiT K1 PLL +title: SpacemiT K1/K3 PLL maintainers: - Haylen Chu properties: compatible: - const: spacemit,k1-pll + enum: + - spacemit,k1-pll + - spacemit,k3-pll reg: maxItems: 1 @@ -28,7 +30,8 @@ properties: "#clock-cells": const: 1 description: - See for valid indices. + For K1 SoC, check for valid indices. + For K3 SoC, check for valid indices. required: - compatible diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml index 133a391ee68c..d87131da30bc 100644 --- a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-syscon.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: SpacemiT K1 SoC System Controller +title: SpacemiT K1/K3 SoC System Controller maintainers: - Haylen Chu @@ -22,6 +22,10 @@ properties: - spacemit,k1-syscon-rcpu - spacemit,k1-syscon-rcpu2 - spacemit,k1-syscon-apbc2 + - spacemit,k3-syscon-apbc + - spacemit,k3-syscon-apmu + - spacemit,k3-syscon-dciu + - spacemit,k3-syscon-mpmu reg: maxItems: 1 @@ -39,7 +43,8 @@ properties: "#clock-cells": const: 1 description: - See for valid indices. + For K1 SoC, check for valid indices. + For K3 SoC, check for valid indices. "#power-domain-cells": const: 1 @@ -60,6 +65,8 @@ allOf: enum: - spacemit,k1-syscon-apmu - spacemit,k1-syscon-mpmu + - spacemit,k3-syscon-apmu + - spacemit,k3-syscon-mpmu then: required: - "#power-domain-cells" @@ -74,6 +81,9 @@ allOf: - spacemit,k1-syscon-apbc - spacemit,k1-syscon-apmu - spacemit,k1-syscon-mpmu + - spacemit,k3-syscon-apbc + - spacemit,k3-syscon-apmu + - spacemit,k3-syscon-mpmu then: required: - clocks diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bindings/clock/spacemit,k3-clocks.h new file mode 100644 index 000000000000..b22336f3ae40 --- /dev/null +++ b/include/dt-bindings/clock/spacemit,k3-clocks.h @@ -0,0 +1,390 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 SpacemiT Technology Co. Ltd + */ + +#ifndef _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ +#define _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ + +/* APBS (PLL) clocks */ +#define CLK_PLL1 0 +#define CLK_PLL2 1 +#define CLK_PLL3 2 +#define CLK_PLL4 3 +#define CLK_PLL5 4 +#define CLK_PLL6 5 +#define CLK_PLL7 6 +#define CLK_PLL8 7 +#define CLK_PLL1_D2 8 +#define CLK_PLL1_D3 9 +#define CLK_PLL1_D4 10 +#define CLK_PLL1_D5 11 +#define CLK_PLL1_D6 12 +#define CLK_PLL1_D7 13 +#define CLK_PLL1_D8 14 +#define CLK_PLL1_DX 15 +#define CLK_PLL1_D64 16 +#define CLK_PLL1_D10_AUD 17 +#define CLK_PLL1_D100_AUD 18 +#define CLK_PLL2_D1 19 +#define CLK_PLL2_D2 20 +#define CLK_PLL2_D3 21 +#define CLK_PLL2_D4 22 +#define CLK_PLL2_D5 23 +#define CLK_PLL2_D6 24 +#define CLK_PLL2_D7 25 +#define CLK_PLL2_D8 26 +#define CLK_PLL2_66 27 +#define CLK_PLL2_33 28 +#define CLK_PLL2_50 29 +#define CLK_PLL2_25 30 +#define CLK_PLL2_20 31 +#define CLK_PLL2_D24_125 32 +#define CLK_PLL2_D120_25 33 +#define CLK_PLL3_D1 34 +#define CLK_PLL3_D2 35 +#define CLK_PLL3_D3 36 +#define CLK_PLL3_D4 37 +#define CLK_PLL3_D5 38 +#define CLK_PLL3_D6 39 +#define CLK_PLL3_D7 40 +#define CLK_PLL3_D8 41 +#define CLK_PLL4_D1 42 +#define CLK_PLL4_D2 43 +#define CLK_PLL4_D3 44 +#define CLK_PLL4_D4 45 +#define CLK_PLL4_D5 46 +#define CLK_PLL4_D6 47 +#define CLK_PLL4_D7 48 +#define CLK_PLL4_D8 49 +#define CLK_PLL5_D1 50 +#define CLK_PLL5_D2 51 +#define CLK_PLL5_D3 52 +#define CLK_PLL5_D4 53 +#define CLK_PLL5_D5 54 +#define CLK_PLL5_D6 55 +#define CLK_PLL5_D7 56 +#define CLK_PLL5_D8 57 +#define CLK_PLL6_D1 58 +#define CLK_PLL6_D2 59 +#define CLK_PLL6_D3 60 +#define CLK_PLL6_D4 61 +#define CLK_PLL6_D5 62 +#define CLK_PLL6_D6 63 +#define CLK_PLL6_D7 64 +#define CLK_PLL6_D8 65 +#define CLK_PLL6_80 66 +#define CLK_PLL6_40 67 +#define CLK_PLL6_20 68 +#define CLK_PLL7_D1 69 +#define CLK_PLL7_D2 70 +#define CLK_PLL7_D3 71 +#define CLK_PLL7_D4 72 +#define CLK_PLL7_D5 73 +#define CLK_PLL7_D6 74 +#define CLK_PLL7_D7 75 +#define CLK_PLL7_D8 76 +#define CLK_PLL8_D1 77 +#define CLK_PLL8_D2 78 +#define CLK_PLL8_D3 79 +#define CLK_PLL8_D4 80 +#define CLK_PLL8_D5 81 +#define CLK_PLL8_D6 82 +#define CLK_PLL8_D7 83 +#define CLK_PLL8_D8 84 + +/* MPMU clocks */ +#define CLK_MPMU_PLL1_307P2 0 +#define CLK_MPMU_PLL1_76P8 1 +#define CLK_MPMU_PLL1_61P44 2 +#define CLK_MPMU_PLL1_153P6 3 +#define CLK_MPMU_PLL1_102P4 4 +#define CLK_MPMU_PLL1_51P2 5 +#define CLK_MPMU_PLL1_51P2_AP 6 +#define CLK_MPMU_PLL1_57P6 7 +#define CLK_MPMU_PLL1_25P6 8 +#define CLK_MPMU_PLL1_12P8 9 +#define CLK_MPMU_PLL1_12P8_WDT 10 +#define CLK_MPMU_PLL1_6P4 11 +#define CLK_MPMU_PLL1_3P2 12 +#define CLK_MPMU_PLL1_1P6 13 +#define CLK_MPMU_PLL1_0P8 14 +#define CLK_MPMU_PLL1_409P6 15 +#define CLK_MPMU_PLL1_204P8 16 +#define CLK_MPMU_PLL1_491 17 +#define CLK_MPMU_PLL1_245P76 18 +#define CLK_MPMU_PLL1_614 19 +#define CLK_MPMU_PLL1_47P26 20 +#define CLK_MPMU_PLL1_31P5 21 +#define CLK_MPMU_PLL1_819 22 +#define CLK_MPMU_PLL1_1228 23 +#define CLK_MPMU_APB 24 +#define CLK_MPMU_SLOW_UART 25 +#define CLK_MPMU_SLOW_UART1 26 +#define CLK_MPMU_SLOW_UART2 27 +#define CLK_MPMU_WDT 28 +#define CLK_MPMU_WDT_BUS 29 +#define CLK_MPMU_RIPC 30 +#define CLK_MPMU_I2S_153P6 31 +#define CLK_MPMU_I2S_153P6_BASE 32 +#define CLK_MPMU_I2S_SYSCLK_SRC 33 +#define CLK_MPMU_I2S1_SYSCLK 34 +#define CLK_MPMU_I2S_BCLK 35 +#define CLK_MPMU_I2S0_SYSCLK_SEL 36 +#define CLK_MPMU_I2S2_SYSCLK_SEL 37 +#define CLK_MPMU_I2S3_SYSCLK_SEL 38 +#define CLK_MPMU_I2S4_SYSCLK_SEL 39 +#define CLK_MPMU_I2S5_SYSCLK_SEL 40 +#define CLK_MPMU_I2S0_SYSCLK_DIV 41 +#define CLK_MPMU_I2S2_SYSCLK_DIV 42 +#define CLK_MPMU_I2S3_SYSCLK_DIV 43 +#define CLK_MPMU_I2S4_SYSCLK_DIV 44 +#define CLK_MPMU_I2S5_SYSCLK_DIV 45 +#define CLK_MPMU_I2S0_SYSCLK 46 +#define CLK_MPMU_I2S2_SYSCLK 47 +#define CLK_MPMU_I2S3_SYSCLK 48 +#define CLK_MPMU_I2S4_SYSCLK 49 +#define CLK_MPMU_I2S5_SYSCLK 50 + +/* APBC clocks */ +#define CLK_APBC_UART0 0 +#define CLK_APBC_UART2 1 +#define CLK_APBC_UART3 2 +#define CLK_APBC_UART4 3 +#define CLK_APBC_UART5 4 +#define CLK_APBC_UART6 5 +#define CLK_APBC_UART7 6 +#define CLK_APBC_UART8 7 +#define CLK_APBC_UART9 8 +#define CLK_APBC_UART10 9 +#define CLK_APBC_UART0_BUS 10 +#define CLK_APBC_UART2_BUS 11 +#define CLK_APBC_UART3_BUS 12 +#define CLK_APBC_UART4_BUS 13 +#define CLK_APBC_UART5_BUS 14 +#define CLK_APBC_UART6_BUS 15 +#define CLK_APBC_UART7_BUS 16 +#define CLK_APBC_UART8_BUS 17 +#define CLK_APBC_UART9_BUS 18 +#define CLK_APBC_UART10_BUS 19 +#define CLK_APBC_GPIO 20 +#define CLK_APBC_GPIO_BUS 21 +#define CLK_APBC_PWM0 22 +#define CLK_APBC_PWM1 23 +#define CLK_APBC_PWM2 24 +#define CLK_APBC_PWM3 25 +#define CLK_APBC_PWM4 26 +#define CLK_APBC_PWM5 27 +#define CLK_APBC_PWM6 28 +#define CLK_APBC_PWM7 29 +#define CLK_APBC_PWM8 30 +#define CLK_APBC_PWM9 31 +#define CLK_APBC_PWM10 32 +#define CLK_APBC_PWM11 33 +#define CLK_APBC_PWM12 34 +#define CLK_APBC_PWM13 35 +#define CLK_APBC_PWM14 36 +#define CLK_APBC_PWM15 37 +#define CLK_APBC_PWM16 38 +#define CLK_APBC_PWM17 39 +#define CLK_APBC_PWM18 40 +#define CLK_APBC_PWM19 41 +#define CLK_APBC_PWM0_BUS 42 +#define CLK_APBC_PWM1_BUS 43 +#define CLK_APBC_PWM2_BUS 44 +#define CLK_APBC_PWM3_BUS 45 +#define CLK_APBC_PWM4_BUS 46 +#define CLK_APBC_PWM5_BUS 47 +#define CLK_APBC_PWM6_BUS 48 +#define CLK_APBC_PWM7_BUS 49 +#define CLK_APBC_PWM8_BUS 50 +#define CLK_APBC_PWM9_BUS 51 +#define CLK_APBC_PWM10_BUS 52 +#define CLK_APBC_PWM11_BUS 53 +#define CLK_APBC_PWM12_BUS 54 +#define CLK_APBC_PWM13_BUS 55 +#define CLK_APBC_PWM14_BUS 56 +#define CLK_APBC_PWM15_BUS 57 +#define CLK_APBC_PWM16_BUS 58 +#define CLK_APBC_PWM17_BUS 59 +#define CLK_APBC_PWM18_BUS 60 +#define CLK_APBC_PWM19_BUS 61 +#define CLK_APBC_SPI0_I2S_BCLK 62 +#define CLK_APBC_SPI1_I2S_BCLK 63 +#define CLK_APBC_SPI3_I2S_BCLK 64 +#define CLK_APBC_SPI0 65 +#define CLK_APBC_SPI1 66 +#define CLK_APBC_SPI3 67 +#define CLK_APBC_SPI0_BUS 68 +#define CLK_APBC_SPI1_BUS 69 +#define CLK_APBC_SPI3_BUS 70 +#define CLK_APBC_RTC 71 +#define CLK_APBC_RTC_BUS 72 +#define CLK_APBC_TWSI0 73 +#define CLK_APBC_TWSI1 74 +#define CLK_APBC_TWSI2 75 +#define CLK_APBC_TWSI4 76 +#define CLK_APBC_TWSI5 77 +#define CLK_APBC_TWSI6 78 +#define CLK_APBC_TWSI8 79 +#define CLK_APBC_TWSI0_BUS 80 +#define CLK_APBC_TWSI1_BUS 81 +#define CLK_APBC_TWSI2_BUS 82 +#define CLK_APBC_TWSI4_BUS 83 +#define CLK_APBC_TWSI5_BUS 84 +#define CLK_APBC_TWSI6_BUS 85 +#define CLK_APBC_TWSI8_BUS 86 +#define CLK_APBC_TIMERS0 87 +#define CLK_APBC_TIMERS1 88 +#define CLK_APBC_TIMERS2 89 +#define CLK_APBC_TIMERS3 90 +#define CLK_APBC_TIMERS4 91 +#define CLK_APBC_TIMERS5 92 +#define CLK_APBC_TIMERS6 93 +#define CLK_APBC_TIMERS7 94 +#define CLK_APBC_TIMERS0_BUS 95 +#define CLK_APBC_TIMERS1_BUS 96 +#define CLK_APBC_TIMERS2_BUS 97 +#define CLK_APBC_TIMERS3_BUS 98 +#define CLK_APBC_TIMERS4_BUS 99 +#define CLK_APBC_TIMERS5_BUS 100 +#define CLK_APBC_TIMERS6_BUS 101 +#define CLK_APBC_TIMERS7_BUS 102 +#define CLK_APBC_AIB 103 +#define CLK_APBC_AIB_BUS 104 +#define CLK_APBC_ONEWIRE 105 +#define CLK_APBC_ONEWIRE_BUS 106 +#define CLK_APBC_I2S0_BCLK 107 +#define CLK_APBC_I2S1_BCLK 108 +#define CLK_APBC_I2S2_BCLK 109 +#define CLK_APBC_I2S3_BCLK 110 +#define CLK_APBC_I2S4_BCLK 111 +#define CLK_APBC_I2S5_BCLK 112 +#define CLK_APBC_I2S0 113 +#define CLK_APBC_I2S1 114 +#define CLK_APBC_I2S2 115 +#define CLK_APBC_I2S3 116 +#define CLK_APBC_I2S4 117 +#define CLK_APBC_I2S5 118 +#define CLK_APBC_I2S0_BUS 119 +#define CLK_APBC_I2S1_BUS 120 +#define CLK_APBC_I2S2_BUS 121 +#define CLK_APBC_I2S3_BUS 122 +#define CLK_APBC_I2S4_BUS 123 +#define CLK_APBC_I2S5_BUS 124 +#define CLK_APBC_DRO 125 +#define CLK_APBC_IR0 126 +#define CLK_APBC_IR1 127 +#define CLK_APBC_TSEN 128 +#define CLK_APBC_TSEN_BUS 129 +#define CLK_APBC_IPC_AP2RCPU 130 +#define CLK_APBC_IPC_AP2RCPU_BUS 131 +#define CLK_APBC_CAN0 132 +#define CLK_APBC_CAN1 133 +#define CLK_APBC_CAN2 134 +#define CLK_APBC_CAN3 135 +#define CLK_APBC_CAN4 136 +#define CLK_APBC_CAN0_BUS 137 +#define CLK_APBC_CAN1_BUS 138 +#define CLK_APBC_CAN2_BUS 139 +#define CLK_APBC_CAN3_BUS 140 +#define CLK_APBC_CAN4_BUS 141 + +/* APMU clocks */ +#define CLK_APMU_AXICLK 0 +#define CLK_APMU_CCI550 1 +#define CLK_APMU_CPU_C0_CORE 2 +#define CLK_APMU_CPU_C1_CORE 3 +#define CLK_APMU_CPU_C2_CORE 4 +#define CLK_APMU_CPU_C3_CORE 5 +#define CLK_APMU_CCIC2PHY 6 +#define CLK_APMU_CCIC3PHY 7 +#define CLK_APMU_CSI 8 +#define CLK_APMU_ISP_BUS 9 +#define CLK_APMU_D1P_1228P8 10 +#define CLK_APMU_D1P_819P2 11 +#define CLK_APMU_D1P_614P4 12 +#define CLK_APMU_D1P_491P52 13 +#define CLK_APMU_D1P_409P6 14 +#define CLK_APMU_D1P_307P2 15 +#define CLK_APMU_D1P_245P76 16 +#define CLK_APMU_V2D 17 +#define CLK_APMU_DSI_ESC 18 +#define CLK_APMU_LCD_HCLK 19 +#define CLK_APMU_LCD_DSC 20 +#define CLK_APMU_LCD_PXCLK 21 +#define CLK_APMU_LCD_MCLK 22 +#define CLK_APMU_CCIC_4X 23 +#define CLK_APMU_CCIC1PHY 24 +#define CLK_APMU_SC2_HCLK 25 +#define CLK_APMU_SDH_AXI 26 +#define CLK_APMU_SDH0 27 +#define CLK_APMU_SDH1 28 +#define CLK_APMU_SDH2 29 +#define CLK_APMU_USB2_BUS 30 +#define CLK_APMU_USB3_PORTA_BUS 31 +#define CLK_APMU_USB3_PORTB_BUS 32 +#define CLK_APMU_USB3_PORTC_BUS 33 +#define CLK_APMU_USB3_PORTD_BUS 34 +#define CLK_APMU_QSPI 35 +#define CLK_APMU_QSPI_BUS 36 +#define CLK_APMU_DMA 37 +#define CLK_APMU_AES_WTM 38 +#define CLK_APMU_VPU 39 +#define CLK_APMU_DTC 40 +#define CLK_APMU_GPU 41 +#define CLK_APMU_MC_AHB 42 +#define CLK_APMU_TOP_DCLK 43 +#define CLK_APMU_UCIE 44 +#define CLK_APMU_UCIE_SBCLK 45 +#define CLK_APMU_RCPU 46 +#define CLK_APMU_DSI4LN2_DSI_ESC 47 +#define CLK_APMU_DSI4LN2_LCD_DSC 48 +#define CLK_APMU_DSI4LN2_LCD_PXCLK 49 +#define CLK_APMU_DSI4LN2_LCD_MCLK 50 +#define CLK_APMU_DSI4LN2_DPU_ACLK 51 +#define CLK_APMU_DPU_ACLK 52 +#define CLK_APMU_UFS_ACLK 53 +#define CLK_APMU_EDP0_PXCLK 54 +#define CLK_APMU_EDP1_PXCLK 55 +#define CLK_APMU_PCIE_PORTA_MSTE 56 +#define CLK_APMU_PCIE_PORTA_SLV 57 +#define CLK_APMU_PCIE_PORTB_MSTE 58 +#define CLK_APMU_PCIE_PORTB_SLV 59 +#define CLK_APMU_PCIE_PORTC_MSTE 60 +#define CLK_APMU_PCIE_PORTC_SLV 61 +#define CLK_APMU_PCIE_PORTD_MSTE 62 +#define CLK_APMU_PCIE_PORTD_SLV 63 +#define CLK_APMU_PCIE_PORTE_MSTE 64 +#define CLK_APMU_PCIE_PORTE_SLV 65 +#define CLK_APMU_EMAC0_BUS 66 +#define CLK_APMU_EMAC0_REF 67 +#define CLK_APMU_EMAC0_1588 68 +#define CLK_APMU_EMAC0_RGMII_TX 69 +#define CLK_APMU_EMAC1_BUS 70 +#define CLK_APMU_EMAC1_REF 71 +#define CLK_APMU_EMAC1_1588 72 +#define CLK_APMU_EMAC1_RGMII_TX 73 +#define CLK_APMU_EMAC2_BUS 74 +#define CLK_APMU_EMAC2_REF 75 +#define CLK_APMU_EMAC2_1588 76 +#define CLK_APMU_EMAC2_RGMII_TX 77 +#define CLK_APMU_ESPI_SCLK_SRC 78 +#define CLK_APMU_ESPI_SCLK 79 +#define CLK_APMU_ESPI_MCLK 80 +#define CLK_APMU_CAM_SRC1 81 +#define CLK_APMU_CAM_SRC2 82 +#define CLK_APMU_CAM_SRC3 83 +#define CLK_APMU_CAM_SRC4 84 +#define CLK_APMU_ISIM_VCLK0 85 +#define CLK_APMU_ISIM_VCLK1 86 +#define CLK_APMU_ISIM_VCLK2 87 +#define CLK_APMU_ISIM_VCLK3 88 + +/* DCIU clocks */ +#define CLK_DCIU_HDMA 0 +#define CLK_DCIU_DMA350 1 +#define CLK_DCIU_C2_TCM_PIPE 2 +#define CLK_DCIU_C3_TCM_PIPE 3 + +#endif /* _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ */ -- cgit v1.2.3 From 091d19cc24018f2bd783e932fb2403cb7a2bdb3c Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Sat, 20 Dec 2025 21:28:15 +0800 Subject: clk: spacemit: k3: extract common header Extracting common header file, which will be shared by clock and reset drivers. So will make it easy to add reset driver for K3 SoC later. Link: https://lore.kernel.org/r/20260108-k3-clk-v5-4-42a11b74ad58@gentoo.org Signed-off-by: Yixun Lan --- include/soc/spacemit/k3-syscon.h | 273 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 273 insertions(+) create mode 100644 include/soc/spacemit/k3-syscon.h (limited to 'include') diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h new file mode 100644 index 000000000000..0299bea065a0 --- /dev/null +++ b/include/soc/spacemit/k3-syscon.h @@ -0,0 +1,273 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* SpacemiT clock and reset driver definitions for the K3 SoC */ + +#ifndef __SOC_K3_SYSCON_H__ +#define __SOC_K3_SYSCON_H__ + +#include "ccu.h" + +/* APBS register offset */ +#define APBS_PLL1_SWCR1 0x100 +#define APBS_PLL1_SWCR2 0x104 +#define APBS_PLL1_SWCR3 0x108 +#define APBS_PLL2_SWCR1 0x118 +#define APBS_PLL2_SWCR2 0x11c +#define APBS_PLL2_SWCR3 0x120 +#define APBS_PLL3_SWCR1 0x124 +#define APBS_PLL3_SWCR2 0x128 +#define APBS_PLL3_SWCR3 0x12c +#define APBS_PLL4_SWCR1 0x130 +#define APBS_PLL4_SWCR2 0x134 +#define APBS_PLL4_SWCR3 0x138 +#define APBS_PLL5_SWCR1 0x13c +#define APBS_PLL5_SWCR2 0x140 +#define APBS_PLL5_SWCR3 0x144 +#define APBS_PLL6_SWCR1 0x148 +#define APBS_PLL6_SWCR2 0x14c +#define APBS_PLL6_SWCR3 0x150 +#define APBS_PLL7_SWCR1 0x158 +#define APBS_PLL7_SWCR2 0x15c +#define APBS_PLL7_SWCR3 0x160 +#define APBS_PLL8_SWCR1 0x180 +#define APBS_PLL8_SWCR2 0x184 +#define APBS_PLL8_SWCR3 0x188 + +/* MPMU register offset */ +#define MPMU_FCCR 0x0008 +#define MPMU_POSR 0x0010 +#define POSR_PLL1_LOCK BIT(24) +#define POSR_PLL2_LOCK BIT(25) +#define POSR_PLL3_LOCK BIT(26) +#define POSR_PLL4_LOCK BIT(27) +#define POSR_PLL5_LOCK BIT(28) +#define POSR_PLL6_LOCK BIT(29) +#define POSR_PLL7_LOCK BIT(30) +#define POSR_PLL8_LOCK BIT(31) +#define MPMU_SUCCR 0x0014 +#define MPMU_ISCCR 0x0044 +#define MPMU_WDTPCR 0x0200 +#define MPMU_RIPCCR 0x0210 +#define MPMU_ACGR 0x1024 +#define MPMU_APBCSCR 0x1050 +#define MPMU_SUCCR_1 0x10b0 + +#define MPMU_I2S0_SYSCLK 0x1100 +#define MPMU_I2S2_SYSCLK 0x1104 +#define MPMU_I2S3_SYSCLK 0x1108 +#define MPMU_I2S4_SYSCLK 0x110c +#define MPMU_I2S5_SYSCLK 0x1110 +#define MPMU_I2S_SYSCLK_CTRL 0x1114 + +/* APBC register offset */ +#define APBC_UART0_CLK_RST 0x00 +#define APBC_UART2_CLK_RST 0x04 +#define APBC_GPIO_CLK_RST 0x08 +#define APBC_PWM0_CLK_RST 0x0c +#define APBC_PWM1_CLK_RST 0x10 +#define APBC_PWM2_CLK_RST 0x14 +#define APBC_PWM3_CLK_RST 0x18 +#define APBC_TWSI8_CLK_RST 0x20 +#define APBC_UART3_CLK_RST 0x24 +#define APBC_RTC_CLK_RST 0x28 +#define APBC_TWSI0_CLK_RST 0x2c +#define APBC_TWSI1_CLK_RST 0x30 +#define APBC_TIMERS0_CLK_RST 0x34 +#define APBC_TWSI2_CLK_RST 0x38 +#define APBC_AIB_CLK_RST 0x3c +#define APBC_TWSI4_CLK_RST 0x40 +#define APBC_TIMERS1_CLK_RST 0x44 +#define APBC_ONEWIRE_CLK_RST 0x48 +#define APBC_TWSI5_CLK_RST 0x4c +#define APBC_DRO_CLK_RST 0x58 +#define APBC_IR0_CLK_RST 0x5c +#define APBC_IR1_CLK_RST 0x1c +#define APBC_TWSI6_CLK_RST 0x60 +#define APBC_COUNTER_CLK_SEL 0x64 +#define APBC_TSEN_CLK_RST 0x6c +#define APBC_UART4_CLK_RST 0x70 +#define APBC_UART5_CLK_RST 0x74 +#define APBC_UART6_CLK_RST 0x78 +#define APBC_SSP3_CLK_RST 0x7c +#define APBC_SSPA0_CLK_RST 0x80 +#define APBC_SSPA1_CLK_RST 0x84 +#define APBC_SSPA2_CLK_RST 0x88 +#define APBC_SSPA3_CLK_RST 0x8c +#define APBC_IPC_AP2AUD_CLK_RST 0x90 +#define APBC_UART7_CLK_RST 0x94 +#define APBC_UART8_CLK_RST 0x98 +#define APBC_UART9_CLK_RST 0x9c +#define APBC_CAN0_CLK_RST 0xa0 +#define APBC_CAN1_CLK_RST 0xa4 +#define APBC_PWM4_CLK_RST 0xa8 +#define APBC_PWM5_CLK_RST 0xac +#define APBC_PWM6_CLK_RST 0xb0 +#define APBC_PWM7_CLK_RST 0xb4 +#define APBC_PWM8_CLK_RST 0xb8 +#define APBC_PWM9_CLK_RST 0xbc +#define APBC_PWM10_CLK_RST 0xc0 +#define APBC_PWM11_CLK_RST 0xc4 +#define APBC_PWM12_CLK_RST 0xc8 +#define APBC_PWM13_CLK_RST 0xcc +#define APBC_PWM14_CLK_RST 0xd0 +#define APBC_PWM15_CLK_RST 0xd4 +#define APBC_PWM16_CLK_RST 0xd8 +#define APBC_PWM17_CLK_RST 0xdc +#define APBC_PWM18_CLK_RST 0xe0 +#define APBC_PWM19_CLK_RST 0xe4 +#define APBC_TIMERS2_CLK_RST 0x11c +#define APBC_TIMERS3_CLK_RST 0x120 +#define APBC_TIMERS4_CLK_RST 0x124 +#define APBC_TIMERS5_CLK_RST 0x128 +#define APBC_TIMERS6_CLK_RST 0x12c +#define APBC_TIMERS7_CLK_RST 0x130 + +#define APBC_CAN2_CLK_RST 0x148 +#define APBC_CAN3_CLK_RST 0x14c +#define APBC_CAN4_CLK_RST 0x150 +#define APBC_UART10_CLK_RST 0x154 +#define APBC_SSP0_CLK_RST 0x158 +#define APBC_SSP1_CLK_RST 0x15c +#define APBC_SSPA4_CLK_RST 0x160 +#define APBC_SSPA5_CLK_RST 0x164 + +/* APMU register offset */ +#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024 +#define APMU_ISP_CLK_RES_CTRL 0x038 +#define APMU_PMU_CLK_GATE_CTRL 0x040 +#define APMU_LCD_CLK_RES_CTRL1 0x044 +#define APMU_LCD_SPI_CLK_RES_CTRL 0x048 +#define APMU_LCD_CLK_RES_CTRL2 0x04c +#define APMU_CCIC_CLK_RES_CTRL 0x050 +#define APMU_SDH0_CLK_RES_CTRL 0x054 +#define APMU_SDH1_CLK_RES_CTRL 0x058 +#define APMU_USB_CLK_RES_CTRL 0x05c +#define APMU_QSPI_CLK_RES_CTRL 0x060 +#define APMU_DMA_CLK_RES_CTRL 0x064 +#define APMU_AES_CLK_RES_CTRL 0x068 +#define APMU_MCB_CLK_RES_CTRL 0x06c +#define APMU_VPU_CLK_RES_CTRL 0x0a4 +#define APMU_DTC_CLK_RES_CTRL 0x0ac +#define APMU_GPU_CLK_RES_CTRL 0x0cc +#define APMU_SDH2_CLK_RES_CTRL 0x0e0 +#define APMU_PMUA_MC_CTRL 0x0e8 +#define APMU_PMU_CC2_AP 0x100 +#define APMU_PMUA_EM_CLK_RES_CTRL 0x104 +#define APMU_UCIE_CTRL 0x11c +#define APMU_RCPU_CLK_RES_CTRL 0x14c +#define APMU_TOP_DCLK_CTRL 0x158 +#define APMU_LCD_EDP_CTRL 0x23c +#define APMU_UFS_CLK_RES_CTRL 0x268 +#define APMU_LCD_CLK_RES_CTRL3 0x26c +#define APMU_LCD_CLK_RES_CTRL4 0x270 +#define APMU_LCD_CLK_RES_CTRL5 0x274 +#define APMU_CCI550_CLK_CTRL 0x300 +#define APMU_ACLK_CLK_CTRL 0x388 +#define APMU_CPU_C0_CLK_CTRL 0x38C +#define APMU_CPU_C1_CLK_CTRL 0x390 +#define APMU_CPU_C2_CLK_CTRL 0x394 +#define APMU_CPU_C3_CLK_CTRL 0x208 +#define APMU_PCIE_CLK_RES_CTRL_A 0x1f0 +#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8 +#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0 +#define APMU_PCIE_CLK_RES_CTRL_D 0x1e0 +#define APMU_PCIE_CLK_RES_CTRL_E 0x1e8 +#define APMU_EMAC0_CLK_RES_CTRL 0x3e4 +#define APMU_EMAC1_CLK_RES_CTRL 0x3ec +#define APMU_EMAC2_CLK_RES_CTRL 0x248 +#define APMU_ESPI_CLK_RES_CTRL 0x240 +#define APMU_SNR_ISIM_VCLK_CTRL 0x3f8 + +/* DCIU register offsets */ +#define DCIU_DMASYS_CLK_EN 0x234 +#define DCIU_DMASYS_SDMA_CLK_EN 0x238 +#define DCIU_C2_TCM_PIPE_CLK 0x244 +#define DCIU_C3_TCM_PIPE_CLK 0x248 + +#define DCIU_DMASYS_S0_RSTN 0x204 +#define DCIU_DMASYS_S1_RSTN 0x208 +#define DCIU_DMASYS_A0_RSTN 0x20C +#define DCIU_DMASYS_A1_RSTN 0x210 +#define DCIU_DMASYS_A2_RSTN 0x214 +#define DCIU_DMASYS_A3_RSTN 0x218 +#define DCIU_DMASYS_A4_RSTN 0x21C +#define DCIU_DMASYS_A5_RSTN 0x220 +#define DCIU_DMASYS_A6_RSTN 0x224 +#define DCIU_DMASYS_A7_RSTN 0x228 +#define DCIU_DMASYS_RSTN 0x22C +#define DCIU_DMASYS_SDMA_RSTN 0x230 + +/* RCPU SYSCTRL register offsets */ +#define RCPU_CAN_CLK_RST 0x4c +#define RCPU_CAN1_CLK_RST 0xF0 +#define RCPU_CAN2_CLK_RST 0xF4 +#define RCPU_CAN3_CLK_RST 0xF8 +#define RCPU_CAN4_CLK_RST 0xFC +#define RCPU_IRC_CLK_RST 0x48 +#define RCPU_IRC1_CLK_RST 0xEC +#define RCPU_GMAC_CLK_RST 0xE4 +#define RCPU_ESPI_CLK_RST 0xDC +#define RCPU_AUDIO_I2S0_SYS_CLK_CTRL 0x70 +#define RCPU_AUDIO_I2S1_SYS_CLK_CTRL 0x44 + +/* RCPU UARTCTRL register offsets */ +#define RCPU1_UART0_CLK_RST 0x00 +#define RCPU1_UART1_CLK_RST 0x04 +#define RCPU1_UART2_CLK_RST 0x08 +#define RCPU1_UART3_CLK_RST 0x0c +#define RCPU1_UART4_CLK_RST 0x10 +#define RCPU1_UART5_CLK_RST 0x14 + +/* RCPU I2SCTRL register offsets */ +#define RCPU2_AUDIO_I2S0_TX_RX_CLK_CTRL 0x60 +#define RCPU2_AUDIO_I2S1_TX_RX_CLK_CTRL 0x64 +#define RCPU2_AUDIO_I2S2_TX_RX_CLK_CTRL 0x68 +#define RCPU2_AUDIO_I2S3_TX_RX_CLK_CTRL 0x6C + +#define RCPU2_AUDIO_I2S2_SYS_CLK_CTRL 0x44 +#define RCPU2_AUDIO_I2S3_SYS_CLK_CTRL 0x54 + +/* RCPU SPICTRL register offsets */ +#define RCPU3_SSP0_CLK_RST 0x00 +#define RCPU3_SSP1_CLK_RST 0x04 +#define RCPU3_PWR_SSP_CLK_RST 0x08 + +/* RCPU I2CCTRL register offsets */ +#define RCPU4_I2C0_CLK_RST 0x00 +#define RCPU4_I2C1_CLK_RST 0x04 +#define RCPU4_PWR_I2C_CLK_RST 0x08 + +/* RPMU register offsets */ +#define RCPU5_AON_PER_CLK_RST_CTRL 0x2C +#define RCPU5_TIMER1_CLK_RST 0x4C +#define RCPU5_TIMER2_CLK_RST 0x70 +#define RCPU5_TIMER3_CLK_RST 0x78 +#define RCPU5_TIMER4_CLK_RST 0x7C +#define RCPU5_GPIO_AND_EDGE_CLK_RST 0x74 +#define RCPU5_RCPU_BUS_CLK_CTRL 0xC0 +#define RCPU5_RT24_CORE0_CLK_CTRL 0xC4 +#define RCPU5_RT24_CORE1_CLK_CTRL 0xC8 +#define RCPU5_RT24_CORE0_SW_RESET 0xCC +#define RCPU5_RT24_CORE1_SW_RESET 0xD0 + +/* RCPU PWMCTRL register offsets */ +#define RCPU6_PWM0_CLK_RST 0x00 +#define RCPU6_PWM1_CLK_RST 0x04 +#define RCPU6_PWM2_CLK_RST 0x08 +#define RCPU6_PWM3_CLK_RST 0x0c +#define RCPU6_PWM4_CLK_RST 0x10 +#define RCPU6_PWM5_CLK_RST 0x14 +#define RCPU6_PWM6_CLK_RST 0x18 +#define RCPU6_PWM7_CLK_RST 0x1c +#define RCPU6_PWM8_CLK_RST 0x20 +#define RCPU6_PWM9_CLK_RST 0x24 + +/* APBC2 SEC register offsets */ +#define APBC2_UART1_CLK_RST 0x00 +#define APBC2_SSP2_CLK_RST 0x04 +#define APBC2_TWSI3_CLK_RST 0x08 +#define APBC2_RTC_CLK_RST 0x0c +#define APBC2_TIMERS_CLK_RST 0x10 +#define APBC2_GPIO_CLK_RST 0x1c + +#endif /* __SOC_K3_SYSCON_H__ */ -- cgit v1.2.3