From 92af77ca26f75f7874634c8ac2f744f86ec56e88 Mon Sep 17 00:00:00 2001 From: Ilpo Järvinen Date: Tue, 24 Oct 2023 14:03:36 +0300 Subject: PCI: dwc: Use FIELD_GET/PREP() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Convert open-coded variants of PCI field access into FIELD_GET/PREP() to make the code easier to understand. Add two missing defines into pci_regs.h. Logically, the Max No-Snoop Latency Register is a separate word sized register in the PCIe spec, but the pre-existing LTR defines in pci_regs.h with dword long values seem to consider the registers together (the same goes for the only user). Thus, follow the custom and make the new values also take both word long LTR registers as a joint dword register. Link: https://lore.kernel.org/r/20231024110336.26264-1-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen Signed-off-by: Bjorn Helgaas --- include/uapi/linux/pci_regs.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index e5f558d96493..495f0ae4ecd5 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -975,6 +975,8 @@ #define PCI_LTR_VALUE_MASK 0x000003ff #define PCI_LTR_SCALE_MASK 0x00001c00 #define PCI_LTR_SCALE_SHIFT 10 +#define PCI_LTR_NOSNOOP_VALUE 0x03ff0000 /* Max No-Snoop Latency Value */ +#define PCI_LTR_NOSNOOP_SCALE 0x1c000000 /* Scale for Max Value */ #define PCI_EXT_CAP_LTR_SIZEOF 8 /* Access Control Service */ -- cgit v1.2.3 From 9a9eec4765737b9b2a8d6ae03de6480a5f12dd5c Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Wed, 18 Oct 2023 14:32:51 +0300 Subject: PCI/DPC: Use FIELD_GET() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use FIELD_GET() to remove dependencies on the field position, i.e., the shift value. No functional change intended. Link: https://lore.kernel.org/r/20231018113254.17616-5-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen Signed-off-by: Bjorn Helgaas --- drivers/pci/pcie/dpc.c | 5 +++-- drivers/pci/quirks.c | 2 +- include/uapi/linux/pci_regs.h | 1 + 3 files changed, 5 insertions(+), 3 deletions(-) (limited to 'include/uapi/linux') diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c index 3ceed8e3de41..a5c259ada9ea 100644 --- a/drivers/pci/pcie/dpc.c +++ b/drivers/pci/pcie/dpc.c @@ -9,6 +9,7 @@ #define dev_fmt(fmt) "DPC: " fmt #include +#include #include #include #include @@ -202,7 +203,7 @@ static void dpc_process_rp_pio_error(struct pci_dev *pdev) /* Get First Error Pointer */ pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status); - first_error = (dpc_status & 0x1f00) >> 8; + first_error = FIELD_GET(PCI_EXP_DPC_RP_PIO_FEP, dpc_status); for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) { if ((status & ~mask) & (1 << i)) @@ -338,7 +339,7 @@ void pci_dpc_init(struct pci_dev *pdev) /* Quirks may set dpc_rp_log_size if device or firmware is buggy */ if (!pdev->dpc_rp_log_size) { pdev->dpc_rp_log_size = - (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8; + FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, cap); if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) { pci_err(pdev, "RP PIO log size %u is invalid\n", pdev->dpc_rp_log_size); diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index eeec1d6f9023..a9fdc2e3f110 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -6154,7 +6154,7 @@ static void dpc_log_size(struct pci_dev *dev) if (!(val & PCI_EXP_DPC_CAP_RP_EXT)) return; - if (!((val & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8)) { + if (FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, val) == 0) { pci_info(dev, "Overriding RP PIO Log Size to 4\n"); dev->dpc_rp_log_size = 4; } diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 495f0ae4ecd5..6c1bad2cb04a 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1047,6 +1047,7 @@ #define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008 /* Interrupt Status */ #define PCI_EXP_DPC_RP_BUSY 0x0010 /* Root Port Busy */ #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */ +#define PCI_EXP_DPC_RP_PIO_FEP 0x1f00 /* RP PIO First Err Ptr */ #define PCI_EXP_DPC_SOURCE_ID 0x0A /* DPC Source Identifier */ -- cgit v1.2.3 From 74f0b5ffe172f913c56e4f5291678bad2a55b6b1 Mon Sep 17 00:00:00 2001 From: Ilpo Järvinen Date: Wed, 18 Oct 2023 14:32:53 +0300 Subject: PCI/DPC: Use defines with DPC reason fields MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add new defines for DPC reason fields and use them instead of literals. Link: https://lore.kernel.org/r/20231018113254.17616-7-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen [bhelgaas: shorten comments] Signed-off-by: Bjorn Helgaas --- drivers/pci/pcie/dpc.c | 27 +++++++++++++++++---------- include/uapi/linux/pci_regs.h | 6 ++++++ 2 files changed, 23 insertions(+), 10 deletions(-) (limited to 'include/uapi/linux') diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c index 0048a11bd119..94111e438241 100644 --- a/drivers/pci/pcie/dpc.c +++ b/drivers/pci/pcie/dpc.c @@ -274,20 +274,27 @@ void dpc_process_error(struct pci_dev *pdev) pci_info(pdev, "containment event, status:%#06x source:%#06x\n", status, source); - reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1; - ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5; + reason = status & PCI_EXP_DPC_STATUS_TRIGGER_RSN; + ext_reason = status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT; pci_warn(pdev, "%s detected\n", - (reason == 0) ? "unmasked uncorrectable error" : - (reason == 1) ? "ERR_NONFATAL" : - (reason == 2) ? "ERR_FATAL" : - (ext_reason == 0) ? "RP PIO error" : - (ext_reason == 1) ? "software trigger" : - "reserved error"); + (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR) ? + "unmasked uncorrectable error" : + (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_NFE) ? + "ERR_NONFATAL" : + (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_FE) ? + "ERR_FATAL" : + (ext_reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO) ? + "RP PIO error" : + (ext_reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_SW_TRIGGER) ? + "software trigger" : + "reserved error"); /* show RP PIO error detail information */ - if (pdev->dpc_rp_extensions && reason == 3 && ext_reason == 0) + if (pdev->dpc_rp_extensions && + reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_IN_EXT && + ext_reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO) dpc_process_rp_pio_error(pdev); - else if (reason == 0 && + else if (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR && dpc_get_aer_uncorrect_severity(pdev, &info) && aer_get_device_error_info(pdev, &info)) { aer_print_error(pdev, &info); diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 6c1bad2cb04a..0fd621505246 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1044,9 +1044,15 @@ #define PCI_EXP_DPC_STATUS 0x08 /* DPC Status */ #define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */ #define PCI_EXP_DPC_STATUS_TRIGGER_RSN 0x0006 /* Trigger Reason */ +#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR 0x0000 /* Uncorrectable error */ +#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_NFE 0x0002 /* Rcvd ERR_NONFATAL */ +#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_FE 0x0004 /* Rcvd ERR_FATAL */ +#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_IN_EXT 0x0006 /* Reason in Trig Reason Extension field */ #define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008 /* Interrupt Status */ #define PCI_EXP_DPC_RP_BUSY 0x0010 /* Root Port Busy */ #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */ +#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO 0x0000 /* RP PIO error */ +#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_SW_TRIGGER 0x0020 /* DPC SW Trigger bit */ #define PCI_EXP_DPC_RP_PIO_FEP 0x1f00 /* RP PIO First Err Ptr */ #define PCI_EXP_DPC_SOURCE_ID 0x0A /* DPC Source Identifier */ -- cgit v1.2.3 From d30fea25845ff65ea1fb255d7b615cd02b65095b Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Tue, 10 Oct 2023 15:44:30 -0500 Subject: PCI/ATS: Show PASID Capability register width in bitmasks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PASID Capability and Control registers are both 16 bits wide. Use 16-bit wide constants in field names to match the register width. No functional change intended. Link: https://lore.kernel.org/r/20231010204436.1000644-5-helgaas@kernel.org Signed-off-by: Bjorn Helgaas Reviewed-by: Ilpo Järvinen Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan --- include/uapi/linux/pci_regs.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 0fd621505246..f35d73efe223 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -930,12 +930,12 @@ /* Process Address Space ID */ #define PCI_PASID_CAP 0x04 /* PASID feature register */ -#define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ -#define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */ +#define PCI_PASID_CAP_EXEC 0x0002 /* Exec permissions Supported */ +#define PCI_PASID_CAP_PRIV 0x0004 /* Privilege Mode Supported */ #define PCI_PASID_CTRL 0x06 /* PASID control register */ -#define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ -#define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ -#define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */ +#define PCI_PASID_CTRL_ENABLE 0x0001 /* Enable bit */ +#define PCI_PASID_CTRL_EXEC 0x0002 /* Exec permissions Enable */ +#define PCI_PASID_CTRL_PRIV 0x0004 /* Privilege Mode Enable */ #define PCI_EXT_CAP_PASID_SIZEOF 8 /* Single Root I/O Virtualization */ -- cgit v1.2.3 From e0701bd0e6669e4c4b0d11254f5948ebf8d0b732 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Tue, 10 Oct 2023 15:44:31 -0500 Subject: PCI/ATS: Use FIELD_GET() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use FIELD_GET() to remove dependences on the field position, i.e., the shift value. No functional change intended. Link: https://lore.kernel.org/r/20231010204436.1000644-6-helgaas@kernel.org Signed-off-by: Bjorn Helgaas Reviewed-by: Jonathan Cameron Reviewed-by: Ilpo Järvinen Reviewed-by: Kuppuswamy Sathyanarayanan --- drivers/pci/ats.c | 7 ++----- include/uapi/linux/pci_regs.h | 1 + 2 files changed, 3 insertions(+), 5 deletions(-) (limited to 'include/uapi/linux') diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index f9cc2e10b676..c570892b2090 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -9,6 +9,7 @@ * Copyright (C) 2011 Advanced Micro Devices, */ +#include #include #include #include @@ -480,8 +481,6 @@ int pci_pasid_features(struct pci_dev *pdev) } EXPORT_SYMBOL_GPL(pci_pasid_features); -#define PASID_NUMBER_SHIFT 8 -#define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT) /** * pci_max_pasids - Get maximum number of PASIDs supported by device * @pdev: PCI device structure @@ -503,9 +502,7 @@ int pci_max_pasids(struct pci_dev *pdev) pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported); - supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT; - - return (1 << supported); + return (1 << FIELD_GET(PCI_PASID_CAP_WIDTH, supported)); } EXPORT_SYMBOL_GPL(pci_max_pasids); #endif /* CONFIG_PCI_PASID */ diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index f35d73efe223..4f226db4c1dc 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -932,6 +932,7 @@ #define PCI_PASID_CAP 0x04 /* PASID feature register */ #define PCI_PASID_CAP_EXEC 0x0002 /* Exec permissions Supported */ #define PCI_PASID_CAP_PRIV 0x0004 /* Privilege Mode Supported */ +#define PCI_PASID_CAP_WIDTH 0x1f00 #define PCI_PASID_CTRL 0x06 /* PASID control register */ #define PCI_PASID_CTRL_ENABLE 0x0001 /* Enable bit */ #define PCI_PASID_CTRL_EXEC 0x0002 /* Exec permissions Enable */ -- cgit v1.2.3 From ec302b118a59785511d6f90592a8be097d67341c Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Tue, 10 Oct 2023 15:44:33 -0500 Subject: PCI/PME: Use FIELD_GET() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use FIELD_GET() to remove dependences on the field position, i.e., the shift value. No functional change intended. Link: https://lore.kernel.org/r/20231010204436.1000644-8-helgaas@kernel.org Signed-off-by: Bjorn Helgaas Reviewed-by: Ilpo Järvinen Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan --- drivers/pci/pcie/pme.c | 4 +++- include/uapi/linux/pci_regs.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'include/uapi/linux') diff --git a/drivers/pci/pcie/pme.c b/drivers/pci/pcie/pme.c index ef8ce436ead9..a2daebd9806c 100644 --- a/drivers/pci/pcie/pme.c +++ b/drivers/pci/pcie/pme.c @@ -9,6 +9,7 @@ #define dev_fmt(fmt) "PME: " fmt +#include #include #include #include @@ -235,7 +236,8 @@ static void pcie_pme_work_fn(struct work_struct *work) pcie_clear_root_pme_status(port); spin_unlock_irq(&data->lock); - pcie_pme_handle_request(port, rtsta & 0xffff); + pcie_pme_handle_request(port, + FIELD_GET(PCI_EXP_RTSTA_PME_RQ_ID, rtsta)); spin_lock_irq(&data->lock); continue; diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 4f226db4c1dc..532d30770ee5 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -637,6 +637,7 @@ #define PCI_EXP_RTCAP 0x1e /* Root Capabilities */ #define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ #define PCI_EXP_RTSTA 0x20 /* Root Status */ +#define PCI_EXP_RTSTA_PME_RQ_ID 0x0000ffff /* PME Requester ID */ #define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */ #define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */ /* -- cgit v1.2.3