From caad07ae07e3fb173e804abdd53fb96aa7186830 Mon Sep 17 00:00:00 2001 From: "Rafael J. Wysocki" Date: Mon, 22 Dec 2025 21:22:48 +0100 Subject: phy: core: Discard pm_runtime_put() return values The PHY core defines phy_pm_runtime_put() to return an int, but that return value is never used. It also passes the return value of pm_runtime_put() to the caller which is not very useful. Returning an error code from pm_runtime_put() merely means that it has not queued up a work item to check whether or not the device can be suspended and there are many perfectly valid situations in which that can happen, like after writing "on" to the devices' runtime PM "control" attribute in sysfs for one example. Modify phy_pm_runtime_put() to discard the pm_runtime_put() return value and change its return type to void. Also drop the redundant pm_runtime_enabled() call from there. No intentional functional impact. This will facilitate a planned change of the pm_runtime_put() return type to void in the future. Signed-off-by: Rafael J. Wysocki Link: https://patch.msgid.link/2556645.jE0xQCEvom@rafael.j.wysocki Signed-off-by: Vinod Koul --- include/linux/phy/phy.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'include/linux') diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index 2af0d01ebb39..ea47975e288a 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -243,7 +243,7 @@ static inline void *phy_get_drvdata(struct phy *phy) #if IS_ENABLED(CONFIG_GENERIC_PHY) int phy_pm_runtime_get(struct phy *phy); int phy_pm_runtime_get_sync(struct phy *phy); -int phy_pm_runtime_put(struct phy *phy); +void phy_pm_runtime_put(struct phy *phy); int phy_pm_runtime_put_sync(struct phy *phy); int phy_init(struct phy *phy); int phy_exit(struct phy *phy); @@ -324,11 +324,8 @@ static inline int phy_pm_runtime_get_sync(struct phy *phy) return -ENOSYS; } -static inline int phy_pm_runtime_put(struct phy *phy) +static inline void phy_pm_runtime_put(struct phy *phy) { - if (!phy) - return 0; - return -ENOSYS; } static inline int phy_pm_runtime_put_sync(struct phy *phy) -- cgit v1.2.3 From a722de305eacb382a5d306f9f8e502f81bab682d Mon Sep 17 00:00:00 2001 From: Sven Peter Date: Sun, 14 Dec 2025 11:51:34 +0000 Subject: soc: apple: Add hardware tunable support Various hardware, like the Type-C PHY or the Thunderbolt/USB4 NHI, present on Apple SoCs need machine-specific tunables passed from our bootloader m1n1 to the device tree. Add generic helpers so that we don't have to duplicate this across multiple drivers. Reviewed-by: Alyssa Rosenzweig Reviewed-by: Neal Gompa Reviewed-by: Janne Grunau Signed-off-by: Sven Peter Link: https://patch.msgid.link/20251214-b4-atcphy-v3-1-ba82b20e9459@kernel.org Signed-off-by: Vinod Koul --- drivers/soc/apple/Kconfig | 4 ++ drivers/soc/apple/Makefile | 3 ++ drivers/soc/apple/tunable.c | 80 +++++++++++++++++++++++++++++++++++++++ include/linux/soc/apple/tunable.h | 62 ++++++++++++++++++++++++++++++ 4 files changed, 149 insertions(+) create mode 100644 drivers/soc/apple/tunable.c create mode 100644 include/linux/soc/apple/tunable.h (limited to 'include/linux') diff --git a/drivers/soc/apple/Kconfig b/drivers/soc/apple/Kconfig index ad6736889231..d0ff32182a2b 100644 --- a/drivers/soc/apple/Kconfig +++ b/drivers/soc/apple/Kconfig @@ -38,6 +38,10 @@ config APPLE_SART Say 'y' here if you have an Apple SoC. +config APPLE_TUNABLE + tristate + depends on ARCH_APPLE || COMPILE_TEST + endmenu endif diff --git a/drivers/soc/apple/Makefile b/drivers/soc/apple/Makefile index 4d9ab8f3037b..0b85ab61aefe 100644 --- a/drivers/soc/apple/Makefile +++ b/drivers/soc/apple/Makefile @@ -8,3 +8,6 @@ apple-rtkit-y = rtkit.o rtkit-crashlog.o obj-$(CONFIG_APPLE_SART) += apple-sart.o apple-sart-y = sart.o + +obj-$(CONFIG_APPLE_TUNABLE) += apple-tunable.o +apple-tunable-y = tunable.o diff --git a/drivers/soc/apple/tunable.c b/drivers/soc/apple/tunable.c new file mode 100644 index 000000000000..659323839171 --- /dev/null +++ b/drivers/soc/apple/tunable.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Apple Silicon hardware tunable support + * + * Each tunable is a list with each entry containing a offset into the MMIO + * region, a mask of bits to be cleared and a set of bits to be set. These + * tunables are passed along by the previous boot stages and vary from device + * to device such that they cannot be hardcoded in the individual drivers. + * + * Copyright (C) The Asahi Linux Contributors + */ + +#include +#include +#include +#include +#include + +struct apple_tunable *devm_apple_tunable_parse(struct device *dev, + struct device_node *np, + const char *name, + struct resource *res) +{ + struct apple_tunable *tunable; + struct property *prop; + const __be32 *p; + size_t sz; + int i; + + if (resource_size(res) < 4) + return ERR_PTR(-EINVAL); + + prop = of_find_property(np, name, NULL); + if (!prop) + return ERR_PTR(-ENOENT); + + if (prop->length % (3 * sizeof(u32))) + return ERR_PTR(-EINVAL); + sz = prop->length / (3 * sizeof(u32)); + + tunable = devm_kzalloc(dev, struct_size(tunable, values, sz), GFP_KERNEL); + if (!tunable) + return ERR_PTR(-ENOMEM); + tunable->sz = sz; + + for (i = 0, p = NULL; i < tunable->sz; ++i) { + p = of_prop_next_u32(prop, p, &tunable->values[i].offset); + p = of_prop_next_u32(prop, p, &tunable->values[i].mask); + p = of_prop_next_u32(prop, p, &tunable->values[i].value); + + /* Sanity checks to catch bugs in our bootloader */ + if (tunable->values[i].offset % 4) + return ERR_PTR(-EINVAL); + if (tunable->values[i].offset > (resource_size(res) - 4)) + return ERR_PTR(-EINVAL); + } + + return tunable; +} +EXPORT_SYMBOL(devm_apple_tunable_parse); + +void apple_tunable_apply(void __iomem *regs, struct apple_tunable *tunable) +{ + size_t i; + + for (i = 0; i < tunable->sz; ++i) { + u32 val, old_val; + + old_val = readl(regs + tunable->values[i].offset); + val = old_val & ~tunable->values[i].mask; + val |= tunable->values[i].value; + if (val != old_val) + writel(val, regs + tunable->values[i].offset); + } +} +EXPORT_SYMBOL(apple_tunable_apply); + +MODULE_LICENSE("Dual MIT/GPL"); +MODULE_AUTHOR("Sven Peter "); +MODULE_DESCRIPTION("Apple Silicon hardware tunable support"); diff --git a/include/linux/soc/apple/tunable.h b/include/linux/soc/apple/tunable.h new file mode 100644 index 000000000000..531ca814cd02 --- /dev/null +++ b/include/linux/soc/apple/tunable.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Apple Silicon hardware tunable support + * + * Each tunable is a list with each entry containing a offset into the MMIO + * region, a mask of bits to be cleared and a set of bits to be set. These + * tunables are passed along by the previous boot stages and vary from device + * to device such that they cannot be hardcoded in the individual drivers. + * + * Copyright (C) The Asahi Linux Contributors + */ + +#ifndef _LINUX_SOC_APPLE_TUNABLE_H_ +#define _LINUX_SOC_APPLE_TUNABLE_H_ + +#include +#include + +/** + * Struct to store an Apple Silicon hardware tunable. + * + * Each tunable is a list with each entry containing a offset into the MMIO + * region, a mask of bits to be cleared and a set of bits to be set. These + * tunables are passed along by the previous boot stages and vary from device + * to device such that they cannot be hardcoded in the individual drivers. + * + * @param sz Number of [offset, mask, value] tuples stored in values. + * @param values [offset, mask, value] array. + */ +struct apple_tunable { + size_t sz; + struct { + u32 offset; + u32 mask; + u32 value; + } values[] __counted_by(sz); +}; + +/** + * Parse an array of hardware tunables from the device tree. + * + * @dev: Device node used for devm_kzalloc internally. + * @np: Device node which contains the tunable array. + * @name: Name of the device tree property which contains the tunables. + * @res: Resource to which the tunables will be applied, used for bound checking + * + * @return: devres allocated struct on success or PTR_ERR on failure. + */ +struct apple_tunable *devm_apple_tunable_parse(struct device *dev, + struct device_node *np, + const char *name, + struct resource *res); + +/** + * Apply a previously loaded hardware tunable. + * + * @param regs: MMIO to which the tunable will be applied. + * @param tunable: Pointer to the tunable. + */ +void apple_tunable_apply(void __iomem *regs, struct apple_tunable *tunable); + +#endif -- cgit v1.2.3 From 031314bd37cb6ce352b1300ffd4e07a7bebce1ef Mon Sep 17 00:00:00 2001 From: Pritam Manohar Sutar Date: Mon, 24 Nov 2025 16:34:49 +0530 Subject: phy: exynos5-usbdrd: support HS phy for ExynosAutov920 Enable UTMI+ phy support for this SoC which is very similar to what the existing Exynos850 supports. Add required change in phy driver to support HS phy for this SoC. Reviewed-by: Alim Akhtar Signed-off-by: Pritam Manohar Sutar Link: https://patch.msgid.link/20251124110453.2887437-3-pritam.sutar@samsung.com Signed-off-by: Vinod Koul --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 123 ++++++++++++++++++++++++++++ include/linux/soc/samsung/exynos-regs-pmu.h | 2 + 2 files changed, 125 insertions(+) (limited to 'include/linux') diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 1c8bf80119f1..7416d2e1e358 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -2054,6 +2054,126 @@ static const struct exynos5_usbdrd_phy_drvdata exynos990_usbdrd_phy = { .n_regulators = ARRAY_SIZE(exynos5_regulator_names), }; +static int exynosautov920_usbdrd_phy_init(struct phy *phy) +{ + struct phy_usb_instance *inst = phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); + int ret; + + ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) + return ret; + + /* Bypass PHY isol */ + inst->phy_cfg->phy_isol(inst, false); + + /* UTMI or PIPE3 specific init */ + inst->phy_cfg->phy_init(phy_drd); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); + + return 0; +} + +static int exynosautov920_usbdrd_phy_exit(struct phy *phy) +{ + struct phy_usb_instance *inst = phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); + int ret; + + ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) + return ret; + + exynos850_usbdrd_phy_exit(phy); + + /* enable PHY isol */ + inst->phy_cfg->phy_isol(inst, true); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); + + return 0; +} + +static int exynosautov920_usbdrd_phy_power_on(struct phy *phy) +{ + struct phy_usb_instance *inst = phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); + int ret; + + dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n"); + + ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_core_clks, + phy_drd->core_clks); + if (ret) + return ret; + + /* Enable supply */ + ret = regulator_bulk_enable(phy_drd->drv_data->n_regulators, + phy_drd->regulators); + if (ret) { + dev_err(phy_drd->dev, "Failed to enable PHY regulator(s)\n"); + goto fail_supply; + } + + return 0; + +fail_supply: + clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, + phy_drd->core_clks); + + return ret; +} + +static int exynosautov920_usbdrd_phy_power_off(struct phy *phy) +{ + struct phy_usb_instance *inst = phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); + + dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n"); + + /* Disable supply */ + regulator_bulk_disable(phy_drd->drv_data->n_regulators, + phy_drd->regulators); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, + phy_drd->core_clks); + + return 0; +} + +static const char * const exynosautov920_usb20_regulators[] = { + "dvdd", "vdd18", "vdd33", +}; + +static const struct phy_ops exynosautov920_usbdrd_phy_ops = { + .init = exynosautov920_usbdrd_phy_init, + .exit = exynosautov920_usbdrd_phy_exit, + .power_on = exynosautov920_usbdrd_phy_power_on, + .power_off = exynosautov920_usbdrd_phy_power_off, + .owner = THIS_MODULE, +}; + +static const struct exynos5_usbdrd_phy_config phy_cfg_exynosautov920[] = { + { + .id = EXYNOS5_DRDPHY_UTMI, + .phy_isol = exynos5_usbdrd_phy_isol, + .phy_init = exynos850_usbdrd_utmi_init, + }, +}; + +static const struct exynos5_usbdrd_phy_drvdata exynosautov920_usbdrd_phy = { + .phy_cfg = phy_cfg_exynosautov920, + .phy_ops = &exynosautov920_usbdrd_phy_ops, + .pmu_offset_usbdrd0_phy = EXYNOSAUTOV920_PHY_CTRL_USB20, + .clk_names = exynos5_clk_names, + .n_clks = ARRAY_SIZE(exynos5_clk_names), + .core_clk_names = exynos5_core_clk_names, + .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names), + .regulator_names = exynosautov920_usb20_regulators, + .n_regulators = ARRAY_SIZE(exynosautov920_usb20_regulators), +}; + static const struct exynos5_usbdrd_phy_config phy_cfg_gs101[] = { { .id = EXYNOS5_DRDPHY_UTMI, @@ -2260,6 +2380,9 @@ static const struct of_device_id exynos5_usbdrd_phy_of_match[] = { }, { .compatible = "samsung,exynos990-usbdrd-phy", .data = &exynos990_usbdrd_phy + }, { + .compatible = "samsung,exynosautov920-usbdrd-phy", + .data = &exynosautov920_usbdrd_phy }, { }, }; diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h index 532c6c2d1195..ab4d8be0e073 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -1015,4 +1015,6 @@ #define GS101_GRP2_INTR_BID_UPEND (0x0208) #define GS101_GRP2_INTR_BID_CLEAR (0x020c) +/* exynosautov920 */ +#define EXYNOSAUTOV920_PHY_CTRL_USB20 (0x0710) #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */ -- cgit v1.2.3 From 2fdfc1bb752e393561cf532f5d54607d70e464bc Mon Sep 17 00:00:00 2001 From: Pritam Manohar Sutar Date: Mon, 24 Nov 2025 16:34:53 +0530 Subject: phy: exynos5-usbdrd: support SS combo phy for ExynosAutov920 Update phy driver to enable SS combo phy for this SoC. New registers' definitions, phy ops (init/exit), and dedicated phy driver data structure are added for SS combo phy. Add these changes in the driver to support SS combo phy for this SoC. Reviewed-by: Alim Akhtar Signed-off-by: Pritam Manohar Sutar Link: https://patch.msgid.link/20251124110453.2887437-7-pritam.sutar@samsung.com Signed-off-by: Vinod Koul --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 325 +++++++++++++++++++++++++++- include/linux/soc/samsung/exynos-regs-pmu.h | 1 + 2 files changed, 322 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 5bbf78d44a74..5a181cb4597e 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -273,6 +273,36 @@ #define EXYNOSAUTOV920_DRD_HSPPLLTUNE 0x110 #define HSPPLLTUNE_FSEL GENMASK(18, 16) +/* ExynosAutov920 phy usb31drd port reg */ +#define EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL 0x000 +#define PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN BIT(5) +#define PHY_RST_CTRL_PIPE_LANE0_RESET_N BIT(4) +#define PHY_RST_CTRL_PHY_RESET_OVRD_EN BIT(1) +#define PHY_RST_CTRL_PHY_RESET BIT(0) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0 0x0004 +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR GENMASK(31, 16) +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK BIT(8) +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK BIT(4) +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL BIT(0) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON1 0x0008 + +#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2 0x000c +#define PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_EN BIT(0) +#define PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA GENMASK(31, 16) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0 0x100 +#define PHY_CONFIG0_PHY0_PMA_PWR_STABLE BIT(14) +#define PHY_CONFIG0_PHY0_PCS_PWR_STABLE BIT(13) +#define PHY_CONFIG0_PHY0_ANA_PWR_EN BIT(1) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7 0x11c +#define PHY_CONFIG7_PHY_TEST_POWERDOWN BIT(24) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4 0x110 +#define PHY_CONFIG4_PIPE_RX0_SRIS_MODE_EN BIT(2) + /* Exynos9 - GS101 */ #define EXYNOS850_DRD_SECPMACTL 0x48 #define SECPMACTL_PMA_ROPLL_REF_CLK_SEL GENMASK(13, 12) @@ -2077,6 +2107,251 @@ static const struct exynos5_usbdrd_phy_drvdata exynos990_usbdrd_phy = { .n_regulators = ARRAY_SIZE(exynos5_regulator_names), }; +static void +exynosautov920_usb31drd_cr_clk(struct exynos5_usbdrd_phy *phy_drd, bool high) +{ + void __iomem *reg_phy = phy_drd->reg_phy; + u32 reg; + + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + if (high) + reg |= PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK; + else + reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK; + + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + fsleep(1); +} + +static void +exynosautov920_usb31drd_port_phy_ready(struct exynos5_usbdrd_phy *phy_drd) +{ + struct device *dev = phy_drd->dev; + void __iomem *reg_phy = phy_drd->reg_phy; + static const unsigned int timeout_us = 20000; + static const unsigned int sleep_us = 40; + u32 reg; + int err; + + /* Clear cr_para_con */ + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + reg &= ~(PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK | + PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR); + reg |= PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + writel(0x0, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON1); + writel(0x0, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2); + + exynosautov920_usb31drd_cr_clk(phy_drd, true); + exynosautov920_usb31drd_cr_clk(phy_drd, false); + + /* + * The maximum time from phy reset de-assertion to de-assertion of + * tx/rx_ack can be as high as 5ms in fast simulation mode. + * Time to phy ready is < 20ms + */ + err = readl_poll_timeout(reg_phy + + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0, + reg, !(reg & PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK), + sleep_us, timeout_us); + if (err) + dev_err(dev, "timed out waiting for rx/tx_ack: %#.8x\n", reg); + + reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); +} + +static void +exynosautov920_usb31drd_cr_write(struct exynos5_usbdrd_phy *phy_drd, + u16 addr, u16 data) +{ + void __iomem *reg_phy = phy_drd->reg_phy; + u32 cnt = 0; + u32 reg; + + /* Pre Clocking */ + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + reg |= PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + + /* + * tx clks must be available prior to assertion of tx req. + * tx pstate p2 to p0 transition directly is not permitted. + * tx clk ready must be asserted synchronously on tx clk prior + * to internal transmit clk alignment sequence in the phy + * when entering from p2 to p1 to p0. + */ + do { + exynosautov920_usb31drd_cr_clk(phy_drd, true); + exynosautov920_usb31drd_cr_clk(phy_drd, false); + cnt++; + } while (cnt < 15); + + reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + + /* + * tx data path is active when tx lane is in p0 state + * and tx data en asserted. enable cr_para_wr_en. + */ + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2); + reg &= ~PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA; + reg |= FIELD_PREP(PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA, data) | + PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2); + + /* write addr */ + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + reg &= ~PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR; + reg |= FIELD_PREP(PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR, addr) | + PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK | + PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + + /* check cr_para_ack*/ + cnt = 0; + do { + /* + * data symbols are captured by phy on rising edge of the + * tx_clk when tx data enabled. + * completion of the write cycle is acknowledged by assertion + * of the cr_para_ack. + */ + exynosautov920_usb31drd_cr_clk(phy_drd, true); + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + if ((reg & PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK)) + break; + + exynosautov920_usb31drd_cr_clk(phy_drd, false); + + /* + * wait for minimum of 10 cr_para_clk cycles after phy reset + * is negated, before accessing control regs to allow for + * internal resets. + */ + cnt++; + } while (cnt < 10); + + if (cnt < 10) + exynosautov920_usb31drd_cr_clk(phy_drd, false); +} + +static void +exynosautov920_usb31drd_phy_reset(struct exynos5_usbdrd_phy *phy_drd, int val) +{ + void __iomem *reg_phy = phy_drd->reg_phy; + u32 reg; + + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + reg &= ~PHY_RST_CTRL_PHY_RESET_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + if (val) + reg |= PHY_RST_CTRL_PHY_RESET; + else + reg &= ~PHY_RST_CTRL_PHY_RESET; + + reg |= PHY_RST_CTRL_PHY_RESET_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); +} + +static void +exynosautov920_usb31drd_lane0_reset(struct exynos5_usbdrd_phy *phy_drd, int val) +{ + void __iomem *reg_phy = phy_drd->reg_phy; + u32 reg; + + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + reg |= PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + if (val) + reg &= ~PHY_RST_CTRL_PIPE_LANE0_RESET_N; + else + reg |= PHY_RST_CTRL_PIPE_LANE0_RESET_N; + + reg &= ~PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); +} + +static void +exynosautov920_usb31drd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd) +{ + void __iomem *reg_phy = phy_drd->reg_phy; + u32 reg; + + /* + * Phy and Pipe Lane reset assert. + * assert reset (phy_reset = 1). + * The lane-ack outputs are asserted during reset (tx_ack = rx_ack = 1) + */ + exynosautov920_usb31drd_phy_reset(phy_drd, 1); + exynosautov920_usb31drd_lane0_reset(phy_drd, 1); + + /* + * ANA Power En, PCS & PMA PWR Stable Set + * ramp-up power suppiles + */ + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0); + reg |= PHY_CONFIG0_PHY0_ANA_PWR_EN | PHY_CONFIG0_PHY0_PCS_PWR_STABLE | + PHY_CONFIG0_PHY0_PMA_PWR_STABLE; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0); + + fsleep(10); + + /* + * phy is not functional in test_powerdown mode, test_powerdown to be + * de-asserted for normal operation + */ + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); + reg &= ~PHY_CONFIG7_PHY_TEST_POWERDOWN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); + + /* + * phy reset signal be asserted for minimum 10us after power + * supplies are ramped-up + */ + fsleep(10); + + /* + * Phy and Pipe Lane reset assert de-assert + */ + exynosautov920_usb31drd_phy_reset(phy_drd, 0); + exynosautov920_usb31drd_lane0_reset(phy_drd, 0); + + /* Pipe_rx0_sris_mode_en = 1 */ + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4); + reg |= PHY_CONFIG4_PIPE_RX0_SRIS_MODE_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4); + + /* + * wait for lane ack outputs to de-assert (tx_ack = rx_ack = 0) + * Exit from the reset state is indicated by de-assertion of *_ack + */ + exynosautov920_usb31drd_port_phy_ready(phy_drd); + + /* override values for level settings */ + exynosautov920_usb31drd_cr_write(phy_drd, 0x22, 0x00F5); +} + +static void +exynosautov920_usb31drd_ssphy_disable(struct exynos5_usbdrd_phy *phy_drd) +{ + void __iomem *reg_phy = phy_drd->reg_phy; + u32 reg; + + /* 1. Assert reset (phy_reset = 1) */ + exynosautov920_usb31drd_lane0_reset(phy_drd, 1); + exynosautov920_usb31drd_phy_reset(phy_drd, 1); + + /* phy test power down */ + reg = readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); + reg |= PHY_CONFIG7_PHY_TEST_POWERDOWN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); +} + static void exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) { @@ -2172,12 +2447,15 @@ exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) /* after POR low and delay 75us, PHYCLOCK is guaranteed. */ fsleep(75); - /* force pipe3 signal for link */ + /* Disable forcing pipe interface */ reg = readl(reg_phy + EXYNOS850_DRD_LINKCTRL); - reg |= LINKCTRL_FORCE_PIPE_EN; - reg &= ~LINKCTRL_FORCE_PHYSTATUS; - reg |= LINKCTRL_FORCE_RXELECIDLE; + reg &= ~LINKCTRL_FORCE_PIPE_EN; writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); + + /* Pclk to pipe_clk */ + reg = readl(reg_phy + EXYNOS2200_DRD_CLKRST); + reg |= EXYNOS2200_CLKRST_LINK_PCLK_SEL; + writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST); } static void @@ -2264,6 +2542,8 @@ static int exynosautov920_usbdrd_combo_phy_exit(struct phy *phy) if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) exynosautov920_usbdrd_hsphy_disable(phy_drd); + else if (inst->phy_cfg->id == EXYNOS5_DRDPHY_PIPE3) + exynosautov920_usb31drd_ssphy_disable(phy_drd); /* enable PHY isol */ inst->phy_cfg->phy_isol(inst, true); @@ -2320,10 +2600,44 @@ static int exynosautov920_usbdrd_phy_power_off(struct phy *phy) return 0; } +static const char * const exynosautov920_usb30_regulators[] = { + "dvdd", "vdd18", +}; + static const char * const exynosautov920_usb20_regulators[] = { "dvdd", "vdd18", "vdd33", }; +static const struct +exynos5_usbdrd_phy_config usb31drd_phy_cfg_exynosautov920[] = { + { + .id = EXYNOS5_DRDPHY_PIPE3, + .phy_isol = exynos5_usbdrd_phy_isol, + .phy_init = exynosautov920_usb31drd_pipe3_init, + }, +}; + +static const struct phy_ops exynosautov920_usb31drd_combo_ssphy_ops = { + .init = exynosautov920_usbdrd_phy_init, + .exit = exynosautov920_usbdrd_combo_phy_exit, + .power_on = exynosautov920_usbdrd_phy_power_on, + .power_off = exynosautov920_usbdrd_phy_power_off, + .owner = THIS_MODULE, +}; + +static const +struct exynos5_usbdrd_phy_drvdata exynosautov920_usb31drd_combo_ssphy = { + .phy_cfg = usb31drd_phy_cfg_exynosautov920, + .phy_ops = &exynosautov920_usb31drd_combo_ssphy_ops, + .pmu_offset_usbdrd0_phy = EXYNOSAUTOV920_PHY_CTRL_USB31, + .clk_names = exynos5_clk_names, + .n_clks = ARRAY_SIZE(exynos5_clk_names), + .core_clk_names = exynos5_core_clk_names, + .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names), + .regulator_names = exynosautov920_usb30_regulators, + .n_regulators = ARRAY_SIZE(exynosautov920_usb30_regulators), +}; + static const struct phy_ops exynosautov920_usbdrd_combo_hsphy_ops = { .init = exynosautov920_usbdrd_phy_init, .exit = exynosautov920_usbdrd_combo_phy_exit, @@ -2588,6 +2902,9 @@ static const struct of_device_id exynos5_usbdrd_phy_of_match[] = { }, { .compatible = "samsung,exynos990-usbdrd-phy", .data = &exynos990_usbdrd_phy + }, { + .compatible = "samsung,exynosautov920-usb31drd-combo-ssphy", + .data = &exynosautov920_usb31drd_combo_ssphy }, { .compatible = "samsung,exynosautov920-usbdrd-combo-hsphy", .data = &exynosautov920_usbdrd_combo_hsphy diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h index ab4d8be0e073..db8a7ca81080 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -1017,4 +1017,5 @@ /* exynosautov920 */ #define EXYNOSAUTOV920_PHY_CTRL_USB20 (0x0710) +#define EXYNOSAUTOV920_PHY_CTRL_USB31 (0x0714) #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */ -- cgit v1.2.3 From 41c6cac6decd5123db1da8ca240a9c808b0ae6ce Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 13 Jan 2026 01:20:48 +0200 Subject: phy: hdmi: Add HDMI 2.1 FRL configuration options The HDMI 2.1 specification introduced the Fixed Rate Link (FRL) mode, aiming to replace the older Transition-Minimized Differential Signaling (TMDS) mode used in previous HDMI versions to support much higher bandwidths (up to 48 Gbps) for modern video and audio formats. FRL has been designed to support ultra high resolution formats at high refresh rates like 8K@60Hz or 4K@120Hz, and eliminates the need for dynamic bandwidth adjustments, which reduces latency. It operates with 3 or 4 lanes at different link rates: 3Gbps, 6Gbps, 8Gbps, 10Gbps or 12Gbps. Add support for configuring the FRL mode for HDMI PHYs. Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-1-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul --- include/linux/phy/phy-hdmi.h | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h index f0ec963c6e84..d4cf4430ee8f 100644 --- a/include/linux/phy/phy-hdmi.h +++ b/include/linux/phy/phy-hdmi.h @@ -6,16 +6,31 @@ #ifndef __PHY_HDMI_H_ #define __PHY_HDMI_H_ +#include + +enum phy_hdmi_mode { + PHY_HDMI_MODE_TMDS, + PHY_HDMI_MODE_FRL, +}; + /** * struct phy_configure_opts_hdmi - HDMI configuration set - * @tmds_char_rate: HDMI TMDS Character Rate in Hertz. * @bpc: Bits per color channel. + * @tmds_char_rate: HDMI TMDS Character Rate in Hertz. + * @frl.rate_per_lane: HDMI FRL Rate per Lane in Gbps. + * @frl.lanes: HDMI FRL lanes count. * * This structure is used to represent the configuration state of a HDMI phy. */ struct phy_configure_opts_hdmi { - unsigned long long tmds_char_rate; unsigned int bpc; + union { + unsigned long long tmds_char_rate; + struct { + u8 rate_per_lane; + u8 lanes; + } frl; + }; }; #endif /* __PHY_HDMI_H_ */ -- cgit v1.2.3