From e491ebea157ff3ba18483ea0f82a9536dc393dec Mon Sep 17 00:00:00 2001 From: Kaustabh Chakraborty Date: Sat, 16 May 2026 03:08:36 +0530 Subject: mfd: sec: Add support for S2MU005 PMIC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Samsung's S2MU005 PMIC includes subdevices for a charger, an MUIC (Micro USB Interface Controller), and flash and RGB LED controllers. S2MU005's interrupt registers divided into three domains, each for the charger, flash LEDs, and the MUIC, packed into a single regmap IRQ chip construct. In devices other than S2MPG1X, the revision can be retrieved from the first register of the PMIC regmap. In S2MU005 however, the location is in offset 0x73. Introduce a switch-case block to allow selecting the REG_ID register. S2MU005 also has a field mask for the revision. Apply it using FIELD_GET() and get the extracted value. Add initial support for S2MU005 in the PMIC driver, along with its three interrupt chips, and support for allowing to fetch revision based on the device variant. Co-developed-by: Łukasz Lebiedziński Signed-off-by: Łukasz Lebiedziński Signed-off-by: Kaustabh Chakraborty Link: https://patch.msgid.link/20260516-s2mu005-pmic-v7-4-73f9702fb461@disroot.org Signed-off-by: Lee Jones --- include/linux/mfd/samsung/core.h | 1 + include/linux/mfd/samsung/irq.h | 66 +++++++ include/linux/mfd/samsung/s2mu005.h | 332 ++++++++++++++++++++++++++++++++++++ 3 files changed, 399 insertions(+) create mode 100644 include/linux/mfd/samsung/s2mu005.h (limited to 'include/linux') diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h index 4480c631110a..6191f409de94 100644 --- a/include/linux/mfd/samsung/core.h +++ b/include/linux/mfd/samsung/core.h @@ -47,6 +47,7 @@ enum sec_device_type { S2MPS15X, S2MPU02, S2MPU05, + S2MU005, }; /** diff --git a/include/linux/mfd/samsung/irq.h b/include/linux/mfd/samsung/irq.h index 6eab95de6fa8..19d0f0e12944 100644 --- a/include/linux/mfd/samsung/irq.h +++ b/include/linux/mfd/samsung/irq.h @@ -408,6 +408,72 @@ enum s2mpu05_irq { #define S2MPU05_IRQ_INT140C_MASK BIT(1) #define S2MPU05_IRQ_TSD_MASK BIT(2) +enum s2mu005_irq { + S2MU005_IRQ_CHGR_DETBAT, + S2MU005_IRQ_CHGR_BAT, + S2MU005_IRQ_CHGR_IVR, + S2MU005_IRQ_CHGR_EVENT, + S2MU005_IRQ_CHGR_CHG, + S2MU005_IRQ_CHGR_VMID, + S2MU005_IRQ_CHGR_WCIN, + S2MU005_IRQ_CHGR_VBUS, + + S2MU005_IRQ_FLED_LBPROT, + S2MU005_IRQ_FLED_OPENCH2, + S2MU005_IRQ_FLED_OPENCH1, + S2MU005_IRQ_FLED_SHORTCH2, + S2MU005_IRQ_FLED_SHORTCH1, + + S2MU005_IRQ_MUIC_ATTACH, + S2MU005_IRQ_MUIC_DETACH, + S2MU005_IRQ_MUIC_KP, + S2MU005_IRQ_MUIC_LKP, + S2MU005_IRQ_MUIC_LKR, + S2MU005_IRQ_MUIC_RIDCHG, + + S2MU005_IRQ_MUIC_VBUSON, + S2MU005_IRQ_MUIC_RSVD, + S2MU005_IRQ_MUIC_ADC, + S2MU005_IRQ_MUIC_STUCK, + S2MU005_IRQ_MUIC_STUCKRCV, + S2MU005_IRQ_MUIC_MHDL, + S2MU005_IRQ_MUIC_AVCHG, + S2MU005_IRQ_MUIC_VBUSOFF, + + S2MU005_IRQ_NR, +}; + +#define S2MU005_IRQ_CHGR_DETBAT_MASK BIT(0) +#define S2MU005_IRQ_CHGR_BAT_MASK BIT(1) +#define S2MU005_IRQ_CHGR_IVR_MASK BIT(2) +#define S2MU005_IRQ_CHGR_EVENT_MASK BIT(3) +#define S2MU005_IRQ_CHGR_CHG_MASK BIT(4) +#define S2MU005_IRQ_CHGR_VMID_MASK BIT(5) +#define S2MU005_IRQ_CHGR_WCIN_MASK BIT(6) +#define S2MU005_IRQ_CHGR_VBUS_MASK BIT(7) + +#define S2MU005_IRQ_FLED_LBPROT_MASK BIT(2) +#define S2MU005_IRQ_FLED_OPENCH2_MASK BIT(4) +#define S2MU005_IRQ_FLED_OPENCH1_MASK BIT(5) +#define S2MU005_IRQ_FLED_SHORTCH2_MASK BIT(6) +#define S2MU005_IRQ_FLED_SHORTCH1_MASK BIT(7) + +#define S2MU005_IRQ_MUIC_ATTACH_MASK BIT(0) +#define S2MU005_IRQ_MUIC_DETACH_MASK BIT(1) +#define S2MU005_IRQ_MUIC_KP_MASK BIT(2) +#define S2MU005_IRQ_MUIC_LKP_MASK BIT(3) +#define S2MU005_IRQ_MUIC_LKR_MASK BIT(4) +#define S2MU005_IRQ_MUIC_RIDCHG_MASK BIT(5) + +#define S2MU005_IRQ_MUIC_VBUSON_MASK BIT(0) +#define S2MU005_IRQ_MUIC_RSVD_MASK BIT(1) +#define S2MU005_IRQ_MUIC_ADC_MASK BIT(2) +#define S2MU005_IRQ_MUIC_STUCK_MASK BIT(3) +#define S2MU005_IRQ_MUIC_STUCKRCV_MASK BIT(4) +#define S2MU005_IRQ_MUIC_MHDL_MASK BIT(5) +#define S2MU005_IRQ_MUIC_AVCHG_MASK BIT(6) +#define S2MU005_IRQ_MUIC_VBUSOFF_MASK BIT(7) + enum s5m8767_irq { S5M8767_IRQ_PWRR, S5M8767_IRQ_PWRF, diff --git a/include/linux/mfd/samsung/s2mu005.h b/include/linux/mfd/samsung/s2mu005.h new file mode 100644 index 000000000000..46e7759545af --- /dev/null +++ b/include/linux/mfd/samsung/s2mu005.h @@ -0,0 +1,332 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2015 Samsung Electronics Co., Ltd + * Copyright (c) 2026 Kaustabh Chakraborty + * Copyright (c) 2026 Łukasz Lebiedziński + */ + +#ifndef __LINUX_MFD_S2MU005_H +#define __LINUX_MFD_S2MU005_H + +#include +#include + +/* S2MU005 registers */ +enum s2mu005_reg { + S2MU005_REG_CHGR_INT1, + S2MU005_REG_CHGR_INT1M, + + S2MU005_REG_FLED_INT1, + S2MU005_REG_FLED_INT1M, + + S2MU005_REG_MUIC_INT1, + S2MU005_REG_MUIC_INT2, + S2MU005_REG_MUIC_INT1M, + S2MU005_REG_MUIC_INT2M, + + S2MU005_REG_CHGR_STATUS0, + S2MU005_REG_CHGR_STATUS1, + S2MU005_REG_CHGR_STATUS2, + S2MU005_REG_CHGR_STATUS3, + S2MU005_REG_CHGR_STATUS4, + S2MU005_REG_CHGR_STATUS5, + S2MU005_REG_CHGR_CTRL0, + S2MU005_REG_CHGR_CTRL1, + S2MU005_REG_CHGR_CTRL2, + S2MU005_REG_CHGR_CTRL3, + S2MU005_REG_CHGR_CTRL4, + S2MU005_REG_CHGR_CTRL5, + S2MU005_REG_CHGR_CTRL6, + S2MU005_REG_CHGR_CTRL7, + S2MU005_REG_CHGR_CTRL8, + S2MU005_REG_CHGR_CTRL9, + S2MU005_REG_CHGR_CTRL10, + S2MU005_REG_CHGR_CTRL11, + S2MU005_REG_CHGR_CTRL12, + S2MU005_REG_CHGR_CTRL13, + S2MU005_REG_CHGR_CTRL14, + S2MU005_REG_CHGR_CTRL15, + S2MU005_REG_CHGR_CTRL16, + S2MU005_REG_CHGR_CTRL17, + S2MU005_REG_CHGR_CTRL18, + S2MU005_REG_CHGR_CTRL19, + S2MU005_REG_CHGR_TEST0, + S2MU005_REG_CHGR_TEST1, + S2MU005_REG_CHGR_TEST2, + S2MU005_REG_CHGR_TEST3, + S2MU005_REG_CHGR_TEST4, + S2MU005_REG_CHGR_TEST5, + S2MU005_REG_CHGR_TEST6, + S2MU005_REG_CHGR_TEST7, + S2MU005_REG_CHGR_TEST8, + S2MU005_REG_CHGR_TEST9, + S2MU005_REG_CHGR_TEST10, + + S2MU005_REG_FLED_STATUS, + S2MU005_REG_FLED_CH0_CTRL0, + S2MU005_REG_FLED_CH0_CTRL1, + S2MU005_REG_FLED_CH0_CTRL2, + S2MU005_REG_FLED_CH0_CTRL3, + S2MU005_REG_FLED_CH1_CTRL0, + S2MU005_REG_FLED_CH1_CTRL1, + S2MU005_REG_FLED_CH1_CTRL2, + S2MU005_REG_FLED_CH1_CTRL3, + S2MU005_REG_FLED_CTRL0, + S2MU005_REG_FLED_CTRL1, + S2MU005_REG_FLED_CTRL2, + S2MU005_REG_FLED_CTRL3, + S2MU005_REG_FLED_CTRL4, + S2MU005_REG_FLED_CTRL5, + S2MU005_REG_FLED_CTRL6, + + S2MU005_REG_RGB_EN, + S2MU005_REG_RGB_CH0_CTRL, + S2MU005_REG_RGB_CH1_CTRL, + S2MU005_REG_RGB_CH2_CTRL, + S2MU005_REG_RGB_CH0_RAMP, + S2MU005_REG_RGB_CH0_STAY, + S2MU005_REG_RGB_CH1_RAMP, + S2MU005_REG_RGB_CH1_STAY, + S2MU005_REG_RGB_CH2_RAMP, + S2MU005_REG_RGB_CH2_STAY, + S2MU005_REG_RGB_TEST0, + S2MU005_REG_RGB_CTRL0, + + S2MU005_REG_MUIC_ADC, + S2MU005_REG_MUIC_DEV1, + S2MU005_REG_MUIC_DEV2, + S2MU005_REG_MUIC_DEV3, + S2MU005_REG_MUIC_BUTTON1, + S2MU005_REG_MUIC_BUTTON2, + S2MU005_REG_MUIC_RESET, + S2MU005_REG_MUIC_CHGTYPE, + S2MU005_REG_MUIC_DEVAPPLE, + S2MU005_REG_MUIC_BCDRESCAN, + S2MU005_REG_MUIC_TEST1, + S2MU005_REG_MUIC_TEST2, + S2MU005_REG_MUIC_TEST3, + + S2MU005_REG_ID = 0x73, + + S2MU005_REG_MUIC_CTRL1 = 0xb2, + S2MU005_REG_MUIC_TIMERSET1, + S2MU005_REG_MUIC_TIMERSET2, + S2MU005_REG_MUIC_SWCTRL, + S2MU005_REG_MUIC_TIMERSET3, + S2MU005_REG_MUIC_CTRL2, + S2MU005_REG_MUIC_CTRL3, + + S2MU005_REG_MUIC_LDOADC_L = 0xbf, + S2MU005_REG_MUIC_LDOADC_H, +}; + +#define S2MU005_REG_FLED_CH_CTRL0(x) (S2MU005_REG_FLED_CH0_CTRL0 + 4 * (x)) +#define S2MU005_REG_FLED_CH_CTRL1(x) (S2MU005_REG_FLED_CH0_CTRL1 + 4 * (x)) +#define S2MU005_REG_FLED_CH_CTRL2(x) (S2MU005_REG_FLED_CH0_CTRL2 + 4 * (x)) +#define S2MU005_REG_FLED_CH_CTRL3(x) (S2MU005_REG_FLED_CH0_CTRL3 + 4 * (x)) + +#define S2MU005_REG_RGB_CH_CTRL(x) (S2MU005_REG_RGB_CH0_CTRL + 1 * (x)) +#define S2MU005_REG_RGB_CH_RAMP(x) (S2MU005_REG_RGB_CH0_RAMP + 2 * (x)) +#define S2MU005_REG_RGB_CH_STAY(x) (S2MU005_REG_RGB_CH0_STAY + 2 * (x)) + +/* S2MU005_REG_CHGR_STATUS0 */ +#define S2MU005_CHGR_VBUS BIT(7) +#define S2MU005_CHGR_WCIN BIT(6) +#define S2MU005_CHGR_VMID BIT(5) +#define S2MU005_CHGR_CHG BIT(4) +#define S2MU005_CHGR_STAT GENMASK(3, 0) + +#define S2MU005_CHGR_STAT_DONE 8 +#define S2MU005_CHGR_STAT_TOPOFF 7 +#define S2MU005_CHGR_STAT_DONE_FLAG 6 +#define S2MU005_CHGR_STAT_CV 5 +#define S2MU005_CHGR_STAT_CC 4 +#define S2MU005_CHGR_STAT_COOL_CHG 3 +#define S2MU005_CHGR_STAT_PRE_CHG 2 + +/* S2MU005_REG_CHGR_STATUS1 */ +#define S2MU005_CHGR_DETBAT BIT(7) +#define S2MU005_CHGR_VBUS_OVP GENMASK(6, 4) + +#define S2MU005_CHGR_VBUS_OVP_OVERVOLT 2 + +/* S2MU005_REG_CHGR_STATUS2 */ +#define S2MU005_CHGR_BAT GENMASK(6, 4) + +#define S2MU005_CHGR_BAT_VOLT_DET 7 +#define S2MU005_CHGR_BAT_FAST_CHG_DET 6 +#define S2MU005_CHGR_BAT_COOL_CHG_DET 5 +#define S2MU005_CHGR_BAT_LOW_CHG 2 +#define S2MU005_CHGR_BAT_SELF_DISCHG 1 +#define S2MU005_CHGR_BAT_OVP_DET 0 + +/* S2MU005_REG_CHGR_STATUS3 */ +#define S2MU005_CHGR_EVT GENMASK(3, 0) + +#define S2MU005_CHGR_EVT_WDT_RST 6 +#define S2MU005_CHGR_EVT_WDT_SUSP 5 +#define S2MU005_CHGR_EVT_VSYS_VUVLO 4 +#define S2MU005_CHGR_EVT_VSYS_VOVP 3 +#define S2MU005_CHGR_EVT_THERM_FOLDBACK 2 +#define S2MU005_CHGR_EVT_THERM_SHUTDOWN 1 + +/* S2MU005_REG_CHGR_CTRL0 */ +#define S2MU005_CHGR_CHG_EN BIT(4) +#define S2MU005_CHGR_OP_MODE GENMASK(2, 0) + +#define S2MU005_CHGR_OP_MODE_OTG BIT(2) +#define S2MU005_CHGR_OP_MODE_CHG BIT(1) + +/* S2MU005_REG_CHGR_CTRL1 */ +#define S2MU005_CHGR_VIN_DROP GENMASK(6, 4) + +/* S2MU005_REG_CHGR_CTRL2 */ +#define S2MU005_CHGR_IN_CURR_LIM GENMASK(5, 0) + +/* S2MU005_REG_CHGR_CTRL4 */ +#define S2MU005_CHGR_OTG_OCP_ON BIT(5) +#define S2MU005_CHGR_OTG_OCP_OFF BIT(4) +#define S2MU005_CHGR_OTG_OCP GENMASK(3, 2) +#define S2MU005_CHGR_OTG_OCP_1P5A 0x3 + +/* S2MU005_REG_CHGR_CTRL5 */ +#define S2MU005_CHGR_VMID_BOOST GENMASK(4, 0) +#define S2MU005_CHGR_VMID_BOOST_5P1V 0x16 + +/* S2MU005_REG_CHGR_CTRL6 */ +#define S2MU005_CHGR_COOL_CHG_CURR GENMASK(5, 0) + +/* S2MU005_REG_CHGR_CTRL7 */ +#define S2MU005_CHGR_FAST_CHG_CURR GENMASK(5, 0) + +/* S2MU005_REG_CHGR_CTRL8 */ +#define S2MU005_CHGR_VF_VBAT GENMASK(6, 1) + +/* S2MU005_REG_CHGR_CTRL10 */ +#define S2MU005_CHGR_TOPOFF_CURR(x) (GENMASK(3, 0) << 4 * (x)) + +/* S2MU005_REG_CHGR_CTRL11 */ +#define S2MU005_CHGR_OSC_BOOST GENMASK(6, 5) +#define S2MU005_CHGR_OSC_BUCK GENMASK(4, 3) +#define S2MU005_CHGR_OSC_BOOST_2MHZ 0x3 + +/* S2MU005_REG_CHGR_CTRL12 */ +#define S2MU005_CHGR_WDT GENMASK(2, 0) + +#define S2MU005_CHGR_WDT_ON BIT(2) +#define S2MU005_CHGR_WDT_OFF BIT(1) + +/* S2MU005_REG_CHGR_CTRL15 */ +#define S2MU005_CHGR_OTG_EN GENMASK(3, 2) +#define S2MU005_CHGR_OTG_EN_ON 0x3 + +/* S2MU005_REG_FLED_STATUS */ +#define S2MU005_FLED_FLASH_STATUS(x) (BIT(7) >> 2 * (x)) +#define S2MU005_FLED_TORCH_STATUS(x) (BIT(6) >> 2 * (x)) + +/* S2MU005_REG_FLED_CHx_CTRL0 */ +#define S2MU005_FLED_FLASH_IOUT GENMASK(3, 0) + +/* S2MU005_REG_FLED_CHx_CTRL1 */ +#define S2MU005_FLED_TORCH_IOUT GENMASK(3, 0) + +/* S2MU005_REG_FLED_CHx_CTRL2 */ +#define S2MU005_FLED_TORCH_TIMEOUT GENMASK(3, 0) + +/* S2MU005_REG_FLED_CHx_CTRL3 */ +#define S2MU005_FLED_FLASH_TIMEOUT GENMASK(3, 0) + +/* S2MU005_REG_FLED_CTRL1 */ +#define S2MU005_FLED_CH_EN BIT(7) + +/* + * S2MU005_REG_FLED_CTRL4 - Rev. EVT0 + * S2MU005_REG_FLED_CTRL6 - Rev. EVT1 and later + */ +#define S2MU005_FLED_FLASH_EN(x) (GENMASK(7, 6) >> 4 * (x)) +#define S2MU005_FLED_TORCH_EN(x) (GENMASK(5, 4) >> 4 * (x)) + +/* S2MU005_REG_RGB_EN */ +#define S2MU005_RGB_RESET BIT(6) +#define S2MU005_RGB_SLOPE GENMASK(5, 0) + +#define S2MU005_RGB_SLOPE_CONST (BIT(4) | BIT(2) | BIT(0)) +#define S2MU005_RGB_SLOPE_SMOOTH (BIT(5) | BIT(3) | BIT(1)) + +/* S2MU005_REG_RGB_CHx_RAMP */ +#define S2MU005_RGB_CH_RAMP_UP GENMASK(7, 4) +#define S2MU005_RGB_CH_RAMP_DN GENMASK(3, 0) + +/* S2MU005_REG_RGB_CHx_STAY */ +#define S2MU005_RGB_CH_STAY_HI GENMASK(7, 4) +#define S2MU005_RGB_CH_STAY_LO GENMASK(3, 0) + +/* S2MU005_REG_MUIC_DEV1 */ +#define S2MU005_MUIC_OTG BIT(7) +#define S2MU005_MUIC_DCP BIT(6) +#define S2MU005_MUIC_CDP BIT(5) +#define S2MU005_MUIC_T1_T2_CHG BIT(4) +#define S2MU005_MUIC_UART BIT(3) +#define S2MU005_MUIC_SDP BIT(2) +#define S2MU005_MUIC_LANHUB BIT(1) +#define S2MU005_MUIC_AUDIO BIT(0) + +/* S2MU005_REG_MUIC_DEV2 */ +#define S2MU005_MUIC_SDP_1P8S BIT(7) +#define S2MU005_MUIC_AV BIT(6) +#define S2MU005_MUIC_TTY BIT(5) +#define S2MU005_MUIC_PPD BIT(4) +#define S2MU005_MUIC_JIG_UART_OFF BIT(3) +#define S2MU005_MUIC_JIG_UART_ON BIT(2) +#define S2MU005_MUIC_JIG_USB_OFF BIT(1) +#define S2MU005_MUIC_JIG_USB_ON BIT(0) + +/* S2MU005_REG_MUIC_DEV3 */ +#define S2MU005_MUIC_U200_CHG BIT(7) +#define S2MU005_MUIC_VBUS_AV BIT(4) +#define S2MU005_MUIC_VBUS_R255 BIT(1) +#define S2MU005_MUIC_MHL BIT(0) + +/* S2MU005_REG_MUIC_DEVAPPLE */ +#define S2MU005_MUIC_APPLE_CHG_0P5A BIT(7) +#define S2MU005_MUIC_APPLE_CHG_1P0A BIT(6) +#define S2MU005_MUIC_APPLE_CHG_2P0A BIT(5) +#define S2MU005_MUIC_APPLE_CHG_2P4A BIT(4) +#define S2MU005_MUIC_SDP_DCD_OUT BIT(3) +#define S2MU005_MUIC_RID_WAKEUP BIT(2) +#define S2MU005_MUIC_VBUS_WAKEUP BIT(1) +#define S2MU005_MUIC_BCV1P2_OR_OPEN BIT(0) + +/* S2MU005_REG_ID */ +#define S2MU005_ID_MASK GENMASK(3, 0) + +/* S2MU005_REG_MUIC_SWCTRL */ +#define S2MU005_MUIC_DM_DP GENMASK(7, 2) +#define S2MU005_MUIC_JIG BIT(0) + +#define S2MU005_MUIC_DM_DP_UART 0x12 +#define S2MU005_MUIC_DM_DP_USB 0x09 + +/* S2MU005_REG_MUIC_CTRL1 */ +#define S2MU005_MUIC_OPEN BIT(4) +#define S2MU005_MUIC_RAW_DATA BIT(3) +#define S2MU005_MUIC_MAN_SW BIT(2) +#define S2MU005_MUIC_WAIT BIT(1) +#define S2MU005_MUIC_IRQ BIT(0) + +/* S2MU005_REG_MUIC_CTRL3 */ +#define S2MU005_MUIC_ONESHOT_ADC BIT(2) + +/* S2MU005_REG_MUIC_LDOADC_L and S2MU005_REG_MUIC_LDOADC_H */ +#define S2MU005_MUIC_VSET GENMASK(4, 0) + +#define S2MU005_MUIC_VSET_3P0V 0x1f +#define S2MU005_MUIC_VSET_2P6V 0x0e +#define S2MU005_MUIC_VSET_2P4V 0x0c +#define S2MU005_MUIC_VSET_2P2V 0x0a +#define S2MU005_MUIC_VSET_2P0V 0x08 +#define S2MU005_MUIC_VSET_1P5V 0x03 +#define S2MU005_MUIC_VSET_1P4V 0x02 +#define S2MU005_MUIC_VSET_1P2V 0x00 + +#endif /* __LINUX_MFD_S2MU005_H */ -- cgit v1.2.3 From 6a2cb13761d90ef3fa960db189a2cc1bdf965ae1 Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Tue, 7 Apr 2026 16:26:48 +0300 Subject: mfd: bd72720: Drop BUCK11 ID The BD72720 header reserves an ID for BUCK11. While this does not (at the moment) cause problems I can see, it is misleading as the BD72720 contains only 10 BUCKs. Make the code clearer and drop the BUCK11 ID. Fixes: af25277b1ddc ("mfd: rohm-bd71828: Support ROHM BD72720") Signed-off-by: Matti Vaittinen Link: https://patch.msgid.link/812c3749a18d609d6f4698506bc516ec7183dfdd.1775565298.git.mazziesaccount@gmail.com Signed-off-by: Lee Jones --- include/linux/mfd/rohm-bd72720.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/mfd/rohm-bd72720.h b/include/linux/mfd/rohm-bd72720.h index ae7343bcab06..d8ddbf232bb3 100644 --- a/include/linux/mfd/rohm-bd72720.h +++ b/include/linux/mfd/rohm-bd72720.h @@ -21,7 +21,6 @@ enum { BD72720_BUCK8, BD72720_BUCK9, BD72720_BUCK10, - BD72720_BUCK11, BD72720_LDO1, BD72720_LDO2, BD72720_LDO3, -- cgit v1.2.3 From 9adbe53e32cdf3785cf71e27962282c628e97f5c Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Tue, 31 Mar 2026 19:43:46 +0400 Subject: mfd: bq257xx: Add BQ25792 support Add register definitions and a new 'type' enum to be passed via MFD private data to support the BQ25792, which is a newer variant of the BQ257xx family. BQ25792 shares similar logic of operation with the already supported BQ25703A but has a completely different register map and different electrical constraints. Signed-off-by: Alexey Charkov Tested-by: Chris Morgan Link: https://patch.msgid.link/20260331-bq25792-v6-9-0278fba33eb9@flipper.net Signed-off-by: Lee Jones --- drivers/mfd/bq257xx.c | 54 +++++- include/linux/mfd/bq257xx.h | 412 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 463 insertions(+), 3 deletions(-) (limited to 'include/linux') diff --git a/drivers/mfd/bq257xx.c b/drivers/mfd/bq257xx.c index e9d49dac0a16..054342c60b73 100644 --- a/drivers/mfd/bq257xx.c +++ b/drivers/mfd/bq257xx.c @@ -39,6 +39,39 @@ static const struct regmap_config bq25703_regmap_config = { .val_format_endian = REGMAP_ENDIAN_LITTLE, }; +static const struct regmap_range bq25792_writeable_reg_ranges[] = { + regmap_reg_range(BQ25792_REG00_MIN_SYS_VOLTAGE, + BQ25792_REG18_NTC_CONTROL_1), + regmap_reg_range(BQ25792_REG28_CHARGER_MASK_0, + BQ25792_REG30_ADC_FUNCTION_DISABLE_1), +}; + +static const struct regmap_access_table bq25792_writeable_regs = { + .yes_ranges = bq25792_writeable_reg_ranges, + .n_yes_ranges = ARRAY_SIZE(bq25792_writeable_reg_ranges), +}; + +static const struct regmap_range bq25792_volatile_reg_ranges[] = { + regmap_reg_range(BQ25792_REG19_ICO_CURRENT_LIMIT, + BQ25792_REG27_FAULT_FLAG_1), + regmap_reg_range(BQ25792_REG31_IBUS_ADC, + BQ25792_REG47_DPDM_DRIVER), +}; + +static const struct regmap_access_table bq25792_volatile_regs = { + .yes_ranges = bq25792_volatile_reg_ranges, + .n_yes_ranges = ARRAY_SIZE(bq25792_volatile_reg_ranges), +}; + +static const struct regmap_config bq25792_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = BQ25792_REG48_PART_INFORMATION, + .cache_type = REGCACHE_MAPLE, + .wr_table = &bq25792_writeable_regs, + .volatile_table = &bq25792_volatile_regs, +}; + static const struct mfd_cell cells[] = { MFD_CELL_NAME("bq257xx-regulator"), MFD_CELL_NAME("bq257xx-charger"), @@ -46,6 +79,7 @@ static const struct mfd_cell cells[] = { static int bq257xx_probe(struct i2c_client *client) { + const struct regmap_config *rcfg; struct bq257xx_device *ddata; int ret; @@ -53,9 +87,21 @@ static int bq257xx_probe(struct i2c_client *client) if (!ddata) return -ENOMEM; + ddata->type = (uintptr_t)i2c_get_match_data(client); ddata->client = client; - ddata->regmap = devm_regmap_init_i2c(client, &bq25703_regmap_config); + switch (ddata->type) { + case BQ25703A: + rcfg = &bq25703_regmap_config; + break; + case BQ25792: + rcfg = &bq25792_regmap_config; + break; + default: + return dev_err_probe(&client->dev, -ENODEV, "Unsupported device type\n"); + } + + ddata->regmap = devm_regmap_init_i2c(client, rcfg); if (IS_ERR(ddata->regmap)) { return dev_err_probe(&client->dev, PTR_ERR(ddata->regmap), "Failed to allocate register map\n"); @@ -73,13 +119,15 @@ static int bq257xx_probe(struct i2c_client *client) } static const struct i2c_device_id bq257xx_i2c_ids[] = { - { "bq25703a" }, + { "bq25703a", BQ25703A }, + { "bq25792", BQ25792 }, {} }; MODULE_DEVICE_TABLE(i2c, bq257xx_i2c_ids); static const struct of_device_id bq257xx_of_match[] = { - { .compatible = "ti,bq25703a" }, + { .compatible = "ti,bq25703a", .data = (void *)BQ25703A }, + { .compatible = "ti,bq25792", .data = (void *)BQ25792 }, {} }; MODULE_DEVICE_TABLE(of, bq257xx_of_match); diff --git a/include/linux/mfd/bq257xx.h b/include/linux/mfd/bq257xx.h index 1d6ddc7fb09f..4ec72eb920f2 100644 --- a/include/linux/mfd/bq257xx.h +++ b/include/linux/mfd/bq257xx.h @@ -98,7 +98,419 @@ #define BQ25703_EN_OTG_MASK BIT(12) +#define BQ25792_REG00_MIN_SYS_VOLTAGE 0x00 +#define BQ25792_REG01_CHARGE_VOLTAGE_LIMIT 0x01 +#define BQ25792_REG03_CHARGE_CURRENT_LIMIT 0x03 +#define BQ25792_REG05_INPUT_VOLTAGE_LIMIT 0x05 +#define BQ25792_REG06_INPUT_CURRENT_LIMIT 0x06 +#define BQ25792_REG08_PRECHARGE_CONTROL 0x08 +#define BQ25792_REG09_TERMINATION_CONTROL 0x09 +#define BQ25792_REG0A_RECHARGE_CONTROL 0x0a +#define BQ25792_REG0B_VOTG_REGULATION 0x0b +#define BQ25792_REG0D_IOTG_REGULATION 0x0d +#define BQ25792_REG0E_TIMER_CONTROL 0x0e +#define BQ25792_REG0F_CHARGER_CONTROL_0 0x0f +#define BQ25792_REG10_CHARGER_CONTROL_1 0x10 +#define BQ25792_REG11_CHARGER_CONTROL_2 0x11 +#define BQ25792_REG12_CHARGER_CONTROL_3 0x12 +#define BQ25792_REG13_CHARGER_CONTROL_4 0x13 +#define BQ25792_REG14_CHARGER_CONTROL_5 0x14 +/* REG15 reserved */ +#define BQ25792_REG16_TEMPERATURE_CONTROL 0x16 +#define BQ25792_REG17_NTC_CONTROL_0 0x17 +#define BQ25792_REG18_NTC_CONTROL_1 0x18 +#define BQ25792_REG19_ICO_CURRENT_LIMIT 0x19 +#define BQ25792_REG1B_CHARGER_STATUS_0 0x1b +#define BQ25792_REG1C_CHARGER_STATUS_1 0x1c +#define BQ25792_REG1D_CHARGER_STATUS_2 0x1d +#define BQ25792_REG1E_CHARGER_STATUS_3 0x1e +#define BQ25792_REG1F_CHARGER_STATUS_4 0x1f +#define BQ25792_REG20_FAULT_STATUS_0 0x20 +#define BQ25792_REG21_FAULT_STATUS_1 0x21 +#define BQ25792_REG22_CHARGER_FLAG_0 0x22 +#define BQ25792_REG23_CHARGER_FLAG_1 0x23 +#define BQ25792_REG24_CHARGER_FLAG_2 0x24 +#define BQ25792_REG25_CHARGER_FLAG_3 0x25 +#define BQ25792_REG26_FAULT_FLAG_0 0x26 +#define BQ25792_REG27_FAULT_FLAG_1 0x27 +#define BQ25792_REG28_CHARGER_MASK_0 0x28 +#define BQ25792_REG29_CHARGER_MASK_1 0x29 +#define BQ25792_REG2A_CHARGER_MASK_2 0x2a +#define BQ25792_REG2B_CHARGER_MASK_3 0x2b +#define BQ25792_REG2C_FAULT_MASK_0 0x2c +#define BQ25792_REG2D_FAULT_MASK_1 0x2d +#define BQ25792_REG2E_ADC_CONTROL 0x2e +#define BQ25792_REG2F_ADC_FUNCTION_DISABLE_0 0x2f +#define BQ25792_REG30_ADC_FUNCTION_DISABLE_1 0x30 +#define BQ25792_REG31_IBUS_ADC 0x31 +#define BQ25792_REG33_IBAT_ADC 0x33 +#define BQ25792_REG35_VBUS_ADC 0x35 +#define BQ25792_REG37_VAC1_ADC 0x37 +#define BQ25792_REG39_VAC2_ADC 0x39 +#define BQ25792_REG3B_VBAT_ADC 0x3b +#define BQ25792_REG3D_VSYS_ADC 0x3d +#define BQ25792_REG3F_TS_ADC 0x3f +#define BQ25792_REG41_TDIE_ADC 0x41 +#define BQ25792_REG43_DP_ADC 0x43 +#define BQ25792_REG45_DM_ADC 0x45 +#define BQ25792_REG47_DPDM_DRIVER 0x47 +#define BQ25792_REG48_PART_INFORMATION 0x48 + +/* Minimal System Voltage */ +#define BQ25792_REG00_VSYSMIN_MASK GENMASK(5, 0) + +#define BQ25792_MINVSYS_MIN_UV 2500000 +#define BQ25792_MINVSYS_STEP_UV 250000 +#define BQ25792_MINVSYS_MAX_UV 16000000 + +/* Charge Voltage Limit */ +#define BQ25792_REG01_VREG_MASK GENMASK(10, 0) + +#define BQ25792_VBATREG_MIN_UV 3000000 +#define BQ25792_VBATREG_STEP_UV 10000 +#define BQ25792_VBATREG_MAX_UV 18800000 + +/* Charge Current Limit */ +#define BQ25792_REG03_ICHG_MASK GENMASK(8, 0) + +#define BQ25792_ICHG_MIN_UA 50000 +#define BQ25792_ICHG_STEP_UA 10000 +#define BQ25792_ICHG_MAX_UA 5000000 + +/* Input Voltage Limit */ +#define BQ25792_REG05_VINDPM_MASK GENMASK(7, 0) + +/* Input Current Limit */ +#define BQ25792_REG06_IINDPM_MASK GENMASK(8, 0) +#define BQ25792_IINDPM_DEFAULT_UA 3000000 +#define BQ25792_IINDPM_STEP_UA 10000 +#define BQ25792_IINDPM_MIN_UA 100000 +#define BQ25792_IINDPM_MAX_UA 3300000 + +/* Precharge Control */ +#define BQ25792_REG08_VBAT_LOWV_MASK GENMASK(7, 6) +#define BQ25792_REG08_IPRECHG_MASK GENMASK(5, 0) + +/* Termination Control */ +#define BQ25792_REG09_REG_RST BIT(6) +#define BQ25792_REG09_ITERM_MASK GENMASK(4, 0) + +/* Re-charge Control */ +#define BQ25792_REG0A_CELL_MASK GENMASK(7, 6) +#define BQ25792_REG0A_TRECHG_MASK GENMASK(5, 4) +#define BQ25792_REG0A_VRECHG_MASK GENMASK(3, 0) + +/* VOTG regulation */ +#define BQ25792_REG0B_VOTG_MASK GENMASK(10, 0) + +#define BQ25792_OTG_VOLT_MIN_UV 2800000 +#define BQ25792_OTG_VOLT_STEP_UV 10000 +#define BQ25792_OTG_VOLT_MAX_UV 22000000 +#define BQ25792_OTG_VOLT_NUM_VOLT ((BQ25792_OTG_VOLT_MAX_UV \ + - BQ25792_OTG_VOLT_MIN_UV) \ + / BQ25792_OTG_VOLT_STEP_UV + 1) + +/* IOTG regulation */ +#define BQ25792_REG0D_PRECHG_TMR BIT(7) +#define BQ25792_REG0D_IOTG_MASK GENMASK(6, 0) + +#define BQ25792_OTG_CUR_MIN_UA 120000 +#define BQ25792_OTG_CUR_STEP_UA 40000 +#define BQ25792_OTG_CUR_MAX_UA 3320000 + +/* Timer Control */ +#define BQ25792_REG0E_TOPOFF_TMR_MASK GENMASK(7, 6) +#define BQ25792_REG0E_EN_TRICHG_TMR BIT(5) +#define BQ25792_REG0E_EN_PRECHG_TMR BIT(4) +#define BQ25792_REG0E_EN_CHG_TMR BIT(3) +#define BQ25792_REG0E_CHG_TMR_MASK GENMASK(2, 1) +#define BQ25792_REG0E_TMR2X_EN BIT(0) + +/* Charger Control 0 */ +#define BQ25792_REG0F_EN_AUTO_IBATDIS BIT(7) +#define BQ25792_REG0F_FORCE_IBATDIS BIT(6) +#define BQ25792_REG0F_EN_CHG BIT(5) +#define BQ25792_REG0F_EN_ICO BIT(4) +#define BQ25792_REG0F_FORCE_ICO BIT(3) +#define BQ25792_REG0F_EN_HIZ BIT(2) +#define BQ25792_REG0F_EN_TERM BIT(1) +/* bit0 reserved */ + +/* Charger Control 1 */ +#define BQ25792_REG10_VAC_OVP_MASK GENMASK(5, 4) +#define BQ25792_REG10_WD_RST BIT(3) +#define BQ25792_REG10_WATCHDOG_MASK GENMASK(2, 0) + +/* Charger Control 2 */ +#define BQ25792_REG11_FORCE_INDET BIT(7) +#define BQ25792_REG11_AUTO_INDET_EN BIT(6) +#define BQ25792_REG11_EN_12V BIT(5) +#define BQ25792_REG11_EN_9V BIT(4) +#define BQ25792_REG11_HVDCP_EN BIT(3) +#define BQ25792_REG11_SDRV_CTRL_MASK GENMASK(2, 1) +#define BQ25792_REG11_SDRV_DLY BIT(0) + +/* Charger Control 3 */ +#define BQ25792_REG12_DIS_ACDRV BIT(7) +#define BQ25792_REG12_EN_OTG BIT(6) +#define BQ25792_REG12_PFM_OTG_DIS BIT(5) +#define BQ25792_REG12_PFM_FWD_DIS BIT(4) +#define BQ25792_REG12_WKUP_DLY BIT(3) +#define BQ25792_REG12_DIS_LDO BIT(2) +#define BQ25792_REG12_DIS_OTG_OOA BIT(1) +#define BQ25792_REG12_DIS_FWD_OOA BIT(0) + +/* Charger Control 4 */ +#define BQ25792_REG13_EN_ACDRV2 BIT(7) +#define BQ25792_REG13_EN_ACDRV1 BIT(6) +#define BQ25792_REG13_PWM_FREQ BIT(5) +#define BQ25792_REG13_DIS_STAT BIT(4) +#define BQ25792_REG13_DIS_VSYS_SHORT BIT(3) +#define BQ25792_REG13_DIS_VOTG_UVP BIT(2) +#define BQ25792_REG13_FORCE_VINDPM_DET BIT(1) +#define BQ25792_REG13_EN_IBUS_OCP BIT(0) + +/* Charger Control 5 */ +#define BQ25792_REG14_SFET_PRESENT BIT(7) +/* bit6 reserved */ +#define BQ25792_REG14_EN_IBAT BIT(5) +#define BQ25792_REG14_IBAT_REG_MASK GENMASK(4, 3) +#define BQ25792_REG14_EN_IINDPM BIT(2) +#define BQ25792_REG14_EN_EXTILIM BIT(1) +#define BQ25792_REG14_EN_BATOC BIT(0) + +#define BQ25792_IBAT_3A FIELD_PREP(BQ25792_REG14_IBAT_REG_MASK, 0) +#define BQ25792_IBAT_4A FIELD_PREP(BQ25792_REG14_IBAT_REG_MASK, 1) +#define BQ25792_IBAT_5A FIELD_PREP(BQ25792_REG14_IBAT_REG_MASK, 2) +#define BQ25792_IBAT_UNLIM FIELD_PREP(BQ25792_REG14_IBAT_REG_MASK, 3) + +/* Temperature Control */ +#define BQ25792_REG16_TREG_MASK GENMASK(7, 6) +#define BQ25792_REG16_TSHUT_MASK GENMASK(5, 4) +#define BQ25792_REG16_VBUS_PD_EN BIT(3) +#define BQ25792_REG16_VAC1_PD_EN BIT(2) +#define BQ25792_REG16_VAC2_PD_EN BIT(1) + +/* NTC Control 0 */ +#define BQ25792_REG17_JEITA_VSET_MASK GENMASK(7, 5) +#define BQ25792_REG17_JEITA_ISETH_MASK GENMASK(4, 3) +#define BQ25792_REG17_JEITA_ISETC_MASK GENMASK(2, 1) + +/* NTC Control 1 */ +#define BQ25792_REG18_TS_COOL_MASK GENMASK(7, 6) +#define BQ25792_REG18_TS_WARM_MASK GENMASK(5, 4) +#define BQ25792_REG18_BHOT_MASK GENMASK(3, 2) +#define BQ25792_REG18_BCOLD BIT(1) +#define BQ25792_REG18_TS_IGNORE BIT(0) + +/* ICO Current Limit */ +#define BQ25792_REG19_ICO_ILIM_MASK GENMASK(8, 0) + +/* Charger Status 0 */ +#define BQ25792_REG1B_IINDPM_STAT BIT(7) +#define BQ25792_REG1B_VINDPM_STAT BIT(6) +#define BQ25792_REG1B_WD_STAT BIT(5) +#define BQ25792_REG1B_POORSRC_STAT BIT(4) +#define BQ25792_REG1B_PG_STAT BIT(3) +#define BQ25792_REG1B_AC2_PRESENT_STAT BIT(2) +#define BQ25792_REG1B_AC1_PRESENT_STAT BIT(1) +#define BQ25792_REG1B_VBUS_PRESENT_STAT BIT(0) + +/* Charger Status 1 */ +#define BQ25792_REG1C_CHG_STAT_MASK GENMASK(7, 5) +#define BQ25792_REG1C_VBUS_STAT_MASK GENMASK(4, 1) +#define BQ25792_REG1C_BC12_DONE_STAT BIT(0) + +/* Charger Status 2 */ +#define BQ25792_REG1D_ICO_STAT_MASK GENMASK(7, 6) +#define BQ25792_REG1D_TREG_STAT BIT(2) +#define BQ25792_REG1D_DPDM_STAT BIT(1) +#define BQ25792_REG1D_VBAT_PRESENT_STAT BIT(0) + +/* Charger Status 3 */ +#define BQ25792_REG1E_ACRB2_STAT BIT(7) +#define BQ25792_REG1E_ACRB1_STAT BIT(6) +#define BQ25792_REG1E_ADC_DONE_STAT BIT(5) +#define BQ25792_REG1E_VSYS_STAT BIT(4) +#define BQ25792_REG1E_CHG_TMR_STAT BIT(3) +#define BQ25792_REG1E_TRICHG_TMR_STAT BIT(2) +#define BQ25792_REG1E_PRECHG_TMR_STAT BIT(1) + +/* Charger Status 4 */ +#define BQ25792_REG1F_VBATOTG_LOW_STAT BIT(4) +#define BQ25792_REG1F_TS_COLD_STAT BIT(3) +#define BQ25792_REG1F_TS_COOL_STAT BIT(2) +#define BQ25792_REG1F_TS_WARM_STAT BIT(1) +#define BQ25792_REG1F_TS_HOT_STAT BIT(0) + +/* FAULT Status 0 */ +#define BQ25792_REG20_IBAT_REG_STAT BIT(7) +#define BQ25792_REG20_VBUS_OVP_STAT BIT(6) +#define BQ25792_REG20_VBAT_OVP_STAT BIT(5) +#define BQ25792_REG20_IBUS_OCP_STAT BIT(4) +#define BQ25792_REG20_IBAT_OCP_STAT BIT(3) +#define BQ25792_REG20_CONV_OCP_STAT BIT(2) +#define BQ25792_REG20_VAC2_OVP_STAT BIT(1) +#define BQ25792_REG20_VAC1_OVP_STAT BIT(0) + +#define BQ25792_REG20_OVERVOLTAGE_MASK (BQ25792_REG20_VBAT_OVP_STAT | \ + BQ25792_REG20_VAC2_OVP_STAT | \ + BQ25792_REG20_VAC1_OVP_STAT) +#define BQ25792_REG20_OVERCURRENT_MASK (BQ25792_REG20_IBAT_OCP_STAT | \ + BQ25792_REG20_CONV_OCP_STAT) + +/* FAULT Status 1 */ +#define BQ25792_REG21_VSYS_SHORT_STAT BIT(7) +#define BQ25792_REG21_VSYS_OVP_STAT BIT(6) +#define BQ25792_REG21_OTG_OVP_STAT BIT(5) +#define BQ25792_REG21_OTG_UVP_STAT BIT(4) +#define BQ25792_REG21_TSHUT_STAT BIT(2) + + +/* Charger Flag 0 */ +#define BQ25792_REG22_IINDPM_FLAG BIT(7) +#define BQ25792_REG22_VINDPM_FLAG BIT(6) +#define BQ25792_REG22_WD_FLAG BIT(5) +#define BQ25792_REG22_POORSRC_FLAG BIT(4) +#define BQ25792_REG22_PG_FLAG BIT(3) +#define BQ25792_REG22_AC2_PRESENT_FLAG BIT(2) +#define BQ25792_REG22_AC1_PRESENT_FLAG BIT(1) +#define BQ25792_REG22_VBUS_PRESENT_FLAG BIT(0) + +/* Charger Flag 1 */ +#define BQ25792_REG23_CHG_FLAG BIT(7) +#define BQ25792_REG23_ICO_FLAG BIT(6) +#define BQ25792_REG23_VBUS_FLAG BIT(4) +#define BQ25792_REG23_TREG_FLAG BIT(2) +#define BQ25792_REG23_VBAT_PRESENT_FLAG BIT(1) +#define BQ25792_REG23_BC12_DONE_FLAG BIT(0) + +/* Charger Flag 2 */ +#define BQ25792_REG24_DPDM_DONE_FLAG BIT(6) +#define BQ25792_REG24_ADC_DONE_FLAG BIT(5) +#define BQ25792_REG24_VSYS_FLAG BIT(4) +#define BQ25792_REG24_CHG_TMR_FLAG BIT(3) +#define BQ25792_REG24_TRICHG_TMR_FLAG BIT(2) +#define BQ25792_REG24_PRECHG_TMR_FLAG BIT(1) +#define BQ25792_REG24_TOPOFF_TMR_FLAG BIT(0) + +/* Charger Flag 3 */ +#define BQ25792_REG25_VBATOTG_LOW_FLAG BIT(4) +#define BQ25792_REG25_TS_COLD_FLAG BIT(3) +#define BQ25792_REG25_TS_COOL_FLAG BIT(2) +#define BQ25792_REG25_TS_WARM_FLAG BIT(1) +#define BQ25792_REG25_TS_HOT_FLAG BIT(0) + +/* FAULT Flag 0 */ +#define BQ25792_REG26_IBAT_REG_FLAG BIT(7) +#define BQ25792_REG26_VBUS_OVP_FLAG BIT(6) +#define BQ25792_REG26_VBAT_OVP_FLAG BIT(5) +#define BQ25792_REG26_IBUS_OCP_FLAG BIT(4) +#define BQ25792_REG26_IBAT_OCP_FLAG BIT(3) +#define BQ25792_REG26_CONV_OCP_FLAG BIT(2) +#define BQ25792_REG26_VAC2_OVP_FLAG BIT(1) +#define BQ25792_REG26_VAC1_OVP_FLAG BIT(0) + +/* FAULT Flag 1 */ +#define BQ25792_REG27_VSYS_SHORT_FLAG BIT(7) +#define BQ25792_REG27_VSYS_OVP_FLAG BIT(6) +#define BQ25792_REG27_OTG_OVP_FLAG BIT(5) +#define BQ25792_REG27_OTG_UVP_FLAG BIT(4) +#define BQ25792_REG27_TSHUT_FLAG BIT(2) + +/* Charger Mask 0 */ +#define BQ25792_REG28_IINDPM_MASK BIT(7) +#define BQ25792_REG28_VINDPM_MASK BIT(6) +#define BQ25792_REG28_WD_MASK BIT(5) +#define BQ25792_REG28_POORSRC_MASK BIT(4) +#define BQ25792_REG28_PG_MASK BIT(3) +#define BQ25792_REG28_AC2_PRESENT_MASK BIT(2) +#define BQ25792_REG28_AC1_PRESENT_MASK BIT(1) +#define BQ25792_REG28_VBUS_PRESENT_MASK BIT(0) + +/* Charger Mask 1 */ +#define BQ25792_REG29_CHG_MASK BIT(7) +#define BQ25792_REG29_ICO_MASK BIT(6) +#define BQ25792_REG29_VBUS_MASK BIT(4) +#define BQ25792_REG29_TREG_MASK BIT(2) +#define BQ25792_REG29_VBAT_PRESENT_MASK BIT(1) +#define BQ25792_REG29_BC12_DONE_MASK BIT(0) + +/* Charger Mask 2 */ +#define BQ25792_REG2A_DPDM_DONE_MASK BIT(6) +#define BQ25792_REG2A_ADC_DONE_MASK BIT(5) +#define BQ25792_REG2A_VSYS_MASK BIT(4) +#define BQ25792_REG2A_CHG_TMR_MASK BIT(3) +#define BQ25792_REG2A_TRICHG_TMR_MASK BIT(2) +#define BQ25792_REG2A_PRECHG_TMR_MASK BIT(1) +#define BQ25792_REG2A_TOPOFF_TMR_MASK BIT(0) + +/* Charger Mask 3 */ +#define BQ25792_REG2B_VBATOTG_LOW_MASK BIT(4) +#define BQ25792_REG2B_TS_COLD_MASK BIT(3) +#define BQ25792_REG2B_TS_COOL_MASK BIT(2) +#define BQ25792_REG2B_TS_WARM_MASK BIT(1) +#define BQ25792_REG2B_TS_HOT_MASK BIT(0) + +/* FAULT Mask 0 */ +#define BQ25792_REG2C_IBAT_REG_MASK BIT(7) +#define BQ25792_REG2C_VBUS_OVP_MASK BIT(6) +#define BQ25792_REG2C_VBAT_OVP_MASK BIT(5) +#define BQ25792_REG2C_IBUS_OCP_MASK BIT(4) +#define BQ25792_REG2C_IBAT_OCP_MASK BIT(3) +#define BQ25792_REG2C_CONV_OCP_MASK BIT(2) +#define BQ25792_REG2C_VAC2_OVP_MASK BIT(1) +#define BQ25792_REG2C_VAC1_OVP_MASK BIT(0) + +/* FAULT Mask 1 */ +#define BQ25792_REG2D_VSYS_SHORT_MASK BIT(7) +#define BQ25792_REG2D_VSYS_OVP_MASK BIT(6) +#define BQ25792_REG2D_OTG_OVP_MASK BIT(5) +#define BQ25792_REG2D_OTG_UVP_MASK BIT(4) +#define BQ25792_REG2D_TSHUT_MASK BIT(2) + +/* ADC Control */ +#define BQ25792_REG2E_ADC_EN BIT(7) +#define BQ25792_REG2E_ADC_RATE BIT(6) +#define BQ25792_REG2E_ADC_SAMPLE_MASK GENMASK(5, 4) +#define BQ25792_REG2E_ADC_AVG BIT(3) +#define BQ25792_REG2E_ADC_AVG_INIT BIT(2) + +/* ADC Function Disable 0 */ +#define BQ25792_REG2F_IBUS_ADC_DIS BIT(7) +#define BQ25792_REG2F_IBAT_ADC_DIS BIT(6) +#define BQ25792_REG2F_VBUS_ADC_DIS BIT(5) +#define BQ25792_REG2F_VBAT_ADC_DIS BIT(4) +#define BQ25792_REG2F_VSYS_ADC_DIS BIT(3) +#define BQ25792_REG2F_TS_ADC_DIS BIT(2) +#define BQ25792_REG2F_TDIE_ADC_DIS BIT(1) + +/* ADC Function Disable 1 */ +#define BQ25792_REG30_DP_ADC_DIS BIT(7) +#define BQ25792_REG30_DM_ADC_DIS BIT(6) +#define BQ25792_REG30_VAC2_ADC_DIS BIT(5) +#define BQ25792_REG30_VAC1_ADC_DIS BIT(4) + +/* 0x31-0x45: ADC result registers (16-bit, RO): single full-width field */ + +#define BQ25792_ADCVSYSVBAT_STEP_UV 1000 +#define BQ25792_ADCIBAT_STEP_UA 1000 + +/* DPDM Driver */ +#define BQ25792_REG47_DPLUS_DAC_MASK GENMASK(7, 5) +#define BQ25792_REG47_DMINUS_DAC_MASK GENMASK(4, 2) + +/* Part Information */ +#define BQ25792_REG48_PN_MASK GENMASK(5, 3) +#define BQ25792_REG48_DEV_REV_MASK GENMASK(2, 0) + +enum bq257xx_type { + BQ25703A = 1, + BQ25792, +}; + struct bq257xx_device { struct i2c_client *client; struct regmap *regmap; + enum bq257xx_type type; }; -- cgit v1.2.3 From 4b51f0da731adb1d3468518dc2deb5dae83978b7 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Wed, 29 Apr 2026 14:23:30 +0200 Subject: mfd: cs5535: Add, assign and expose the software node for the GPIO cell There are board files in-tree that want to request GPIOs from this chip. They currently rely on the GPIO core's mechanism of matching software nodes' labels against GPIO controller names. We want to remove this behavior from the kernel and to this end, we need to associate the referenced GPIO controller with its target software node. Create a dedicated GPIO software node for cs5535, assign it to the GPIO cell and expose its address in a new header. We only expose a single software node instance but that's alright: all existing hardware only contains a single cs5535 companion and the geode board file for which we expose this is legacy anyway. Signed-off-by: Bartosz Golaszewski Link: https://patch.msgid.link/20260429-cs5535-swnode-v1-1-2bc5e17ddcf9@oss.qualcomm.com Signed-off-by: Lee Jones --- drivers/mfd/cs5535-mfd.c | 9 +++++++++ include/linux/mfd/cs5535.h | 8 ++++++++ 2 files changed, 17 insertions(+) create mode 100644 include/linux/mfd/cs5535.h (limited to 'include/linux') diff --git a/drivers/mfd/cs5535-mfd.c b/drivers/mfd/cs5535-mfd.c index d0fb2e52ee76..f3becbef19f5 100644 --- a/drivers/mfd/cs5535-mfd.c +++ b/drivers/mfd/cs5535-mfd.c @@ -12,8 +12,11 @@ #include #include +#include #include #include +#include + #include #define DRV_NAME "cs5535-mfd" @@ -29,6 +32,11 @@ enum cs5535_mfd_bars { static struct resource cs5535_mfd_resources[NR_BARS]; +const struct software_node cs5535_gpio_swnode = { + .name = "cs5535-gpio", +}; +EXPORT_SYMBOL_NS(cs5535_gpio_swnode, "CS5535"); + static struct mfd_cell cs5535_mfd_cells[] = { { .name = "cs5535-smb", @@ -39,6 +47,7 @@ static struct mfd_cell cs5535_mfd_cells[] = { .name = "cs5535-gpio", .num_resources = 1, .resources = &cs5535_mfd_resources[GPIO_BAR], + .swnode = &cs5535_gpio_swnode, }, { .name = "cs5535-mfgpt", diff --git a/include/linux/mfd/cs5535.h b/include/linux/mfd/cs5535.h new file mode 100644 index 000000000000..2e4ebf5d06af --- /dev/null +++ b/include/linux/mfd/cs5535.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MFD_CS5535_H__ +#define __MFD_CS5535_H__ + +extern const struct software_node cs5535_gpio_swnode; + +#endif /* __MFD_CS5535_H__ */ -- cgit v1.2.3 From 5618127fed7e8f974b3615d429ffdea670b203be Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 27 Apr 2026 16:34:27 +0200 Subject: mfd: wm8994: Remove dead legacy-gpio code The old-style gpio handling in wm8994 came from a commit 7c8844481a1c ("mfd: wm8994: Emulate level triggered interrupts if required") in linux-3.11, but nothing in the kernel ever set the 'irq_gpio' member in the wm8994_pdata structure, so this was always dead code. Remove it now to reduce the dependency on the legacy gpio interfaces. Signed-off-by: Arnd Bergmann Reviewed-by: Bartosz Golaszewski Reviewed-by: Charles Keepax Reviewed-by: Linus Walleij Link: https://patch.msgid.link/20260427143437.3059210-1-arnd@kernel.org Signed-off-by: Lee Jones --- drivers/mfd/wm8994-irq.c | 94 ++-------------------------------------- include/linux/mfd/wm8994/pdata.h | 5 --- 2 files changed, 4 insertions(+), 95 deletions(-) (limited to 'include/linux') diff --git a/drivers/mfd/wm8994-irq.c b/drivers/mfd/wm8994-irq.c index 1475b1ac6983..a46cea948763 100644 --- a/drivers/mfd/wm8994-irq.c +++ b/drivers/mfd/wm8994-irq.c @@ -135,53 +135,9 @@ static const struct regmap_irq_chip wm8994_irq_chip = { .runtime_pm = true, }; -static void wm8994_edge_irq_enable(struct irq_data *data) -{ -} - -static void wm8994_edge_irq_disable(struct irq_data *data) -{ -} - -static struct irq_chip wm8994_edge_irq_chip = { - .name = "wm8994_edge", - .irq_disable = wm8994_edge_irq_disable, - .irq_enable = wm8994_edge_irq_enable, -}; - -static irqreturn_t wm8994_edge_irq(int irq, void *data) -{ - struct wm8994 *wm8994 = data; - - while (gpio_get_value_cansleep(wm8994->pdata.irq_gpio)) - handle_nested_irq(irq_find_mapping(wm8994->edge_irq, 0)); - - return IRQ_HANDLED; -} - -static int wm8994_edge_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct wm8994 *wm8994 = h->host_data; - - irq_set_chip_data(virq, wm8994); - irq_set_chip_and_handler(virq, &wm8994_edge_irq_chip, handle_edge_irq); - irq_set_nested_thread(virq, 1); - irq_set_noprobe(virq); - - return 0; -} - -static const struct irq_domain_ops wm8994_edge_irq_ops = { - .map = wm8994_edge_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - int wm8994_irq_init(struct wm8994 *wm8994) { int ret; - unsigned long irqflags; - struct wm8994_pdata *pdata = &wm8994->pdata; if (!wm8994->irq) { dev_warn(wm8994->dev, @@ -190,53 +146,11 @@ int wm8994_irq_init(struct wm8994 *wm8994) return 0; } - /* select user or default irq flags */ - irqflags = IRQF_TRIGGER_HIGH | IRQF_ONESHOT; - if (pdata->irq_flags) - irqflags = pdata->irq_flags; - /* use a GPIO for edge triggered controllers */ - if (irqflags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { - if (gpio_to_irq(pdata->irq_gpio) != wm8994->irq) { - dev_warn(wm8994->dev, "IRQ %d is not GPIO %d (%d)\n", - wm8994->irq, pdata->irq_gpio, - gpio_to_irq(pdata->irq_gpio)); - wm8994->irq = gpio_to_irq(pdata->irq_gpio); - } - - ret = devm_gpio_request_one(wm8994->dev, pdata->irq_gpio, - GPIOF_IN, "WM8994 IRQ"); - - if (ret != 0) { - dev_err(wm8994->dev, "Failed to get IRQ GPIO: %d\n", - ret); - return ret; - } - - wm8994->edge_irq = irq_domain_create_linear(NULL, 1, &wm8994_edge_irq_ops, wm8994); - - ret = regmap_add_irq_chip(wm8994->regmap, - irq_create_mapping(wm8994->edge_irq, - 0), - IRQF_ONESHOT, - wm8994->irq_base, &wm8994_irq_chip, - &wm8994->irq_data); - if (ret != 0) { - dev_err(wm8994->dev, "Failed to get IRQ: %d\n", - ret); - return ret; - } - - ret = request_threaded_irq(wm8994->irq, - NULL, wm8994_edge_irq, - irqflags, - "WM8994 edge", wm8994); - } else { - ret = regmap_add_irq_chip(wm8994->regmap, wm8994->irq, - irqflags, - wm8994->irq_base, &wm8994_irq_chip, - &wm8994->irq_data); - } + ret = regmap_add_irq_chip(wm8994->regmap, wm8994->irq, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, + wm8994->irq_base, &wm8994_irq_chip, + &wm8994->irq_data); if (ret != 0) { dev_err(wm8994->dev, "Failed to register IRQ chip: %d\n", ret); diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h index 6e2962ef5b81..b95a56a338c3 100644 --- a/include/linux/mfd/wm8994/pdata.h +++ b/include/linux/mfd/wm8994/pdata.h @@ -226,11 +226,6 @@ struct wm8994_pdata { * lines is mastered. */ int max_channels_clocked[WM8994_NUM_AIF]; - - /** - * GPIO for the IRQ pin if host only supports edge triggering - */ - int irq_gpio; }; #endif -- cgit v1.2.3 From 7b7b7fa42d08087a9d5f3d49453dbe721cbbd2d4 Mon Sep 17 00:00:00 2001 From: Amit Sunil Dhamne Date: Mon, 4 May 2026 22:49:54 +0000 Subject: mfd: max77759: Improve static struct formatting and commentary Improve code style. This includes the following: - Formatting the max77759_chgr_irqs entries to fit in a single line instead of breaking them into multiple lines to improve readability. - Refactoring comments such that they're full sentences and have punctuation marks for a couple of macro definitions to adhere to the documentation style. - Explicitly initializing `MAX77759_CHGR_MODE_OFF`. Signed-off-by: Amit Sunil Dhamne Link: https://patch.msgid.link/20260504-fix-mfd-max77759-driver-v1-1-4d4a31a1d214@google.com Signed-off-by: Lee Jones --- drivers/mfd/max77759.c | 48 +++++++++++++++----------------------------- include/linux/mfd/max77759.h | 6 +++--- 2 files changed, 19 insertions(+), 35 deletions(-) (limited to 'include/linux') diff --git a/drivers/mfd/max77759.c b/drivers/mfd/max77759.c index 9fa6027a92c4..b50433e7b3d3 100644 --- a/drivers/mfd/max77759.c +++ b/drivers/mfd/max77759.c @@ -286,38 +286,22 @@ static const struct regmap_irq max77759_topsys_irqs[] = { }; static const struct regmap_irq max77759_chgr_irqs[] = { - REGMAP_IRQ_REG(MAX77759_CHGR_INT1_AICL, 0, - MAX77759_CHGR_REG_CHG_INT_AICL), - REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHGIN, 0, - MAX77759_CHGR_REG_CHG_INT_CHGIN), - REGMAP_IRQ_REG(MAX77759_CHGR_INT1_WCIN, 0, - MAX77759_CHGR_REG_CHG_INT_WCIN), - REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHG, 0, - MAX77759_CHGR_REG_CHG_INT_CHG), - REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BAT, 0, - MAX77759_CHGR_REG_CHG_INT_BAT), - REGMAP_IRQ_REG(MAX77759_CHGR_INT1_INLIM, 0, - MAX77759_CHGR_REG_CHG_INT_INLIM), - REGMAP_IRQ_REG(MAX77759_CHGR_INT1_THM2, 0, - MAX77759_CHGR_REG_CHG_INT_THM2), - REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BYP, 0, - MAX77759_CHGR_REG_CHG_INT_BYP), - REGMAP_IRQ_REG(MAX77759_CHGR_INT2_INSEL, 1, - MAX77759_CHGR_REG_CHG_INT2_INSEL), - REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO1, 1, - MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO1), - REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO2, 1, - MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO2), - REGMAP_IRQ_REG(MAX77759_CHGR_INT2_BAT_OILO, 1, - MAX77759_CHGR_REG_CHG_INT2_BAT_OILO), - REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CC, 1, - MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CC), - REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CV, 1, - MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CV), - REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_TO, 1, - MAX77759_CHGR_REG_CHG_INT2_CHG_STA_TO), - REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_DONE, 1, - MAX77759_CHGR_REG_CHG_INT2_CHG_STA_DONE), + REGMAP_IRQ_REG(MAX77759_CHGR_INT1_AICL, 0, MAX77759_CHGR_REG_CHG_INT_AICL), + REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHGIN, 0, MAX77759_CHGR_REG_CHG_INT_CHGIN), + REGMAP_IRQ_REG(MAX77759_CHGR_INT1_WCIN, 0, MAX77759_CHGR_REG_CHG_INT_WCIN), + REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHG, 0, MAX77759_CHGR_REG_CHG_INT_CHG), + REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BAT, 0, MAX77759_CHGR_REG_CHG_INT_BAT), + REGMAP_IRQ_REG(MAX77759_CHGR_INT1_INLIM, 0, MAX77759_CHGR_REG_CHG_INT_INLIM), + REGMAP_IRQ_REG(MAX77759_CHGR_INT1_THM2, 0, MAX77759_CHGR_REG_CHG_INT_THM2), + REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BYP, 0, MAX77759_CHGR_REG_CHG_INT_BYP), + REGMAP_IRQ_REG(MAX77759_CHGR_INT2_INSEL, 1, MAX77759_CHGR_REG_CHG_INT2_INSEL), + REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO1, 1, MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO1), + REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO2, 1, MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO2), + REGMAP_IRQ_REG(MAX77759_CHGR_INT2_BAT_OILO, 1, MAX77759_CHGR_REG_CHG_INT2_BAT_OILO), + REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CC, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CC), + REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CV, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CV), + REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_TO, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_TO), + REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_DONE, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_DONE), }; static const struct regmap_irq_chip max77759_pmic_irq_chip = { diff --git a/include/linux/mfd/max77759.h b/include/linux/mfd/max77759.h index ec19be952877..7c0b13219d51 100644 --- a/include/linux/mfd/max77759.h +++ b/include/linux/mfd/max77759.h @@ -106,9 +106,9 @@ #define MAX77759_CHGR_REG_CHG_CNFG_10 0xc3 #define MAX77759_CHGR_REG_CHG_CNFG_11 0xc4 #define MAX77759_CHGR_REG_CHG_CNFG_12 0xc5 -/* Wireless Charging input channel select */ +/* Setting this enables the Wireless Charging input channel. */ #define MAX77759_CHGR_REG_CHG_CNFG_12_WCINSEL BIT(6) -/* CHGIN/USB input channel select */ +/* Setting this enables the CHGIN/USB input channel. */ #define MAX77759_CHGR_REG_CHG_CNFG_12_CHGINSEL BIT(5) #define MAX77759_CHGR_REG_CHG_CNFG_13 0xc6 #define MAX77759_CHGR_REG_CHG_CNFG_14 0xc7 @@ -204,7 +204,7 @@ enum max77759_chgr_chg_dtls_states { }; enum max77759_chgr_mode { - MAX77759_CHGR_MODE_OFF, + MAX77759_CHGR_MODE_OFF = 0x0, MAX77759_CHGR_MODE_CHG_BUCK_ON = 0x5, MAX77759_CHGR_MODE_OTG_BOOST_ON = 0xA, }; -- cgit v1.2.3 From e6f0018fbf1f4eabd3fb8ac71f06cb31efce3c86 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 30 Apr 2026 18:28:05 +0200 Subject: mfd: ezx-pcap: Remove unused driver Support for the Motorola EZX phones based on Intel PXA processors was removed in 2022, but this driver remained present in the tree. As far as I can tell, the support was never quite functional upstream because the board files did not actually instantiate the SPI device for the PCAP. There are still also drivers for the various mfd cells: keys, touchscreen, regulator and rtc, all of which are obviously orphaned as well but can be removed separately as the Kconfig dependency now prevents them from being enabled. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202604301209.f1YXTsIr-lkp@intel.com/ Signed-off-by: Arnd Bergmann Reviewed-by: Linus Walleij Acked-by: Harald Welte Reviewed-by: Bartosz Golaszewski Link: https://patch.msgid.link/20260430162855.2029285-1-arnd@kernel.org Signed-off-by: Lee Jones --- drivers/mfd/Kconfig | 7 - drivers/mfd/Makefile | 1 - drivers/mfd/ezx-pcap.c | 491 ------------------------------------------- include/linux/mfd/ezx-pcap.h | 253 ---------------------- 4 files changed, 752 deletions(-) delete mode 100644 drivers/mfd/ezx-pcap.c delete mode 100644 include/linux/mfd/ezx-pcap.h (limited to 'include/linux') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 7192c9d1d268..d08d70d41bce 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1199,13 +1199,6 @@ config MFD_OCELOT If unsure, say N. -config EZX_PCAP - bool "Motorola EZXPCAP Support" - depends on SPI_MASTER - help - This enables the PCAP ASIC present on EZX Phones. This is - needed for MMC, TouchScreen, Sound, USB, etc.. - config MFD_CPCAP tristate "Support for Motorola CPCAP" depends on SPI diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index e75e8045c28a..dd4bb7e77c33 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -131,7 +131,6 @@ obj-$(CONFIG_MFD_CORE) += mfd-core.o ocelot-soc-objs := ocelot-core.o ocelot-spi.o obj-$(CONFIG_MFD_OCELOT) += ocelot-soc.o -obj-$(CONFIG_EZX_PCAP) += ezx-pcap.o obj-$(CONFIG_MFD_CPCAP) += motorola-cpcap.o obj-$(CONFIG_MCP) += mcp-core.o diff --git a/drivers/mfd/ezx-pcap.c b/drivers/mfd/ezx-pcap.c deleted file mode 100644 index 9a685ff8cd15..000000000000 --- a/drivers/mfd/ezx-pcap.c +++ /dev/null @@ -1,491 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Driver for Motorola PCAP2 as present in EZX phones - * - * Copyright (C) 2006 Harald Welte - * Copyright (C) 2009 Daniel Ribeiro - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define PCAP_ADC_MAXQ 8 -struct pcap_adc_request { - u8 bank; - u8 ch[2]; - u32 flags; - void (*callback)(void *, u16[]); - void *data; -}; - -struct pcap_chip { - struct spi_device *spi; - - /* IO */ - u32 buf; - spinlock_t io_lock; - - /* IRQ */ - unsigned int irq_base; - u32 msr; - struct work_struct isr_work; - struct work_struct msr_work; - struct workqueue_struct *workqueue; - - /* ADC */ - struct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ]; - u8 adc_head; - u8 adc_tail; - spinlock_t adc_lock; -}; - -/* IO */ -static int ezx_pcap_putget(struct pcap_chip *pcap, u32 *data) -{ - struct spi_transfer t; - struct spi_message m; - int status; - - memset(&t, 0, sizeof(t)); - spi_message_init(&m); - t.len = sizeof(u32); - spi_message_add_tail(&t, &m); - - pcap->buf = *data; - t.tx_buf = (u8 *) &pcap->buf; - t.rx_buf = (u8 *) &pcap->buf; - status = spi_sync(pcap->spi, &m); - - if (status == 0) - *data = pcap->buf; - - return status; -} - -int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value) -{ - unsigned long flags; - int ret; - - spin_lock_irqsave(&pcap->io_lock, flags); - value &= PCAP_REGISTER_VALUE_MASK; - value |= PCAP_REGISTER_WRITE_OP_BIT - | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); - ret = ezx_pcap_putget(pcap, &value); - spin_unlock_irqrestore(&pcap->io_lock, flags); - - return ret; -} -EXPORT_SYMBOL_GPL(ezx_pcap_write); - -int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value) -{ - unsigned long flags; - int ret; - - spin_lock_irqsave(&pcap->io_lock, flags); - *value = PCAP_REGISTER_READ_OP_BIT - | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); - - ret = ezx_pcap_putget(pcap, value); - spin_unlock_irqrestore(&pcap->io_lock, flags); - - return ret; -} -EXPORT_SYMBOL_GPL(ezx_pcap_read); - -int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val) -{ - unsigned long flags; - int ret; - u32 tmp = PCAP_REGISTER_READ_OP_BIT | - (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); - - spin_lock_irqsave(&pcap->io_lock, flags); - ret = ezx_pcap_putget(pcap, &tmp); - if (ret) - goto out_unlock; - - tmp &= (PCAP_REGISTER_VALUE_MASK & ~mask); - tmp |= (val & mask) | PCAP_REGISTER_WRITE_OP_BIT | - (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); - - ret = ezx_pcap_putget(pcap, &tmp); -out_unlock: - spin_unlock_irqrestore(&pcap->io_lock, flags); - - return ret; -} -EXPORT_SYMBOL_GPL(ezx_pcap_set_bits); - -/* IRQ */ -int irq_to_pcap(struct pcap_chip *pcap, int irq) -{ - return irq - pcap->irq_base; -} -EXPORT_SYMBOL_GPL(irq_to_pcap); - -int pcap_to_irq(struct pcap_chip *pcap, int irq) -{ - return pcap->irq_base + irq; -} -EXPORT_SYMBOL_GPL(pcap_to_irq); - -static void pcap_mask_irq(struct irq_data *d) -{ - struct pcap_chip *pcap = irq_data_get_irq_chip_data(d); - - pcap->msr |= 1 << irq_to_pcap(pcap, d->irq); - queue_work(pcap->workqueue, &pcap->msr_work); -} - -static void pcap_unmask_irq(struct irq_data *d) -{ - struct pcap_chip *pcap = irq_data_get_irq_chip_data(d); - - pcap->msr &= ~(1 << irq_to_pcap(pcap, d->irq)); - queue_work(pcap->workqueue, &pcap->msr_work); -} - -static struct irq_chip pcap_irq_chip = { - .name = "pcap", - .irq_disable = pcap_mask_irq, - .irq_mask = pcap_mask_irq, - .irq_unmask = pcap_unmask_irq, -}; - -static void pcap_msr_work(struct work_struct *work) -{ - struct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work); - - ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr); -} - -static void pcap_isr_work(struct work_struct *work) -{ - struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work); - struct pcap_platform_data *pdata = dev_get_platdata(&pcap->spi->dev); - u32 msr, isr, int_sel, service; - int irq; - - do { - ezx_pcap_read(pcap, PCAP_REG_MSR, &msr); - ezx_pcap_read(pcap, PCAP_REG_ISR, &isr); - - /* We can't service/ack irqs that are assigned to port 2 */ - if (!(pdata->config & PCAP_SECOND_PORT)) { - ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel); - isr &= ~int_sel; - } - - ezx_pcap_write(pcap, PCAP_REG_MSR, isr | msr); - ezx_pcap_write(pcap, PCAP_REG_ISR, isr); - - service = isr & ~msr; - for (irq = pcap->irq_base; service; service >>= 1, irq++) { - if (service & 1) - generic_handle_irq_safe(irq); - } - ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr); - } while (gpio_get_value(pdata->gpio)); -} - -static void pcap_irq_handler(struct irq_desc *desc) -{ - struct pcap_chip *pcap = irq_desc_get_handler_data(desc); - - desc->irq_data.chip->irq_ack(&desc->irq_data); - queue_work(pcap->workqueue, &pcap->isr_work); -} - -/* ADC */ -void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits) -{ - unsigned long flags; - u32 tmp; - - spin_lock_irqsave(&pcap->adc_lock, flags); - ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); - tmp &= ~(PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR); - tmp |= bits & (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR); - ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); - spin_unlock_irqrestore(&pcap->adc_lock, flags); -} -EXPORT_SYMBOL_GPL(pcap_set_ts_bits); - -static void pcap_disable_adc(struct pcap_chip *pcap) -{ - u32 tmp; - - ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); - tmp &= ~(PCAP_ADC_ADEN|PCAP_ADC_BATT_I_ADC|PCAP_ADC_BATT_I_POLARITY); - ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); -} - -static void pcap_adc_trigger(struct pcap_chip *pcap) -{ - unsigned long flags; - u32 tmp; - u8 head; - - spin_lock_irqsave(&pcap->adc_lock, flags); - head = pcap->adc_head; - if (!pcap->adc_queue[head]) { - /* queue is empty, save power */ - pcap_disable_adc(pcap); - spin_unlock_irqrestore(&pcap->adc_lock, flags); - return; - } - /* start conversion on requested bank, save TS_M bits */ - ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); - tmp &= (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR); - tmp |= pcap->adc_queue[head]->flags | PCAP_ADC_ADEN; - - if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1) - tmp |= PCAP_ADC_AD_SEL1; - - ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); - spin_unlock_irqrestore(&pcap->adc_lock, flags); - ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC); -} - -static irqreturn_t pcap_adc_irq(int irq, void *_pcap) -{ - struct pcap_chip *pcap = _pcap; - struct pcap_adc_request *req; - u16 res[2]; - u32 tmp; - - spin_lock(&pcap->adc_lock); - req = pcap->adc_queue[pcap->adc_head]; - - if (WARN(!req, "adc irq without pending request\n")) { - spin_unlock(&pcap->adc_lock); - return IRQ_HANDLED; - } - - /* read requested channels results */ - ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp); - tmp &= ~(PCAP_ADC_ADA1_MASK | PCAP_ADC_ADA2_MASK); - tmp |= (req->ch[0] << PCAP_ADC_ADA1_SHIFT); - tmp |= (req->ch[1] << PCAP_ADC_ADA2_SHIFT); - ezx_pcap_write(pcap, PCAP_REG_ADC, tmp); - ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp); - res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT; - res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT; - - pcap->adc_queue[pcap->adc_head] = NULL; - pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1); - spin_unlock(&pcap->adc_lock); - - /* pass the results and release memory */ - req->callback(req->data, res); - kfree(req); - - /* trigger next conversion (if any) on queue */ - pcap_adc_trigger(pcap); - - return IRQ_HANDLED; -} - -int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[], - void *callback, void *data) -{ - struct pcap_adc_request *req; - unsigned long irq_flags; - - /* This will be freed after we have a result */ - req = kmalloc_obj(struct pcap_adc_request); - if (!req) - return -ENOMEM; - - req->bank = bank; - req->flags = flags; - req->ch[0] = ch[0]; - req->ch[1] = ch[1]; - req->callback = callback; - req->data = data; - - spin_lock_irqsave(&pcap->adc_lock, irq_flags); - if (pcap->adc_queue[pcap->adc_tail]) { - spin_unlock_irqrestore(&pcap->adc_lock, irq_flags); - kfree(req); - return -EBUSY; - } - pcap->adc_queue[pcap->adc_tail] = req; - pcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1); - spin_unlock_irqrestore(&pcap->adc_lock, irq_flags); - - /* start conversion */ - pcap_adc_trigger(pcap); - - return 0; -} -EXPORT_SYMBOL_GPL(pcap_adc_async); - -/* subdevs */ -static int pcap_remove_subdev(struct device *dev, void *unused) -{ - platform_device_unregister(to_platform_device(dev)); - return 0; -} - -static int pcap_add_subdev(struct pcap_chip *pcap, - struct pcap_subdev *subdev) -{ - struct platform_device *pdev; - int ret; - - pdev = platform_device_alloc(subdev->name, subdev->id); - if (!pdev) - return -ENOMEM; - - pdev->dev.parent = &pcap->spi->dev; - pdev->dev.platform_data = subdev->platform_data; - - ret = platform_device_add(pdev); - if (ret) - platform_device_put(pdev); - - return ret; -} - -static void ezx_pcap_remove(struct spi_device *spi) -{ - struct pcap_chip *pcap = spi_get_drvdata(spi); - unsigned long flags; - int i; - - /* remove all registered subdevs */ - device_for_each_child(&spi->dev, NULL, pcap_remove_subdev); - - /* cleanup ADC */ - spin_lock_irqsave(&pcap->adc_lock, flags); - for (i = 0; i < PCAP_ADC_MAXQ; i++) - kfree(pcap->adc_queue[i]); - spin_unlock_irqrestore(&pcap->adc_lock, flags); - - /* cleanup irqchip */ - for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) - irq_set_chip_and_handler(i, NULL, NULL); -} - -static int ezx_pcap_probe(struct spi_device *spi) -{ - struct pcap_platform_data *pdata = dev_get_platdata(&spi->dev); - struct pcap_chip *pcap; - int i, adc_irq; - int ret; - - /* platform data is required */ - if (!pdata) - return -ENODEV; - - pcap = devm_kzalloc(&spi->dev, sizeof(*pcap), GFP_KERNEL); - if (!pcap) - return -ENOMEM; - - spin_lock_init(&pcap->io_lock); - spin_lock_init(&pcap->adc_lock); - INIT_WORK(&pcap->isr_work, pcap_isr_work); - INIT_WORK(&pcap->msr_work, pcap_msr_work); - spi_set_drvdata(spi, pcap); - - /* setup spi */ - spi->bits_per_word = 32; - spi->mode = SPI_MODE_0 | (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0); - ret = spi_setup(spi); - if (ret) - return ret; - - pcap->spi = spi; - - /* setup irq */ - pcap->irq_base = pdata->irq_base; - pcap->workqueue = devm_alloc_ordered_workqueue(&spi->dev, "pcapd", 0); - if (!pcap->workqueue) - return -ENOMEM; - - /* redirect interrupts to AP, except adcdone2 */ - if (!(pdata->config & PCAP_SECOND_PORT)) - ezx_pcap_write(pcap, PCAP_REG_INT_SEL, - (1 << PCAP_IRQ_ADCDONE2)); - - /* setup irq chip */ - for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) { - irq_set_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq); - irq_set_chip_data(i, pcap); - irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE); - } - - /* mask/ack all PCAP interrupts */ - ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT); - ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER); - pcap->msr = PCAP_MASK_ALL_INTERRUPT; - - irq_set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING); - irq_set_chained_handler_and_data(spi->irq, pcap_irq_handler, pcap); - irq_set_irq_wake(spi->irq, 1); - - /* ADC */ - adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ? - PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE); - - ret = devm_request_irq(&spi->dev, adc_irq, pcap_adc_irq, 0, "ADC", - pcap); - if (ret) - goto free_irqchip; - - /* setup subdevs */ - for (i = 0; i < pdata->num_subdevs; i++) { - ret = pcap_add_subdev(pcap, &pdata->subdevs[i]); - if (ret) - goto remove_subdevs; - } - - /* board specific quirks */ - if (pdata->init) - pdata->init(pcap); - - return 0; - -remove_subdevs: - device_for_each_child(&spi->dev, NULL, pcap_remove_subdev); -free_irqchip: - for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) - irq_set_chip_and_handler(i, NULL, NULL); - - return ret; -} - -static struct spi_driver ezxpcap_driver = { - .probe = ezx_pcap_probe, - .remove = ezx_pcap_remove, - .driver = { - .name = "ezx-pcap", - }, -}; - -static int __init ezx_pcap_init(void) -{ - return spi_register_driver(&ezxpcap_driver); -} - -static void __exit ezx_pcap_exit(void) -{ - spi_unregister_driver(&ezxpcap_driver); -} - -subsys_initcall(ezx_pcap_init); -module_exit(ezx_pcap_exit); - -MODULE_AUTHOR("Daniel Ribeiro / Harald Welte"); -MODULE_DESCRIPTION("Motorola PCAP2 ASIC Driver"); -MODULE_ALIAS("spi:ezx-pcap"); diff --git a/include/linux/mfd/ezx-pcap.h b/include/linux/mfd/ezx-pcap.h deleted file mode 100644 index ea51b1cdca5a..000000000000 --- a/include/linux/mfd/ezx-pcap.h +++ /dev/null @@ -1,253 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2009 Daniel Ribeiro - * - * For further information, please see http://wiki.openezx.org/PCAP2 - */ - -#ifndef EZX_PCAP_H -#define EZX_PCAP_H - -struct pcap_subdev { - int id; - const char *name; - void *platform_data; -}; - -struct pcap_platform_data { - unsigned int irq_base; - unsigned int config; - int gpio; - void (*init) (void *); /* board specific init */ - int num_subdevs; - struct pcap_subdev *subdevs; -}; - -struct pcap_chip; - -int ezx_pcap_write(struct pcap_chip *, u8, u32); -int ezx_pcap_read(struct pcap_chip *, u8, u32 *); -int ezx_pcap_set_bits(struct pcap_chip *, u8, u32, u32); -int pcap_to_irq(struct pcap_chip *, int); -int irq_to_pcap(struct pcap_chip *, int); -int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *); -void pcap_set_ts_bits(struct pcap_chip *, u32); - -#define PCAP_SECOND_PORT 1 -#define PCAP_CS_AH 2 - -#define PCAP_REGISTER_WRITE_OP_BIT 0x80000000 -#define PCAP_REGISTER_READ_OP_BIT 0x00000000 - -#define PCAP_REGISTER_VALUE_MASK 0x01ffffff -#define PCAP_REGISTER_ADDRESS_MASK 0x7c000000 -#define PCAP_REGISTER_ADDRESS_SHIFT 26 -#define PCAP_REGISTER_NUMBER 32 -#define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff -#define PCAP_MASK_ALL_INTERRUPT 0x01ffffff - -/* registers accessible by both pcap ports */ -#define PCAP_REG_ISR 0x0 /* Interrupt Status */ -#define PCAP_REG_MSR 0x1 /* Interrupt Mask */ -#define PCAP_REG_PSTAT 0x2 /* Processor Status */ -#define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */ -#define PCAP_REG_AUXVREG 0x7 /* Auxiliary Regulator Control */ -#define PCAP_REG_BATT 0x8 /* Battery Control */ -#define PCAP_REG_ADC 0x9 /* AD Control */ -#define PCAP_REG_ADR 0xa /* AD Result */ -#define PCAP_REG_CODEC 0xb /* Audio Codec Control */ -#define PCAP_REG_RX_AMPS 0xc /* RX Audio Amplifiers Control */ -#define PCAP_REG_ST_DAC 0xd /* Stereo DAC Control */ -#define PCAP_REG_BUSCTRL 0x14 /* Connectivity Control */ -#define PCAP_REG_PERIPH 0x15 /* Peripheral Control */ -#define PCAP_REG_LOWPWR 0x18 /* Regulator Low Power Control */ -#define PCAP_REG_TX_AMPS 0x1a /* TX Audio Amplifiers Control */ -#define PCAP_REG_GP 0x1b /* General Purpose */ -#define PCAP_REG_TEST1 0x1c -#define PCAP_REG_TEST2 0x1d -#define PCAP_REG_VENDOR_TEST1 0x1e -#define PCAP_REG_VENDOR_TEST2 0x1f - -/* registers accessible by pcap port 1 only (a1200, e2 & e6) */ -#define PCAP_REG_INT_SEL 0x3 /* Interrupt Select */ -#define PCAP_REG_SWCTRL 0x4 /* Switching Regulator Control */ -#define PCAP_REG_VREG1 0x5 /* Regulator Bank 1 Control */ -#define PCAP_REG_RTC_TOD 0xe /* RTC Time of Day */ -#define PCAP_REG_RTC_TODA 0xf /* RTC Time of Day Alarm */ -#define PCAP_REG_RTC_DAY 0x10 /* RTC Day */ -#define PCAP_REG_RTC_DAYA 0x11 /* RTC Day Alarm */ -#define PCAP_REG_MTRTMR 0x12 /* AD Monitor Timer */ -#define PCAP_REG_PWR 0x13 /* Power Control */ -#define PCAP_REG_AUXVREG_MASK 0x16 /* Auxiliary Regulator Mask */ -#define PCAP_REG_VENDOR_REV 0x17 -#define PCAP_REG_PERIPH_MASK 0x19 /* Peripheral Mask */ - -/* PCAP2 Interrupts */ -#define PCAP_NIRQS 23 -#define PCAP_IRQ_ADCDONE 0 /* ADC done port 1 */ -#define PCAP_IRQ_TS 1 /* Touch Screen */ -#define PCAP_IRQ_1HZ 2 /* 1HZ timer */ -#define PCAP_IRQ_WH 3 /* ADC above high limit */ -#define PCAP_IRQ_WL 4 /* ADC below low limit */ -#define PCAP_IRQ_TODA 5 /* Time of day alarm */ -#define PCAP_IRQ_USB4V 6 /* USB above 4V */ -#define PCAP_IRQ_ONOFF 7 /* On/Off button */ -#define PCAP_IRQ_ONOFF2 8 /* On/Off button 2 */ -#define PCAP_IRQ_USB1V 9 /* USB above 1V */ -#define PCAP_IRQ_MOBPORT 10 -#define PCAP_IRQ_MIC 11 /* Mic attach/HS button */ -#define PCAP_IRQ_HS 12 /* Headset attach */ -#define PCAP_IRQ_ST 13 -#define PCAP_IRQ_PC 14 /* Power Cut */ -#define PCAP_IRQ_WARM 15 -#define PCAP_IRQ_EOL 16 /* Battery End Of Life */ -#define PCAP_IRQ_CLK 17 -#define PCAP_IRQ_SYSRST 18 /* System Reset */ -#define PCAP_IRQ_DUMMY 19 -#define PCAP_IRQ_ADCDONE2 20 /* ADC done port 2 */ -#define PCAP_IRQ_SOFTRESET 21 -#define PCAP_IRQ_MNEXB 22 - -/* voltage regulators */ -#define V1 0 -#define V2 1 -#define V3 2 -#define V4 3 -#define V5 4 -#define V6 5 -#define V7 6 -#define V8 7 -#define V9 8 -#define V10 9 -#define VAUX1 10 -#define VAUX2 11 -#define VAUX3 12 -#define VAUX4 13 -#define VSIM 14 -#define VSIM2 15 -#define VVIB 16 -#define SW1 17 -#define SW2 18 -#define SW3 19 -#define SW1S 20 -#define SW2S 21 - -#define PCAP_BATT_DAC_MASK 0x000000ff -#define PCAP_BATT_DAC_SHIFT 0 -#define PCAP_BATT_B_FDBK (1 << 8) -#define PCAP_BATT_EXT_ISENSE (1 << 9) -#define PCAP_BATT_V_COIN_MASK 0x00003c00 -#define PCAP_BATT_V_COIN_SHIFT 10 -#define PCAP_BATT_I_COIN (1 << 14) -#define PCAP_BATT_COIN_CH_EN (1 << 15) -#define PCAP_BATT_EOL_SEL_MASK 0x000e0000 -#define PCAP_BATT_EOL_SEL_SHIFT 17 -#define PCAP_BATT_EOL_CMP_EN (1 << 20) -#define PCAP_BATT_BATT_DET_EN (1 << 21) -#define PCAP_BATT_THERMBIAS_CTRL (1 << 22) - -#define PCAP_ADC_ADEN (1 << 0) -#define PCAP_ADC_RAND (1 << 1) -#define PCAP_ADC_AD_SEL1 (1 << 2) -#define PCAP_ADC_AD_SEL2 (1 << 3) -#define PCAP_ADC_ADA1_MASK 0x00000070 -#define PCAP_ADC_ADA1_SHIFT 4 -#define PCAP_ADC_ADA2_MASK 0x00000380 -#define PCAP_ADC_ADA2_SHIFT 7 -#define PCAP_ADC_ATO_MASK 0x00003c00 -#define PCAP_ADC_ATO_SHIFT 10 -#define PCAP_ADC_ATOX (1 << 14) -#define PCAP_ADC_MTR1 (1 << 15) -#define PCAP_ADC_MTR2 (1 << 16) -#define PCAP_ADC_TS_M_MASK 0x000e0000 -#define PCAP_ADC_TS_M_SHIFT 17 -#define PCAP_ADC_TS_REF_LOWPWR (1 << 20) -#define PCAP_ADC_TS_REFENB (1 << 21) -#define PCAP_ADC_BATT_I_POLARITY (1 << 22) -#define PCAP_ADC_BATT_I_ADC (1 << 23) - -#define PCAP_ADC_BANK_0 0 -#define PCAP_ADC_BANK_1 1 -/* ADC bank 0 */ -#define PCAP_ADC_CH_COIN 0 -#define PCAP_ADC_CH_BATT 1 -#define PCAP_ADC_CH_BPLUS 2 -#define PCAP_ADC_CH_MOBPORTB 3 -#define PCAP_ADC_CH_TEMPERATURE 4 -#define PCAP_ADC_CH_CHARGER_ID 5 -#define PCAP_ADC_CH_AD6 6 -/* ADC bank 1 */ -#define PCAP_ADC_CH_AD7 0 -#define PCAP_ADC_CH_AD8 1 -#define PCAP_ADC_CH_AD9 2 -#define PCAP_ADC_CH_TS_X1 3 -#define PCAP_ADC_CH_TS_X2 4 -#define PCAP_ADC_CH_TS_Y1 5 -#define PCAP_ADC_CH_TS_Y2 6 - -#define PCAP_ADC_T_NOW 0 -#define PCAP_ADC_T_IN_BURST 1 -#define PCAP_ADC_T_OUT_BURST 2 - -#define PCAP_ADC_ATO_IN_BURST 6 -#define PCAP_ADC_ATO_OUT_BURST 0 - -#define PCAP_ADC_TS_M_XY 1 -#define PCAP_ADC_TS_M_PRESSURE 2 -#define PCAP_ADC_TS_M_PLATE_X 3 -#define PCAP_ADC_TS_M_PLATE_Y 4 -#define PCAP_ADC_TS_M_STANDBY 5 -#define PCAP_ADC_TS_M_NONTS 6 - -#define PCAP_ADR_ADD1_MASK 0x000003ff -#define PCAP_ADR_ADD1_SHIFT 0 -#define PCAP_ADR_ADD2_MASK 0x000ffc00 -#define PCAP_ADR_ADD2_SHIFT 10 -#define PCAP_ADR_ADINC1 (1 << 20) -#define PCAP_ADR_ADINC2 (1 << 21) -#define PCAP_ADR_ASC (1 << 22) -#define PCAP_ADR_ONESHOT (1 << 23) - -#define PCAP_BUSCTRL_FSENB (1 << 0) -#define PCAP_BUSCTRL_USB_SUSPEND (1 << 1) -#define PCAP_BUSCTRL_USB_PU (1 << 2) -#define PCAP_BUSCTRL_USB_PD (1 << 3) -#define PCAP_BUSCTRL_VUSB_EN (1 << 4) -#define PCAP_BUSCTRL_USB_PS (1 << 5) -#define PCAP_BUSCTRL_VUSB_MSTR_EN (1 << 6) -#define PCAP_BUSCTRL_VBUS_PD_ENB (1 << 7) -#define PCAP_BUSCTRL_CURRLIM (1 << 8) -#define PCAP_BUSCTRL_RS232ENB (1 << 9) -#define PCAP_BUSCTRL_RS232_DIR (1 << 10) -#define PCAP_BUSCTRL_SE0_CONN (1 << 11) -#define PCAP_BUSCTRL_USB_PDM (1 << 12) -#define PCAP_BUSCTRL_BUS_PRI_ADJ (1 << 24) - -/* leds */ -#define PCAP_LED0 0 -#define PCAP_LED1 1 -#define PCAP_BL0 2 -#define PCAP_BL1 3 -#define PCAP_LED_3MA 0 -#define PCAP_LED_4MA 1 -#define PCAP_LED_5MA 2 -#define PCAP_LED_9MA 3 -#define PCAP_LED_T_MASK 0xf -#define PCAP_LED_C_MASK 0x3 -#define PCAP_BL_MASK 0x1f -#define PCAP_BL0_SHIFT 0 -#define PCAP_LED0_EN (1 << 5) -#define PCAP_LED1_EN (1 << 6) -#define PCAP_LED0_T_SHIFT 7 -#define PCAP_LED1_T_SHIFT 11 -#define PCAP_LED0_C_SHIFT 15 -#define PCAP_LED1_C_SHIFT 17 -#define PCAP_BL1_SHIFT 20 - -/* RTC */ -#define PCAP_RTC_DAY_MASK 0x3fff -#define PCAP_RTC_TOD_MASK 0xffff -#define PCAP_RTC_PC_MASK 0x7 -#define SEC_PER_DAY 86400 - -#endif -- cgit v1.2.3