From c5a2de97fbd2979fab291fb048084d3fddd322dd Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 15 Dec 2017 09:41:23 -0800 Subject: bus: ti-sysc: Add parsing of module capabilities We need to configure the interconnect target module based on the device three configuration. Let's also add a new quirk for SYSC_QUIRK_RESET_STATUS to indicate that the SYSCONFIG reset bit changes after the reset is done. Signed-off-by: Tony Lindgren --- include/linux/platform_data/ti-sysc.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include/linux/platform_data/ti-sysc.h') diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h index 28e5a61d4abc..1be356330b96 100644 --- a/include/linux/platform_data/ti-sysc.h +++ b/include/linux/platform_data/ti-sysc.h @@ -41,6 +41,7 @@ struct sysc_regbits { s8 emufree_shift; }; +#define SYSC_QUIRK_RESET_STATUS BIT(7) #define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6) #define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5) #define SYSC_QUIRK_OPT_CLKS_NEEDED BIT(4) @@ -49,6 +50,8 @@ struct sysc_regbits { #define SYSC_QUIRK_UNCACHED BIT(1) #define SYSC_QUIRK_USE_CLOCKACT BIT(0) +#define SYSC_NR_IDLEMODES 4 + /** * struct sysc_capabilities - capabilities for an interconnect target module * @@ -65,10 +68,17 @@ struct sysc_capabilities { /** * struct sysc_config - configuration for an interconnect target module + * @sysc_val: configured value for sysc register + * @midlemodes: bitmask of supported master idle modes + * @sidlemodes: bitmask of supported master idle modes * @srst_udelay: optional delay needed after OCP soft reset * @quirks: bitmask of enabled quirks */ struct sysc_config { + u32 sysc_val; + u32 syss_mask; + u8 midlemodes; + u8 sidlemodes; u8 srst_udelay; u32 quirks; }; -- cgit v1.2.3