From 095a7e388b5fbf8958686a90a04fe9387f6aa50b Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:12 -0700 Subject: irqchip: mips-gic: Remove counter access functions The MIPS GIC clocksource driver is no longer using the accessor functions provided by the irqchip driver, so remove them. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17022/ Signed-off-by: Ralf Baechle --- include/linux/irqchip/mips-gic.h | 22 ---------------------- 1 file changed, 22 deletions(-) (limited to 'include/linux/irqchip') diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index 2b0e56619e53..c9e1c993cf5b 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -40,11 +40,6 @@ #define GIC_SH_CONFIG_OFS 0x0000 -/* Shared Global Counter */ -#define GIC_SH_COUNTER_31_00_OFS 0x0010 -/* 64-bit counter register for CM3 */ -#define GIC_SH_COUNTER_OFS GIC_SH_COUNTER_31_00_OFS -#define GIC_SH_COUNTER_63_32_OFS 0x0014 #define GIC_SH_REVISIONID_OFS 0x0020 /* Convert an interrupt number to a byte offset/bit for multi-word registers */ @@ -107,10 +102,6 @@ #define GIC_VPE_WD_CONFIG0_OFS 0x0090 #define GIC_VPE_WD_COUNT0_OFS 0x0094 #define GIC_VPE_WD_INITIAL0_OFS 0x0098 -#define GIC_VPE_COMPARE_LO_OFS 0x00a0 -/* 64-bit Compare register on CM3 */ -#define GIC_VPE_COMPARE_OFS GIC_VPE_COMPARE_LO_OFS -#define GIC_VPE_COMPARE_HI_OFS 0x00a4 #define GIC_VPE_EIC_SHADOW_SET_BASE_OFS 0x0100 #define GIC_VPE_EIC_SS(intr) (4 * (intr)) @@ -128,12 +119,6 @@ #define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 /* Masks */ -#define GIC_SH_CONFIG_COUNTSTOP_SHF 28 -#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF) - -#define GIC_SH_CONFIG_COUNTBITS_SHF 24 -#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF) - #define GIC_SH_CONFIG_NUMINTRS_SHF 16 #define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF) @@ -258,13 +243,6 @@ extern unsigned int gic_present; extern void gic_init(unsigned long gic_base_addr, unsigned long gic_addrspace_size, unsigned int cpu_vec, unsigned int irqbase); -extern u64 gic_read_count(void); -extern unsigned int gic_get_count_width(void); -extern u64 gic_read_compare(void); -extern void gic_write_compare(u64 cnt); -extern void gic_write_cpu_compare(u64 cnt, int cpu); -extern void gic_start_count(void); -extern void gic_stop_count(void); extern int gic_get_c0_compare_int(void); extern int gic_get_c0_perfcount_int(void); extern int gic_get_c0_fdc_int(void); -- cgit v1.2.3 From 9762d2e6d329a500dc6c07156e3c56aab3992471 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:14 -0700 Subject: irqchip: mips-gic: Remove gic_read_local_vp_id() Nothing needs gic_read_local_vp_id() any longer, so remove the dead code. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17024/ Signed-off-by: Ralf Baechle --- drivers/irqchip/irq-mips-gic.c | 8 -------- include/linux/irqchip/mips-gic.h | 17 ----------------- 2 files changed, 25 deletions(-) (limited to 'include/linux/irqchip') diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index e41ff59ceb32..5193e6cf87ab 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -138,14 +138,6 @@ static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe) GIC_SH_MAP_TO_VPE_REG_BIT(vpe)); } -unsigned gic_read_local_vp_id(void) -{ - unsigned long ident; - - ident = gic_read(GIC_REG(VPE_LOCAL, GIC_VP_IDENT)); - return ident & GIC_VP_IDENT_VCNUM_MSK; -} - static bool gic_local_irq_is_routable(int intr) { u32 vpe_ctl; diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index c9e1c993cf5b..29453bdc06e2 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -98,7 +98,6 @@ #define GIC_VPE_SWINT0_MAP_OFS 0x0054 #define GIC_VPE_SWINT1_MAP_OFS 0x0058 #define GIC_VPE_OTHER_ADDR_OFS 0x0080 -#define GIC_VP_IDENT_OFS 0x0088 #define GIC_VPE_WD_CONFIG0_OFS 0x0090 #define GIC_VPE_WD_COUNT0_OFS 0x0094 #define GIC_VPE_WD_INITIAL0_OFS 0x0098 @@ -197,10 +196,6 @@ #define GIC_VPE_SMASK_FDC_SHF 6 #define GIC_VPE_SMASK_FDC_MSK (MSK(1) << GIC_VPE_SMASK_FDC_SHF) -/* GIC_VP_IDENT fields */ -#define GIC_VP_IDENT_VCNUM_SHF 0 -#define GIC_VP_IDENT_VCNUM_MSK (MSK(6) << GIC_VP_IDENT_VCNUM_SHF) - /* GIC nomenclature for Core Interrupt Pins. */ #define GIC_CPU_INT0 0 /* Core Interrupt 2 */ #define GIC_CPU_INT1 1 /* . */ @@ -260,16 +255,4 @@ static inline int gic_get_usm_range(struct resource *gic_usm_res) #endif /* CONFIG_MIPS_GIC */ -/** - * gic_read_local_vp_id() - read the local VPs VCNUM - * - * Read the VCNUM of the local VP from the GIC_VP_IDENT register and - * return it to the caller. This ID should be used to refer to the VP - * via the GICs VP-other region, or when calculating an offset to a - * bit representing the VP in interrupt masks. - * - * Return: The VCNUM value for the local VP. - */ -extern unsigned gic_read_local_vp_id(void); - #endif /* __LINUX_IRQCHIP_MIPS_GIC_H */ -- cgit v1.2.3 From e98fcb2a8cc003c37c24713d2303667a8f624a30 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:16 -0700 Subject: irqchip: mips-gic: Simplify shared interrupt pending/mask reads Simplify the reads of the bitmaps indicating pending & masked interrupts in gic_handle_shared_int() using the __ioread32_copy() & __ioread64_copy() helper functions. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17026/ Signed-off-by: Ralf Baechle --- drivers/irqchip/irq-mips-gic.c | 29 +++++++++++------------------ include/linux/irqchip/mips-gic.h | 6 ------ 2 files changed, 11 insertions(+), 24 deletions(-) (limited to 'include/linux/irqchip') diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 5193e6cf87ab..7445c3b58c44 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -225,31 +225,24 @@ int gic_get_usm_range(struct resource *gic_usm_res) static void gic_handle_shared_int(bool chained) { - unsigned int i, intr, virq, gic_reg_step = mips_cm_is64 ? 8 : 4; + unsigned int intr, virq; unsigned long *pcpu_mask; - unsigned long pending_reg, intrmask_reg; DECLARE_BITMAP(pending, GIC_MAX_INTRS); DECLARE_BITMAP(intrmask, GIC_MAX_INTRS); /* Get per-cpu bitmaps */ pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask; - pending_reg = GIC_REG(SHARED, GIC_SH_PEND); - intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK); - - for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) { - pending[i] = gic_read(pending_reg); - intrmask[i] = gic_read(intrmask_reg); - pending_reg += gic_reg_step; - intrmask_reg += gic_reg_step; - - if (!IS_ENABLED(CONFIG_64BIT) || mips_cm_is64) - continue; - - pending[i] |= (u64)gic_read(pending_reg) << 32; - intrmask[i] |= (u64)gic_read(intrmask_reg) << 32; - pending_reg += gic_reg_step; - intrmask_reg += gic_reg_step; + if (mips_cm_is64) { + __ioread64_copy(pending, addr_gic_pend(), + DIV_ROUND_UP(gic_shared_intrs, 64)); + __ioread64_copy(intrmask, addr_gic_mask(), + DIV_ROUND_UP(gic_shared_intrs, 64)); + } else { + __ioread32_copy(pending, addr_gic_pend(), + DIV_ROUND_UP(gic_shared_intrs, 32)); + __ioread32_copy(intrmask, addr_gic_mask(), + DIV_ROUND_UP(gic_shared_intrs, 32)); } bitmap_and(pending, pending, intrmask, gic_shared_intrs); diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index 29453bdc06e2..835e25506660 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -68,12 +68,6 @@ #define GIC_SH_RMASK_OFS 0x0300 #define GIC_SH_SMASK_OFS 0x0380 -/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */ -#define GIC_SH_MASK_OFS 0x0400 - -/* Pending Global Interrupts (RO) */ -#define GIC_SH_PEND_OFS 0x0480 - /* Maps Interrupt X to a Pin */ #define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500 #define GIC_SH_MAP_TO_PIN(intr) (4 * (intr)) -- cgit v1.2.3 From a0dc5cb5e31bdbcf1f1dddf62a62d06d6b82d53a Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:17 -0700 Subject: irqchip: mips-gic: Simplify gic_local_irq_domain_map() Simplify gic_local_irq_domain_map() by: - Moving the check for invalid IRQs outside of the loop. - Moving the decision about whether to use gic_cpu_pin or timer_cpu_pin outside of the loop. - Using the new write_gic_vo_map() accessor function to avoid the need to handle each map register separately. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17027/ Signed-off-by: Ralf Baechle --- drivers/irqchip/irq-mips-gic.c | 57 +++++++++++----------------------------- include/linux/irqchip/mips-gic.h | 6 ----- 2 files changed, 16 insertions(+), 47 deletions(-) (limited to 'include/linux/irqchip') diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 7445c3b58c44..4b6c4e55562d 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -498,58 +498,33 @@ static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hw) { int intr = GIC_HWIRQ_TO_LOCAL(hw); - int ret = 0; int i; unsigned long flags; + u32 val; if (!gic_local_irq_is_routable(intr)) return -EPERM; - spin_lock_irqsave(&gic_lock, flags); - for (i = 0; i < gic_vpes; i++) { - u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin; + if (intr > GIC_LOCAL_INT_FDC) { + pr_err("Invalid local IRQ %d\n", intr); + return -EINVAL; + } - gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), - mips_cm_vp_id(i)); + if (intr == GIC_LOCAL_INT_TIMER) { + /* CONFIG_MIPS_CMP workaround (see __gic_init) */ + val = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin; + } else { + val = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin; + } - switch (intr) { - case GIC_LOCAL_INT_WD: - gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val); - break; - case GIC_LOCAL_INT_COMPARE: - gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP), - val); - break; - case GIC_LOCAL_INT_TIMER: - /* CONFIG_MIPS_CMP workaround (see __gic_init) */ - val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin; - gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), - val); - break; - case GIC_LOCAL_INT_PERFCTR: - gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), - val); - break; - case GIC_LOCAL_INT_SWINT0: - gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP), - val); - break; - case GIC_LOCAL_INT_SWINT1: - gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP), - val); - break; - case GIC_LOCAL_INT_FDC: - gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val); - break; - default: - pr_err("Invalid local IRQ %d\n", intr); - ret = -EINVAL; - break; - } + spin_lock_irqsave(&gic_lock, flags); + for (i = 0; i < gic_vpes; i++) { + write_gic_vl_other(mips_cm_vp_id(i)); + write_gic_vo_map(intr, val); } spin_unlock_irqrestore(&gic_lock, flags); - return ret; + return 0; } static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index 835e25506660..1342b17b6812 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -84,13 +84,7 @@ #define GIC_VPE_MASK_OFS 0x0008 #define GIC_VPE_RMASK_OFS 0x000c #define GIC_VPE_SMASK_OFS 0x0010 -#define GIC_VPE_WD_MAP_OFS 0x0040 -#define GIC_VPE_COMPARE_MAP_OFS 0x0044 #define GIC_VPE_TIMER_MAP_OFS 0x0048 -#define GIC_VPE_FDC_MAP_OFS 0x004c -#define GIC_VPE_PERFCTR_MAP_OFS 0x0050 -#define GIC_VPE_SWINT0_MAP_OFS 0x0054 -#define GIC_VPE_SWINT1_MAP_OFS 0x0058 #define GIC_VPE_OTHER_ADDR_OFS 0x0080 #define GIC_VPE_WD_CONFIG0_OFS 0x0090 #define GIC_VPE_WD_COUNT0_OFS 0x0094 -- cgit v1.2.3 From 87554b0ef3884143563e090375269730780c6617 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:18 -0700 Subject: irqchip: mips-gic: Drop gic_(re)set_mask() functions The gic_set_mask() & gic_reset_mask() functions are now no more convenient to call than the write_gic_smask() or write_gic_rmask() accessor functions. Remove the layer of abstraction. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17028/ Signed-off-by: Ralf Baechle --- drivers/irqchip/irq-mips-gic.c | 18 +++--------------- include/linux/irqchip/mips-gic.h | 4 ---- 2 files changed, 3 insertions(+), 19 deletions(-) (limited to 'include/linux/irqchip') diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 4b6c4e55562d..7eb998c61d1e 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -92,18 +92,6 @@ static inline void gic_update_bits(unsigned int reg, unsigned long mask, gic_write(reg, regval); } -static inline void gic_reset_mask(unsigned int intr) -{ - gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr), - 1ul << GIC_INTR_BIT(intr)); -} - -static inline void gic_set_mask(unsigned int intr) -{ - gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr), - 1ul << GIC_INTR_BIT(intr)); -} - static inline void gic_set_polarity(unsigned int intr, unsigned int pol) { gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) + @@ -260,12 +248,12 @@ static void gic_handle_shared_int(bool chained) static void gic_mask_irq(struct irq_data *d) { - gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq)); + write_gic_rmask(BIT(GIC_HWIRQ_TO_SHARED(d->hwirq))); } static void gic_unmask_irq(struct irq_data *d) { - gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq)); + write_gic_smask(BIT(GIC_HWIRQ_TO_SHARED(d->hwirq))); } static void gic_ack_irq(struct irq_data *d) @@ -478,7 +466,7 @@ static void __init gic_basic_init(void) for (i = 0; i < gic_shared_intrs; i++) { gic_set_polarity(i, GIC_POL_POS); gic_set_trigger(i, GIC_TRIG_LEVEL); - gic_reset_mask(i); + write_gic_rmask(BIT(i)); } for (i = 0; i < gic_vpes; i++) { diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index 1342b17b6812..8160cc8b677d 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -64,10 +64,6 @@ /* Set/Clear corresponding bit in Edge Detect Register */ #define GIC_SH_WEDGE_OFS 0x0280 -/* Mask manipulation */ -#define GIC_SH_RMASK_OFS 0x0300 -#define GIC_SH_SMASK_OFS 0x0380 - /* Maps Interrupt X to a Pin */ #define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500 #define GIC_SH_MAP_TO_PIN(intr) (4 * (intr)) -- cgit v1.2.3 From 80e5f9c9e295b08c5c588083a4ad35e1e5f78731 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:19 -0700 Subject: irqchip: mips-gic: Remove gic_set_polarity() Remove the gic_set_polarity() function in favour of using the new change_gic_pol() accessor function which provides equivalent functionality. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17029/ Signed-off-by: Ralf Baechle --- drivers/irqchip/irq-mips-gic.c | 17 +++++------------ include/linux/irqchip/mips-gic.h | 5 ----- 2 files changed, 5 insertions(+), 17 deletions(-) (limited to 'include/linux/irqchip') diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 7eb998c61d1e..987289558024 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -92,13 +92,6 @@ static inline void gic_update_bits(unsigned int reg, unsigned long mask, gic_write(reg, regval); } -static inline void gic_set_polarity(unsigned int intr, unsigned int pol) -{ - gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) + - GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr), - (unsigned long)pol << GIC_INTR_BIT(intr)); -} - static inline void gic_set_trigger(unsigned int intr, unsigned int trig) { gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) + @@ -272,13 +265,13 @@ static int gic_set_type(struct irq_data *d, unsigned int type) spin_lock_irqsave(&gic_lock, flags); switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_FALLING: - gic_set_polarity(irq, GIC_POL_NEG); + change_gic_pol(irq, GIC_POL_FALLING_EDGE); gic_set_trigger(irq, GIC_TRIG_EDGE); gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); is_edge = true; break; case IRQ_TYPE_EDGE_RISING: - gic_set_polarity(irq, GIC_POL_POS); + change_gic_pol(irq, GIC_POL_RISING_EDGE); gic_set_trigger(irq, GIC_TRIG_EDGE); gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); is_edge = true; @@ -290,14 +283,14 @@ static int gic_set_type(struct irq_data *d, unsigned int type) is_edge = true; break; case IRQ_TYPE_LEVEL_LOW: - gic_set_polarity(irq, GIC_POL_NEG); + change_gic_pol(irq, GIC_POL_ACTIVE_LOW); gic_set_trigger(irq, GIC_TRIG_LEVEL); gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); is_edge = false; break; case IRQ_TYPE_LEVEL_HIGH: default: - gic_set_polarity(irq, GIC_POL_POS); + change_gic_pol(irq, GIC_POL_ACTIVE_HIGH); gic_set_trigger(irq, GIC_TRIG_LEVEL); gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); is_edge = false; @@ -464,7 +457,7 @@ static void __init gic_basic_init(void) /* Setup defaults */ for (i = 0; i < gic_shared_intrs; i++) { - gic_set_polarity(i, GIC_POL_POS); + change_gic_pol(i, GIC_POL_ACTIVE_HIGH); gic_set_trigger(i, GIC_TRIG_LEVEL); write_gic_rmask(BIT(i)); } diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index 8160cc8b677d..960e49a64e7a 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -14,8 +14,6 @@ #define GIC_MAX_INTRS 256 /* Constants */ -#define GIC_POL_POS 1 -#define GIC_POL_NEG 0 #define GIC_TRIG_EDGE 1 #define GIC_TRIG_LEVEL 0 #define GIC_TRIG_DUAL_ENABLE 1 @@ -52,9 +50,6 @@ }) #define GIC_INTR_BIT(intr) ((intr) % (mips_cm_is64 ? 64 : 32)) -/* Polarity : Reset Value is always 0 */ -#define GIC_SH_SET_POLARITY_OFS 0x0100 - /* Triggering : Reset Value is always 0 */ #define GIC_SH_SET_TRIGGER_OFS 0x0180 -- cgit v1.2.3 From 471aa962a6acc19a990e20fa3846db40e62120cc Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:20 -0700 Subject: irqchip: mips-gic: Remove gic_set_trigger() Remove the gic_set_trigger() function in favour of using the new change_gic_trig() accessor function which provides equivalent functionality. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17030/ Signed-off-by: Ralf Baechle --- drivers/irqchip/irq-mips-gic.c | 19 ++++++------------- include/linux/irqchip/mips-gic.h | 5 ----- 2 files changed, 6 insertions(+), 18 deletions(-) (limited to 'include/linux/irqchip') diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 987289558024..14a1682f399e 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -92,13 +92,6 @@ static inline void gic_update_bits(unsigned int reg, unsigned long mask, gic_write(reg, regval); } -static inline void gic_set_trigger(unsigned int intr, unsigned int trig) -{ - gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) + - GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr), - (unsigned long)trig << GIC_INTR_BIT(intr)); -} - static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual) { gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr), @@ -266,32 +259,32 @@ static int gic_set_type(struct irq_data *d, unsigned int type) switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_FALLING: change_gic_pol(irq, GIC_POL_FALLING_EDGE); - gic_set_trigger(irq, GIC_TRIG_EDGE); + change_gic_trig(irq, GIC_TRIG_EDGE); gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); is_edge = true; break; case IRQ_TYPE_EDGE_RISING: change_gic_pol(irq, GIC_POL_RISING_EDGE); - gic_set_trigger(irq, GIC_TRIG_EDGE); + change_gic_trig(irq, GIC_TRIG_EDGE); gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); is_edge = true; break; case IRQ_TYPE_EDGE_BOTH: /* polarity is irrelevant in this case */ - gic_set_trigger(irq, GIC_TRIG_EDGE); + change_gic_trig(irq, GIC_TRIG_EDGE); gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE); is_edge = true; break; case IRQ_TYPE_LEVEL_LOW: change_gic_pol(irq, GIC_POL_ACTIVE_LOW); - gic_set_trigger(irq, GIC_TRIG_LEVEL); + change_gic_trig(irq, GIC_TRIG_LEVEL); gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); is_edge = false; break; case IRQ_TYPE_LEVEL_HIGH: default: change_gic_pol(irq, GIC_POL_ACTIVE_HIGH); - gic_set_trigger(irq, GIC_TRIG_LEVEL); + change_gic_trig(irq, GIC_TRIG_LEVEL); gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); is_edge = false; break; @@ -458,7 +451,7 @@ static void __init gic_basic_init(void) /* Setup defaults */ for (i = 0; i < gic_shared_intrs; i++) { change_gic_pol(i, GIC_POL_ACTIVE_HIGH); - gic_set_trigger(i, GIC_TRIG_LEVEL); + change_gic_trig(i, GIC_TRIG_LEVEL); write_gic_rmask(BIT(i)); } diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index 960e49a64e7a..2e9f0c43d425 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -14,8 +14,6 @@ #define GIC_MAX_INTRS 256 /* Constants */ -#define GIC_TRIG_EDGE 1 -#define GIC_TRIG_LEVEL 0 #define GIC_TRIG_DUAL_ENABLE 1 #define GIC_TRIG_DUAL_DISABLE 0 @@ -50,9 +48,6 @@ }) #define GIC_INTR_BIT(intr) ((intr) % (mips_cm_is64 ? 64 : 32)) -/* Triggering : Reset Value is always 0 */ -#define GIC_SH_SET_TRIGGER_OFS 0x0180 - /* Dual edge triggering : Reset Value is always 0 */ #define GIC_SH_SET_DUAL_OFS 0x0200 -- cgit v1.2.3 From c26ba670cdb84e0556436be7bf68a75a1d4f4d76 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:21 -0700 Subject: irqchip: mips-gic: Remove gic_set_dual_edge() Remove the gic_set_dual_edge() function in favour of using the new change_gic_dual() accessor function which provides equivalent functionality. This also allows us to remove the gic_update_bits() function which gic_set_dual_edge() was the last user of, along with the GIC_INTR_OFS() & GIC_INTR_BIT() macros. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17031/ Signed-off-by: Ralf Baechle --- drivers/irqchip/irq-mips-gic.c | 28 +++++----------------------- include/linux/irqchip/mips-gic.h | 17 ----------------- 2 files changed, 5 insertions(+), 40 deletions(-) (limited to 'include/linux/irqchip') diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 14a1682f399e..8aae9d20b82c 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -81,24 +81,6 @@ static inline void gic_write(unsigned int reg, unsigned long val) return gic_write64(reg, (u64)val); } -static inline void gic_update_bits(unsigned int reg, unsigned long mask, - unsigned long val) -{ - unsigned long regval; - - regval = gic_read(reg); - regval &= ~mask; - regval |= val; - gic_write(reg, regval); -} - -static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual) -{ - gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr), - 1ul << GIC_INTR_BIT(intr), - (unsigned long)dual << GIC_INTR_BIT(intr)); -} - static inline void gic_map_to_pin(unsigned int intr, unsigned int pin) { gic_write32(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) + @@ -260,32 +242,32 @@ static int gic_set_type(struct irq_data *d, unsigned int type) case IRQ_TYPE_EDGE_FALLING: change_gic_pol(irq, GIC_POL_FALLING_EDGE); change_gic_trig(irq, GIC_TRIG_EDGE); - gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); + change_gic_dual(irq, GIC_DUAL_SINGLE); is_edge = true; break; case IRQ_TYPE_EDGE_RISING: change_gic_pol(irq, GIC_POL_RISING_EDGE); change_gic_trig(irq, GIC_TRIG_EDGE); - gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); + change_gic_dual(irq, GIC_DUAL_SINGLE); is_edge = true; break; case IRQ_TYPE_EDGE_BOTH: /* polarity is irrelevant in this case */ change_gic_trig(irq, GIC_TRIG_EDGE); - gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE); + change_gic_dual(irq, GIC_DUAL_DUAL); is_edge = true; break; case IRQ_TYPE_LEVEL_LOW: change_gic_pol(irq, GIC_POL_ACTIVE_LOW); change_gic_trig(irq, GIC_TRIG_LEVEL); - gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); + change_gic_dual(irq, GIC_DUAL_SINGLE); is_edge = false; break; case IRQ_TYPE_LEVEL_HIGH: default: change_gic_pol(irq, GIC_POL_ACTIVE_HIGH); change_gic_trig(irq, GIC_TRIG_LEVEL); - gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); + change_gic_dual(irq, GIC_DUAL_SINGLE); is_edge = false; break; } diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index 2e9f0c43d425..bd348fc9db18 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -13,10 +13,6 @@ #define GIC_MAX_INTRS 256 -/* Constants */ -#define GIC_TRIG_DUAL_ENABLE 1 -#define GIC_TRIG_DUAL_DISABLE 0 - #define MSK(n) ((1 << (n)) - 1) /* Accessors */ @@ -38,19 +34,6 @@ #define GIC_SH_REVISIONID_OFS 0x0020 -/* Convert an interrupt number to a byte offset/bit for multi-word registers */ -#define GIC_INTR_OFS(intr) ({ \ - unsigned bits = mips_cm_is64 ? 64 : 32; \ - unsigned reg_idx = (intr) / bits; \ - unsigned reg_width = bits / 8; \ - \ - reg_idx * reg_width; \ -}) -#define GIC_INTR_BIT(intr) ((intr) % (mips_cm_is64 ? 64 : 32)) - -/* Dual edge triggering : Reset Value is always 0 */ -#define GIC_SH_SET_DUAL_OFS 0x0200 - /* Set/Clear corresponding bit in Edge Detect Register */ #define GIC_SH_WEDGE_OFS 0x0280 -- cgit v1.2.3 From d3e8cf44792d60047ba45036abfc38ab414e49e5 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:22 -0700 Subject: irqchip: mips-gic: Remove gic_map_to_pin() Remove the gic_map_to_pin() function in favour of using the new write_gic_map_pin() accessor function which isn't any more complex to use & allows us to drop a level of abstraction. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17032/ Signed-off-by: Ralf Baechle --- drivers/irqchip/irq-mips-gic.c | 8 +------- include/linux/irqchip/mips-gic.h | 10 ---------- 2 files changed, 1 insertion(+), 17 deletions(-) (limited to 'include/linux/irqchip') diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 8aae9d20b82c..f1a4e5d86ca3 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -81,12 +81,6 @@ static inline void gic_write(unsigned int reg, unsigned long val) return gic_write64(reg, (u64)val); } -static inline void gic_map_to_pin(unsigned int intr, unsigned int pin) -{ - gic_write32(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) + - GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin); -} - static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe) { gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) + @@ -491,7 +485,7 @@ static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, int i; spin_lock_irqsave(&gic_lock, flags); - gic_map_to_pin(intr, gic_cpu_pin); + write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); gic_map_to_vpe(intr, mips_cm_vp_id(vpe)); for (i = 0; i < min(gic_vpes, NR_CPUS); i++) clear_bit(intr, pcpu_masks[i].pcpu_mask); diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index bd348fc9db18..dea79a7a54cc 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -37,10 +37,6 @@ /* Set/Clear corresponding bit in Edge Detect Register */ #define GIC_SH_WEDGE_OFS 0x0280 -/* Maps Interrupt X to a Pin */ -#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500 -#define GIC_SH_MAP_TO_PIN(intr) (4 * (intr)) - /* Maps Interrupt X to a VPE */ #define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000 #define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \ @@ -84,12 +80,6 @@ #define GIC_SH_WEDGE_SET(intr) ((intr) | (0x1 << 31)) #define GIC_SH_WEDGE_CLR(intr) ((intr) & ~(0x1 << 31)) -#define GIC_MAP_TO_PIN_SHF 31 -#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF) -#define GIC_MAP_TO_NMI_SHF 30 -#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF) -#define GIC_MAP_TO_YQ_SHF 29 -#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF) #define GIC_MAP_SHF 0 #define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF) -- cgit v1.2.3 From 0efe3cbf1504309bf088f74eb627d0987f67e934 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:23 -0700 Subject: irqchip: mips-gic: Remove gic_map_to_vpe() Remove the gic_map_to_vpe() function in favour of using the new write_gic_map_vp() accessor function which isn't any more complex to use & allows us to drop a level of abstraction. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17033/ Signed-off-by: Ralf Baechle --- drivers/irqchip/irq-mips-gic.c | 11 ++--------- include/linux/irqchip/mips-gic.h | 6 ------ 2 files changed, 2 insertions(+), 15 deletions(-) (limited to 'include/linux/irqchip') diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index f1a4e5d86ca3..d9851cbb2a6b 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -81,13 +81,6 @@ static inline void gic_write(unsigned int reg, unsigned long val) return gic_write64(reg, (u64)val); } -static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe) -{ - gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) + - GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe), - GIC_SH_MAP_TO_VPE_REG_BIT(vpe)); -} - static bool gic_local_irq_is_routable(int intr) { u32 vpe_ctl; @@ -294,7 +287,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, spin_lock_irqsave(&gic_lock, flags); /* Re-route this IRQ */ - gic_map_to_vpe(irq, mips_cm_vp_id(cpumask_first(&tmp))); + write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpumask_first(&tmp)))); /* Update the pcpu_masks */ for (i = 0; i < min(gic_vpes, NR_CPUS); i++) @@ -486,7 +479,7 @@ static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, spin_lock_irqsave(&gic_lock, flags); write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); - gic_map_to_vpe(intr, mips_cm_vp_id(vpe)); + write_gic_map_vp(intr, BIT(mips_cm_vp_id(vpe))); for (i = 0; i < min(gic_vpes, NR_CPUS); i++) clear_bit(intr, pcpu_masks[i].pcpu_mask); set_bit(intr, pcpu_masks[vpe].pcpu_mask); diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index dea79a7a54cc..ad8b216b6056 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -37,12 +37,6 @@ /* Set/Clear corresponding bit in Edge Detect Register */ #define GIC_SH_WEDGE_OFS 0x0280 -/* Maps Interrupt X to a VPE */ -#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000 -#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \ - ((32 * (intr)) + (((vpe) / 32) * 4)) -#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32)) - /* Register Map for Local Section */ #define GIC_VPE_CTL_OFS 0x0000 #define GIC_VPE_PEND_OFS 0x0004 -- cgit v1.2.3 From 3680746abd87e733ec836025115580562b3dcb47 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:24 -0700 Subject: irqchip: mips-gic: Convert remaining shared reg access to new accessors Convert the remaining accesses to registers in the GIC shared register block to use the new accessor functions provided by asm/mips-gic.h, resulting in code which is often shorter & easier to read. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17034/ Signed-off-by: Ralf Baechle --- drivers/irqchip/irq-mips-gic.c | 16 ++++++++-------- include/linux/irqchip/mips-gic.h | 20 -------------------- 2 files changed, 8 insertions(+), 28 deletions(-) (limited to 'include/linux/irqchip') diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index d9851cbb2a6b..a906284215b7 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -119,7 +119,7 @@ static void gic_send_ipi(struct irq_data *d, unsigned int cpu) { irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d)); - gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_SET(hwirq)); + write_gic_wedge(GIC_WEDGE_RW | hwirq); } int gic_get_c0_compare_int(void) @@ -215,7 +215,7 @@ static void gic_ack_irq(struct irq_data *d) { unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); - gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_CLR(irq)); + write_gic_wedge(irq); } static int gic_set_type(struct irq_data *d, unsigned int type) @@ -700,13 +700,13 @@ static void __init __gic_init(unsigned long gic_base_addr, mips_gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size); - gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); - gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >> - GIC_SH_CONFIG_NUMINTRS_SHF; - gic_shared_intrs = ((gic_shared_intrs + 1) * 8); + gicconfig = read_gic_config(); + gic_shared_intrs = gicconfig & GIC_CONFIG_NUMINTERRUPTS; + gic_shared_intrs >>= __fls(GIC_CONFIG_NUMINTERRUPTS); + gic_shared_intrs = (gic_shared_intrs + 1) * 8; - gic_vpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >> - GIC_SH_CONFIG_NUMVPES_SHF; + gic_vpes = gicconfig & GIC_CONFIG_PVPS; + gic_vpes >>= __fls(GIC_CONFIG_PVPS); gic_vpes = gic_vpes + 1; if (cpu_has_veic) { diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index ad8b216b6056..f0a60770d775 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -19,8 +19,6 @@ #define GIC_REG(segment, offset) (segment##_##SECTION_OFS + offset##_##OFS) /* GIC Address Space */ -#define SHARED_SECTION_OFS 0x0000 -#define SHARED_SECTION_SIZE 0x8000 #define VPE_LOCAL_SECTION_OFS 0x8000 #define VPE_LOCAL_SECTION_SIZE 0x4000 #define VPE_OTHER_SECTION_OFS 0xc000 @@ -28,15 +26,6 @@ #define USM_VISIBLE_SECTION_OFS 0x10000 #define USM_VISIBLE_SECTION_SIZE 0x10000 -/* Register Map for Shared Section */ - -#define GIC_SH_CONFIG_OFS 0x0000 - -#define GIC_SH_REVISIONID_OFS 0x0020 - -/* Set/Clear corresponding bit in Edge Detect Register */ -#define GIC_SH_WEDGE_OFS 0x0280 - /* Register Map for Local Section */ #define GIC_VPE_CTL_OFS 0x0000 #define GIC_VPE_PEND_OFS 0x0004 @@ -65,15 +54,6 @@ #define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 /* Masks */ -#define GIC_SH_CONFIG_NUMINTRS_SHF 16 -#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF) - -#define GIC_SH_CONFIG_NUMVPES_SHF 0 -#define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF) - -#define GIC_SH_WEDGE_SET(intr) ((intr) | (0x1 << 31)) -#define GIC_SH_WEDGE_CLR(intr) ((intr) & ~(0x1 << 31)) - #define GIC_MAP_SHF 0 #define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF) -- cgit v1.2.3 From 9da3c64589e4eae68631b1b5ed31c586be6ad923 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:25 -0700 Subject: irqchip: mips-gic: Convert local int mask access to new accessors Use the new accessor functions provided by asm/mips-gic.h to access masks controlling local interrupts, resulting in code which is often shorter & easier to read. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17035/ Signed-off-by: Ralf Baechle --- drivers/irqchip/irq-mips-gic.c | 14 +++++------ include/linux/irqchip/mips-gic.h | 52 ---------------------------------------- 2 files changed, 7 insertions(+), 59 deletions(-) (limited to 'include/linux/irqchip') diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index a906284215b7..42d7866c6cd5 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -328,8 +328,8 @@ static void gic_handle_local_int(bool chained) unsigned long pending, masked; unsigned int intr, virq; - pending = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_PEND)); - masked = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_MASK)); + pending = read_gic_vl_pend(); + masked = read_gic_vl_mask(); bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS); @@ -347,14 +347,14 @@ static void gic_mask_local_irq(struct irq_data *d) { int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); - gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr); + write_gic_vl_rmask(BIT(intr)); } static void gic_unmask_local_irq(struct irq_data *d) { int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); - gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr); + write_gic_vl_smask(BIT(intr)); } static struct irq_chip gic_local_irq_controller = { @@ -373,7 +373,7 @@ static void gic_mask_local_irq_all_vpes(struct irq_data *d) for (i = 0; i < gic_vpes; i++) { gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), mips_cm_vp_id(i)); - gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr); + write_gic_vo_rmask(BIT(intr)); } spin_unlock_irqrestore(&gic_lock, flags); } @@ -388,7 +388,7 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d) for (i = 0; i < gic_vpes; i++) { gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), mips_cm_vp_id(i)); - gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr); + write_gic_vo_smask(BIT(intr)); } spin_unlock_irqrestore(&gic_lock, flags); } @@ -432,7 +432,7 @@ static void __init gic_basic_init(void) for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) { if (!gic_local_irq_is_routable(j)) continue; - gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j); + write_gic_vo_rmask(BIT(j)); } } } diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index f0a60770d775..011698962a8d 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -28,10 +28,6 @@ /* Register Map for Local Section */ #define GIC_VPE_CTL_OFS 0x0000 -#define GIC_VPE_PEND_OFS 0x0004 -#define GIC_VPE_MASK_OFS 0x0008 -#define GIC_VPE_RMASK_OFS 0x000c -#define GIC_VPE_SMASK_OFS 0x0010 #define GIC_VPE_TIMER_MAP_OFS 0x0048 #define GIC_VPE_OTHER_ADDR_OFS 0x0080 #define GIC_VPE_WD_CONFIG0_OFS 0x0090 @@ -69,54 +65,6 @@ #define GIC_VPE_CTL_EIC_MODE_SHF 0 #define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF) -/* GIC_VPE_PEND Masks */ -#define GIC_VPE_PEND_WD_SHF 0 -#define GIC_VPE_PEND_WD_MSK (MSK(1) << GIC_VPE_PEND_WD_SHF) -#define GIC_VPE_PEND_CMP_SHF 1 -#define GIC_VPE_PEND_CMP_MSK (MSK(1) << GIC_VPE_PEND_CMP_SHF) -#define GIC_VPE_PEND_TIMER_SHF 2 -#define GIC_VPE_PEND_TIMER_MSK (MSK(1) << GIC_VPE_PEND_TIMER_SHF) -#define GIC_VPE_PEND_PERFCOUNT_SHF 3 -#define GIC_VPE_PEND_PERFCOUNT_MSK (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF) -#define GIC_VPE_PEND_SWINT0_SHF 4 -#define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF) -#define GIC_VPE_PEND_SWINT1_SHF 5 -#define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF) -#define GIC_VPE_PEND_FDC_SHF 6 -#define GIC_VPE_PEND_FDC_MSK (MSK(1) << GIC_VPE_PEND_FDC_SHF) - -/* GIC_VPE_RMASK Masks */ -#define GIC_VPE_RMASK_WD_SHF 0 -#define GIC_VPE_RMASK_WD_MSK (MSK(1) << GIC_VPE_RMASK_WD_SHF) -#define GIC_VPE_RMASK_CMP_SHF 1 -#define GIC_VPE_RMASK_CMP_MSK (MSK(1) << GIC_VPE_RMASK_CMP_SHF) -#define GIC_VPE_RMASK_TIMER_SHF 2 -#define GIC_VPE_RMASK_TIMER_MSK (MSK(1) << GIC_VPE_RMASK_TIMER_SHF) -#define GIC_VPE_RMASK_PERFCNT_SHF 3 -#define GIC_VPE_RMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF) -#define GIC_VPE_RMASK_SWINT0_SHF 4 -#define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF) -#define GIC_VPE_RMASK_SWINT1_SHF 5 -#define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF) -#define GIC_VPE_RMASK_FDC_SHF 6 -#define GIC_VPE_RMASK_FDC_MSK (MSK(1) << GIC_VPE_RMASK_FDC_SHF) - -/* GIC_VPE_SMASK Masks */ -#define GIC_VPE_SMASK_WD_SHF 0 -#define GIC_VPE_SMASK_WD_MSK (MSK(1) << GIC_VPE_SMASK_WD_SHF) -#define GIC_VPE_SMASK_CMP_SHF 1 -#define GIC_VPE_SMASK_CMP_MSK (MSK(1) << GIC_VPE_SMASK_CMP_SHF) -#define GIC_VPE_SMASK_TIMER_SHF 2 -#define GIC_VPE_SMASK_TIMER_MSK (MSK(1) << GIC_VPE_SMASK_TIMER_SHF) -#define GIC_VPE_SMASK_PERFCNT_SHF 3 -#define GIC_VPE_SMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF) -#define GIC_VPE_SMASK_SWINT0_SHF 4 -#define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF) -#define GIC_VPE_SMASK_SWINT1_SHF 5 -#define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF) -#define GIC_VPE_SMASK_FDC_SHF 6 -#define GIC_VPE_SMASK_FDC_MSK (MSK(1) << GIC_VPE_SMASK_FDC_SHF) - /* GIC nomenclature for Core Interrupt Pins. */ #define GIC_CPU_INT0 0 /* Core Interrupt 2 */ #define GIC_CPU_INT1 1 /* . */ -- cgit v1.2.3 From 0d0cf58cd6814ed63deb67fc5f4c27ad725075b1 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:26 -0700 Subject: irqchip: mips-gic: Convert remaining local reg access to new accessors Convert the remaining accesses to registers in the GIC VP-local & VP-other register blocks to use the new accessor functions provided by asm/mips-gic.h, resulting in code which is often shorter & easier to read. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17036/ Signed-off-by: Ralf Baechle --- drivers/irqchip/irq-mips-gic.c | 68 +++++++--------------------------------- include/linux/irqchip/mips-gic.h | 44 -------------------------- 2 files changed, 12 insertions(+), 100 deletions(-) (limited to 'include/linux/irqchip') diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 42d7866c6cd5..ff6c2df86fe8 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -45,42 +45,6 @@ DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS); static void __gic_irq_dispatch(void); -static inline u32 gic_read32(unsigned int reg) -{ - return __raw_readl(mips_gic_base + reg); -} - -static inline u64 gic_read64(unsigned int reg) -{ - return __raw_readq(mips_gic_base + reg); -} - -static inline unsigned long gic_read(unsigned int reg) -{ - if (!mips_cm_is64) - return gic_read32(reg); - else - return gic_read64(reg); -} - -static inline void gic_write32(unsigned int reg, u32 val) -{ - return __raw_writel(val, mips_gic_base + reg); -} - -static inline void gic_write64(unsigned int reg, u64 val) -{ - return __raw_writeq(val, mips_gic_base + reg); -} - -static inline void gic_write(unsigned int reg, unsigned long val) -{ - if (!mips_cm_is64) - return gic_write32(reg, (u32)val); - else - return gic_write64(reg, (u64)val); -} - static bool gic_local_irq_is_routable(int intr) { u32 vpe_ctl; @@ -89,17 +53,17 @@ static bool gic_local_irq_is_routable(int intr) if (cpu_has_veic) return true; - vpe_ctl = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_CTL)); + vpe_ctl = read_gic_vl_ctl(); switch (intr) { case GIC_LOCAL_INT_TIMER: - return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK; + return vpe_ctl & GIC_VX_CTL_TIMER_ROUTABLE; case GIC_LOCAL_INT_PERFCTR: - return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK; + return vpe_ctl & GIC_VX_CTL_PERFCNT_ROUTABLE; case GIC_LOCAL_INT_FDC: - return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK; + return vpe_ctl & GIC_VX_CTL_FDC_ROUTABLE; case GIC_LOCAL_INT_SWINT0: case GIC_LOCAL_INT_SWINT1: - return vpe_ctl & GIC_VPE_CTL_SWINT_RTBL_MSK; + return vpe_ctl & GIC_VX_CTL_SWINT_ROUTABLE; default: return true; } @@ -111,8 +75,7 @@ static void gic_bind_eic_interrupt(int irq, int set) irq -= GIC_PIN_TO_VEC_OFFSET; /* Set irq to use shadow set */ - gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) + - GIC_VPE_EIC_SS(irq), set); + write_gic_vl_eic_shadow_set(irq, set); } static void gic_send_ipi(struct irq_data *d, unsigned int cpu) @@ -371,8 +334,7 @@ static void gic_mask_local_irq_all_vpes(struct irq_data *d) spin_lock_irqsave(&gic_lock, flags); for (i = 0; i < gic_vpes; i++) { - gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), - mips_cm_vp_id(i)); + write_gic_vl_other(mips_cm_vp_id(i)); write_gic_vo_rmask(BIT(intr)); } spin_unlock_irqrestore(&gic_lock, flags); @@ -386,8 +348,7 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d) spin_lock_irqsave(&gic_lock, flags); for (i = 0; i < gic_vpes; i++) { - gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), - mips_cm_vp_id(i)); + write_gic_vl_other(mips_cm_vp_id(i)); write_gic_vo_smask(BIT(intr)); } spin_unlock_irqrestore(&gic_lock, flags); @@ -427,8 +388,7 @@ static void __init gic_basic_init(void) for (i = 0; i < gic_vpes; i++) { unsigned int j; - gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), - mips_cm_vp_id(i)); + write_gic_vl_other(mips_cm_vp_id(i)); for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) { if (!gic_local_irq_is_routable(j)) continue; @@ -712,10 +672,8 @@ static void __init __gic_init(unsigned long gic_base_addr, if (cpu_has_veic) { /* Set EIC mode for all VPEs */ for_each_present_cpu(cpu) { - gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), - mips_cm_vp_id(cpu)); - gic_write(GIC_REG(VPE_OTHER, GIC_VPE_CTL), - GIC_VPE_CTL_EIC_MODE_MSK); + write_gic_vl_other(mips_cm_vp_id(cpu)); + write_gic_vo_ctl(GIC_VX_CTL_EIC); } /* Always use vector 1 in EIC mode */ @@ -740,9 +698,7 @@ static void __init __gic_init(unsigned long gic_base_addr, */ if (IS_ENABLED(CONFIG_MIPS_CMP) && gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) { - timer_cpu_pin = gic_read32(GIC_REG(VPE_LOCAL, - GIC_VPE_TIMER_MAP)) & - GIC_MAP_MSK; + timer_cpu_pin = read_gic_vl_timer_map() & GIC_MAP_PIN_MAP; irq_set_chained_handler(MIPS_CPU_IRQ_BASE + GIC_CPU_PIN_OFFSET + timer_cpu_pin, diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index 011698962a8d..b7a3ce1da9a7 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -13,58 +13,14 @@ #define GIC_MAX_INTRS 256 -#define MSK(n) ((1 << (n)) - 1) - -/* Accessors */ -#define GIC_REG(segment, offset) (segment##_##SECTION_OFS + offset##_##OFS) - /* GIC Address Space */ -#define VPE_LOCAL_SECTION_OFS 0x8000 -#define VPE_LOCAL_SECTION_SIZE 0x4000 -#define VPE_OTHER_SECTION_OFS 0xc000 -#define VPE_OTHER_SECTION_SIZE 0x4000 #define USM_VISIBLE_SECTION_OFS 0x10000 #define USM_VISIBLE_SECTION_SIZE 0x10000 -/* Register Map for Local Section */ -#define GIC_VPE_CTL_OFS 0x0000 -#define GIC_VPE_TIMER_MAP_OFS 0x0048 -#define GIC_VPE_OTHER_ADDR_OFS 0x0080 -#define GIC_VPE_WD_CONFIG0_OFS 0x0090 -#define GIC_VPE_WD_COUNT0_OFS 0x0094 -#define GIC_VPE_WD_INITIAL0_OFS 0x0098 - -#define GIC_VPE_EIC_SHADOW_SET_BASE_OFS 0x0100 -#define GIC_VPE_EIC_SS(intr) (4 * (intr)) - -#define GIC_VPE_EIC_VEC_BASE_OFS 0x0800 -#define GIC_VPE_EIC_VEC(intr) (4 * (intr)) - -#define GIC_VPE_TENABLE_NMI_OFS 0x1000 -#define GIC_VPE_TENABLE_YQ_OFS 0x1004 -#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080 -#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084 - /* User Mode Visible Section Register Map */ #define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000 #define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 -/* Masks */ -#define GIC_MAP_SHF 0 -#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF) - -/* GIC_VPE_CTL Masks */ -#define GIC_VPE_CTL_FDC_RTBL_SHF 4 -#define GIC_VPE_CTL_FDC_RTBL_MSK (MSK(1) << GIC_VPE_CTL_FDC_RTBL_SHF) -#define GIC_VPE_CTL_SWINT_RTBL_SHF 3 -#define GIC_VPE_CTL_SWINT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_SWINT_RTBL_SHF) -#define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2 -#define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF) -#define GIC_VPE_CTL_TIMER_RTBL_SHF 1 -#define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF) -#define GIC_VPE_CTL_EIC_MODE_SHF 0 -#define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF) - /* GIC nomenclature for Core Interrupt Pins. */ #define GIC_CPU_INT0 0 /* Core Interrupt 2 */ #define GIC_CPU_INT1 1 /* . */ -- cgit v1.2.3 From ba9cc4352e9c40ab3b158620a1bd9cd53295ea17 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:27 -0700 Subject: MIPS: GIC: Move GIC_LOCAL_INT_* to asm/mips-gic.h Move the definition of VP-local interrupts provided by the MIPS Global Interrupt Controller to the new asm/mips-gic.h header to be alongside the new accessor functions. Whilst at it, convert to an enum which lends itself more easily to expansion & documentation. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17037/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mips-gic.h | 24 ++++++++++++++++++++++++ include/linux/irqchip/mips-gic.h | 10 ---------- 2 files changed, 24 insertions(+), 10 deletions(-) (limited to 'include/linux/irqchip') diff --git a/arch/mips/include/asm/mips-gic.h b/arch/mips/include/asm/mips-gic.h index 8cf4bdc1a059..27736d7f4aba 100644 --- a/arch/mips/include/asm/mips-gic.h +++ b/arch/mips/include/asm/mips-gic.h @@ -277,6 +277,30 @@ GIC_VX_ACCESSOR_RW(64, 0x0a0, compare) /* GIC_Vx_EIC_SHADOW_SET_BASE - Set shadow register set for each interrupt */ GIC_VX_ACCESSOR_RW_INTR_REG(32, 0x100, 0x4, eic_shadow_set) +/** + * enum mips_gic_local_interrupt - GIC local interrupts + * @GIC_LOCAL_INT_WD: GIC watchdog timer interrupt + * @GIC_LOCAL_INT_COMPARE: GIC count/compare interrupt + * @GIC_LOCAL_INT_TIMER: CP0 count/compare interrupt + * @GIC_LOCAL_INT_PERFCTR: Performance counter interrupt + * @GIC_LOCAL_INT_SWINT0: Software interrupt 0 + * @GIC_LOCAL_INT_SWINT1: Software interrupt 1 + * @GIC_LOCAL_INT_FDC: Fast debug channel interrupt + * @GIC_NUM_LOCAL_INTRS: The number of local interrupts + * + * Enumerates interrupts provided by the GIC that are local to a VP. + */ +enum mips_gic_local_interrupt { + GIC_LOCAL_INT_WD, + GIC_LOCAL_INT_COMPARE, + GIC_LOCAL_INT_TIMER, + GIC_LOCAL_INT_PERFCTR, + GIC_LOCAL_INT_SWINT0, + GIC_LOCAL_INT_SWINT1, + GIC_LOCAL_INT_FDC, + GIC_NUM_LOCAL_INTRS +}; + /** * mips_gic_present() - Determine whether a GIC is present * diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index b7a3ce1da9a7..9546947d1842 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -38,16 +38,6 @@ /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ #define GIC_PIN_TO_VEC_OFFSET 1 -/* Local GIC interrupts. */ -#define GIC_LOCAL_INT_WD 0 /* GIC watchdog */ -#define GIC_LOCAL_INT_COMPARE 1 /* GIC count and compare timer */ -#define GIC_LOCAL_INT_TIMER 2 /* CPU timer interrupt */ -#define GIC_LOCAL_INT_PERFCTR 3 /* CPU performance counter */ -#define GIC_LOCAL_INT_SWINT0 4 /* CPU software interrupt 0 */ -#define GIC_LOCAL_INT_SWINT1 5 /* CPU software interrupt 1 */ -#define GIC_LOCAL_INT_FDC 6 /* CPU fast debug channel */ -#define GIC_NUM_LOCAL_INTRS 7 - /* Convert between local/shared IRQ number and GIC HW IRQ number. */ #define GIC_LOCAL_HWIRQ_BASE 0 #define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x)) -- cgit v1.2.3 From 3ee50dcbef374651056ea42d5eb543bbacb3ff41 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:28 -0700 Subject: irqchip: mips-gic: Remove GIC_CPU_INT* macros The GIC_CPU_INT* macros are never used. Remove the dead code. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17038/ Signed-off-by: Ralf Baechle --- include/linux/irqchip/mips-gic.h | 8 -------- 1 file changed, 8 deletions(-) (limited to 'include/linux/irqchip') diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index 9546947d1842..e93aaf529baa 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -21,14 +21,6 @@ #define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000 #define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 -/* GIC nomenclature for Core Interrupt Pins. */ -#define GIC_CPU_INT0 0 /* Core Interrupt 2 */ -#define GIC_CPU_INT1 1 /* . */ -#define GIC_CPU_INT2 2 /* . */ -#define GIC_CPU_INT3 3 /* . */ -#define GIC_CPU_INT4 4 /* . */ -#define GIC_CPU_INT5 5 /* Core Interrupt 7 */ - /* Add 2 to convert GIC CPU pin to core interrupt */ #define GIC_CPU_PIN_OFFSET 2 -- cgit v1.2.3 From b11d4c1f5a3ac68fa163b0daeca1f98ba328c9de Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:29 -0700 Subject: irqchip: mips-gic: Move various definitions to the driver Move the definitions of macros used to convert between hardware IRQ numbers & shared or local interrupt numbers into the irqchip driver, which is all that should ever need to care about them. Remove GIC_CPU_TO_VEC_OFFSET() in the process since it's never used. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17039/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mips-boards/maltaint.h | 5 ----- drivers/irqchip/irq-mips-gic.c | 16 ++++++++++++++++ include/linux/irqchip/mips-gic.h | 19 ------------------- 3 files changed, 16 insertions(+), 24 deletions(-) (limited to 'include/linux/irqchip') diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h index 987ff580466b..817698abf2eb 100644 --- a/arch/mips/include/asm/mips-boards/maltaint.h +++ b/arch/mips/include/asm/mips-boards/maltaint.h @@ -10,8 +10,6 @@ #ifndef _MIPS_MALTAINT_H #define _MIPS_MALTAINT_H -#include - /* * Interrupts 0..15 are used for Malta ISA compatible interrupts */ @@ -62,7 +60,4 @@ #define MSC01E_INT_PERFCTR 10 #define MSC01E_INT_CPUCTR 11 -/* GIC external interrupts */ -#define GIC_INT_I8259A GIC_SHARED_TO_HWIRQ(3) - #endif /* !(_MIPS_MALTAINT_H) */ diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index ff6c2df86fe8..6e303df56447 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -23,6 +23,22 @@ #include +#define GIC_MAX_INTRS 256 + +/* Add 2 to convert GIC CPU pin to core interrupt */ +#define GIC_CPU_PIN_OFFSET 2 + +/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ +#define GIC_PIN_TO_VEC_OFFSET 1 + +/* Convert between local/shared IRQ number and GIC HW IRQ number. */ +#define GIC_LOCAL_HWIRQ_BASE 0 +#define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x)) +#define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE) +#define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS +#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x)) +#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE) + unsigned int gic_present; void __iomem *mips_gic_base; diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index e93aaf529baa..da02a146b292 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -11,8 +11,6 @@ #include #include -#define GIC_MAX_INTRS 256 - /* GIC Address Space */ #define USM_VISIBLE_SECTION_OFS 0x10000 #define USM_VISIBLE_SECTION_SIZE 0x10000 @@ -21,23 +19,6 @@ #define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000 #define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 -/* Add 2 to convert GIC CPU pin to core interrupt */ -#define GIC_CPU_PIN_OFFSET 2 - -/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */ -#define GIC_CPU_TO_VEC_OFFSET 2 - -/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ -#define GIC_PIN_TO_VEC_OFFSET 1 - -/* Convert between local/shared IRQ number and GIC HW IRQ number. */ -#define GIC_LOCAL_HWIRQ_BASE 0 -#define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x)) -#define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE) -#define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS -#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x)) -#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE) - #ifdef CONFIG_MIPS_GIC extern unsigned int gic_present; -- cgit v1.2.3 From 84103814a2cfd3561ff00bd7317c22f40f9e0dad Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:31 -0700 Subject: irqchip: mips-gic: Remove gic_get_usm_range() The MIPS VDSO code is no longer reliant upon the irqchip driver to provide the address of the GIC's user-visible section via gic_get_usm_range(). Remove the now-dead code. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17041/ Signed-off-by: Ralf Baechle --- drivers/irqchip/irq-mips-gic.c | 14 -------------- include/linux/irqchip/mips-gic.h | 11 ----------- 2 files changed, 25 deletions(-) (limited to 'include/linux/irqchip') diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 6e303df56447..3e4c79e921e3 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -46,7 +46,6 @@ struct gic_pcpu_mask { DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS); }; -static unsigned long __gic_base_addr; static struct gic_pcpu_mask pcpu_masks[NR_CPUS]; static DEFINE_SPINLOCK(gic_lock); static struct irq_domain *gic_irq_domain; @@ -134,17 +133,6 @@ int gic_get_c0_fdc_int(void) GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC)); } -int gic_get_usm_range(struct resource *gic_usm_res) -{ - if (!gic_present) - return -1; - - gic_usm_res->start = __gic_base_addr + USM_VISIBLE_SECTION_OFS; - gic_usm_res->end = gic_usm_res->start + (USM_VISIBLE_SECTION_SIZE - 1); - - return 0; -} - static void gic_handle_shared_int(bool chained) { unsigned int intr, virq; @@ -672,8 +660,6 @@ static void __init __gic_init(unsigned long gic_base_addr, unsigned int gicconfig, cpu; unsigned int v[2]; - __gic_base_addr = gic_base_addr; - mips_gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size); gicconfig = read_gic_config(); diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index da02a146b292..843e1bb49767 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -11,10 +11,6 @@ #include #include -/* GIC Address Space */ -#define USM_VISIBLE_SECTION_OFS 0x10000 -#define USM_VISIBLE_SECTION_SIZE 0x10000 - /* User Mode Visible Section Register Map */ #define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000 #define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 @@ -29,18 +25,11 @@ extern void gic_init(unsigned long gic_base_addr, extern int gic_get_c0_compare_int(void); extern int gic_get_c0_perfcount_int(void); extern int gic_get_c0_fdc_int(void); -extern int gic_get_usm_range(struct resource *gic_usm_res); #else /* CONFIG_MIPS_GIC */ #define gic_present 0 -static inline int gic_get_usm_range(struct resource *gic_usm_res) -{ - /* Shouldn't be called. */ - return -1; -} - #endif /* CONFIG_MIPS_GIC */ #endif /* __LINUX_IRQCHIP_MIPS_GIC_H */ -- cgit v1.2.3 From 85eec73ce4c4322b3b442b9582f6656abb5d125f Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:33 -0700 Subject: irqchip: mips-gic: Remove gic_init() All in-tree platforms now probe the GIC driver using device tree, and as such nothing calls gic_init() any longer. Remove the dead code. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17043/ Signed-off-by: Ralf Baechle --- drivers/irqchip/irq-mips-gic.c | 7 ------- include/linux/irqchip/mips-gic.h | 3 --- 2 files changed, 10 deletions(-) (limited to 'include/linux/irqchip') diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 462c2e509714..4ef3f53225ca 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -737,13 +737,6 @@ static void __init __gic_init(unsigned long gic_base_addr, gic_basic_init(); } -void __init gic_init(unsigned long gic_base_addr, - unsigned long gic_addrspace_size, - unsigned int cpu_vec, unsigned int irqbase) -{ - __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL); -} - static int __init gic_of_init(struct device_node *node, struct device_node *parent) { diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index 843e1bb49767..63c5f87034c9 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -19,9 +19,6 @@ extern unsigned int gic_present; -extern void gic_init(unsigned long gic_base_addr, - unsigned long gic_addrspace_size, unsigned int cpu_vec, - unsigned int irqbase); extern int gic_get_c0_compare_int(void); extern int gic_get_c0_perfcount_int(void); extern int gic_get_c0_fdc_int(void); -- cgit v1.2.3 From 56d7b61dc6d4e13cef786c8e4a2bfe43e4db932d Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:35 -0700 Subject: irqchip: mips-gic: Remove gic_present Nothing uses the global gic_present variable anymore; mips_gic_present() should be used instead. Remove the dead code. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17045/ Signed-off-by: Ralf Baechle --- drivers/irqchip/irq-mips-gic.c | 2 -- include/linux/irqchip/mips-gic.h | 6 ------ 2 files changed, 8 deletions(-) (limited to 'include/linux/irqchip') diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 4ef3f53225ca..b444bef6d3c2 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -39,7 +39,6 @@ #define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x)) #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE) -unsigned int gic_present; void __iomem *mips_gic_base; struct gic_pcpu_mask { @@ -781,7 +780,6 @@ static int __init gic_of_init(struct device_node *node, /* Ensure GIC region is enabled before trying to access it */ __sync(); } - gic_present = true; __gic_init(gic_base, gic_len, cpu_vec, 0, node); diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index 63c5f87034c9..113010c8dd8b 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -17,16 +17,10 @@ #ifdef CONFIG_MIPS_GIC -extern unsigned int gic_present; - extern int gic_get_c0_compare_int(void); extern int gic_get_c0_perfcount_int(void); extern int gic_get_c0_fdc_int(void); -#else /* CONFIG_MIPS_GIC */ - -#define gic_present 0 - #endif /* CONFIG_MIPS_GIC */ #endif /* __LINUX_IRQCHIP_MIPS_GIC_H */ -- cgit v1.2.3 From dd0163508c07a67b28befe5af23d7ab9941ae8ca Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:36 -0700 Subject: irqchip: mips-gic: Move gic_get_c0_*_int() to asm/mips-gic.h The linux/irqchip/mips-gic.h header is now almost empty. Move the declarations of gic_get_c0_compare_int(), gic_get_c0_perfcount_int() & gic_get_c0_fdc_int() to asm/mips-gic.h in order to close in on being able to delete the former header. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17046/ Signed-off-by: Ralf Baechle --- arch/mips/generic/irq.c | 1 - arch/mips/include/asm/mips-gic.h | 30 ++++++++++++++++++++++++++++++ arch/mips/mti-malta/malta-time.c | 1 - arch/mips/pistachio/time.c | 2 +- arch/mips/ralink/irq-gic.c | 2 +- drivers/irqchip/irq-mips-gic.c | 1 - include/linux/irqchip/mips-gic.h | 8 -------- 7 files changed, 32 insertions(+), 13 deletions(-) (limited to 'include/linux/irqchip') diff --git a/arch/mips/generic/irq.c b/arch/mips/generic/irq.c index 2d7bf74179d5..5322d09dd51b 100644 --- a/arch/mips/generic/irq.c +++ b/arch/mips/generic/irq.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/include/asm/mips-gic.h b/arch/mips/include/asm/mips-gic.h index 27736d7f4aba..a2badf572632 100644 --- a/arch/mips/include/asm/mips-gic.h +++ b/arch/mips/include/asm/mips-gic.h @@ -314,4 +314,34 @@ static inline bool mips_gic_present(void) return IS_ENABLED(CONFIG_MIPS_GIC) && mips_gic_base; } +/** + * gic_get_c0_compare_int() - Return cp0 count/compare interrupt virq + * + * Determine the virq number to use for the coprocessor 0 count/compare + * interrupt, which may be routed via the GIC. + * + * Returns the virq number or a negative error number. + */ +extern int gic_get_c0_compare_int(void); + +/** + * gic_get_c0_perfcount_int() - Return performance counter interrupt virq + * + * Determine the virq number to use for CPU performance counter interrupts, + * which may be routed via the GIC. + * + * Returns the virq number or a negative error number. + */ +extern int gic_get_c0_perfcount_int(void); + +/** + * gic_get_c0_fdc_int() - Return fast debug channel interrupt virq + * + * Determine the virq number to use for fast debug channel (FDC) interrupts, + * which may be routed via the GIC. + * + * Returns the virq number or a negative error number. + */ +extern int gic_get_c0_fdc_int(void); + #endif /* __MIPS_ASM_MIPS_CPS_H__ */ diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c index 7d53103b085f..66c866740ff2 100644 --- a/arch/mips/mti-malta/malta-time.c +++ b/arch/mips/mti-malta/malta-time.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include diff --git a/arch/mips/pistachio/time.c b/arch/mips/pistachio/time.c index 17a0f1dec05b..8a6af9b76202 100644 --- a/arch/mips/pistachio/time.c +++ b/arch/mips/pistachio/time.c @@ -12,9 +12,9 @@ #include #include #include -#include #include +#include #include unsigned int get_c0_compare_int(void) diff --git a/arch/mips/ralink/irq-gic.c b/arch/mips/ralink/irq-gic.c index 2058280450b5..bda576f2cad8 100644 --- a/arch/mips/ralink/irq-gic.c +++ b/arch/mips/ralink/irq-gic.c @@ -11,7 +11,7 @@ #include #include -#include +#include int get_c0_perfcount_int(void) { diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index b444bef6d3c2..bbf39dcfeda4 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index 113010c8dd8b..277d5be03a57 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -15,12 +15,4 @@ #define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000 #define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 -#ifdef CONFIG_MIPS_GIC - -extern int gic_get_c0_compare_int(void); -extern int gic_get_c0_perfcount_int(void); -extern int gic_get_c0_fdc_int(void); - -#endif /* CONFIG_MIPS_GIC */ - #endif /* __LINUX_IRQCHIP_MIPS_GIC_H */ -- cgit v1.2.3 From 16ae123e89d603a69d980bd76c4bb686f219ba0e Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:37 -0700 Subject: MIPS: VDSO: Avoid use of linux/irqchip/mips-gic.h Our VDSO code makes use of macros from linux/irqchip/mips-gic.h to provide offsets to register values, but these are trivial offsets to the two 32 bit halves of a 64 bit value. Replace use of the macros with zero (ie. omit adding an offset) and the size of the low 32 bit of the value. This removes our need for linux/irqchip/mips-gic.h & prepares us for it to be removed. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17047/ Signed-off-by: Ralf Baechle --- arch/mips/vdso/gettimeofday.c | 7 +++---- include/linux/irqchip/mips-gic.h | 4 ---- 2 files changed, 3 insertions(+), 8 deletions(-) (limited to 'include/linux/irqchip') diff --git a/arch/mips/vdso/gettimeofday.c b/arch/mips/vdso/gettimeofday.c index fec7835b9de7..e22b422f282c 100644 --- a/arch/mips/vdso/gettimeofday.c +++ b/arch/mips/vdso/gettimeofday.c @@ -11,7 +11,6 @@ #include "vdso.h" #include -#include #include #include @@ -125,9 +124,9 @@ static __always_inline u64 read_gic_count(const union mips_vdso_data *data) u32 hi, hi2, lo; do { - hi = __raw_readl(gic + GIC_UMV_SH_COUNTER_63_32_OFS); - lo = __raw_readl(gic + GIC_UMV_SH_COUNTER_31_00_OFS); - hi2 = __raw_readl(gic + GIC_UMV_SH_COUNTER_63_32_OFS); + hi = __raw_readl(gic + sizeof(lo)); + lo = __raw_readl(gic); + hi2 = __raw_readl(gic + sizeof(lo)); } while (hi2 != hi); return (((u64)hi) << 32) + lo; diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index 277d5be03a57..6e6c9adea049 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -11,8 +11,4 @@ #include #include -/* User Mode Visible Section Register Map */ -#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000 -#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 - #endif /* __LINUX_IRQCHIP_MIPS_GIC_H */ -- cgit v1.2.3 From 1fad12cd5ef43755d028f760fa089c87f5533451 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 12 Aug 2017 21:36:39 -0700 Subject: irqchip: mips-gic: Remove linux/irqchip/mips-gic.h The linux/irqchip/mips-gic.h header is no longer used. Remove it. Signed-off-by: Paul Burton Acked-by: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17049/ Signed-off-by: Ralf Baechle --- include/linux/irqchip/mips-gic.h | 14 -------------- 1 file changed, 14 deletions(-) delete mode 100644 include/linux/irqchip/mips-gic.h (limited to 'include/linux/irqchip') diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h deleted file mode 100644 index 6e6c9adea049..000000000000 --- a/include/linux/irqchip/mips-gic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000, 07 MIPS Technologies, Inc. - */ -#ifndef __LINUX_IRQCHIP_MIPS_GIC_H -#define __LINUX_IRQCHIP_MIPS_GIC_H - -#include -#include - -#endif /* __LINUX_IRQCHIP_MIPS_GIC_H */ -- cgit v1.2.3