From 58a2b4c9bdf98452fec95bb1a5eeed60c01f621a Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Thu, 18 Apr 2019 13:12:05 +0200 Subject: clk: fractional-divider: add explicit big endian support Add a clock specific flag to switch register accesses to big endian, to allow runtime configuration of big endian fractional divider clocks. Signed-off-by: Jonas Gorski Signed-off-by: Stephen Boyd --- include/linux/clk-provider.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/linux/clk-provider.h') diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index f0abdfbe3d60..7c6861995505 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -606,6 +606,9 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw); * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED * is set then the numerator and denominator are both the value read * plus one. + * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are + * used for the divider register. Setting this flag makes the register + * accesses big endian. */ struct clk_fractional_divider { struct clk_hw hw; @@ -626,6 +629,7 @@ struct clk_fractional_divider { #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) +#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1) extern const struct clk_ops clk_fractional_divider_ops; struct clk *clk_register_fractional_divider(struct device *dev, -- cgit v1.2.3