From 2aae5eaa941e356b5f6e78c207c7dc3a93286622 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 20 Apr 2023 19:32:50 +0200 Subject: dt-bindings: clock: Add SM8350 VIDEOCC SM8350, like most recent higher-end chips has a separate clock controller block just for the Venus IP. Document it. The binding was separated as the driver, unlike the earlier ones, doesn't expect clock-names to keep it easier to maintain. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230413-topic-lahaina_vidcc-v4-1-86c714a66a81@linaro.org --- include/dt-bindings/reset/qcom,sm8350-videocc.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 include/dt-bindings/reset/qcom,sm8350-videocc.h (limited to 'include/dt-bindings/reset') diff --git a/include/dt-bindings/reset/qcom,sm8350-videocc.h b/include/dt-bindings/reset/qcom,sm8350-videocc.h new file mode 100644 index 000000000000..cd356b207a4a --- /dev/null +++ b/include/dt-bindings/reset/qcom,sm8350-videocc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H +#define _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H + +#define VIDEO_CC_CVP_INTERFACE_BCR 0 +#define VIDEO_CC_CVP_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_CLK_ARES 2 +#define VIDEO_CC_CVP_MVS0C_BCR 3 +#define VIDEO_CC_CVP_MVS1_BCR 4 +#define VIDEO_CC_MVS1C_CLK_ARES 5 +#define VIDEO_CC_CVP_MVS1C_BCR 6 + +#endif -- cgit v1.2.3