From fd43fe19b830d6cd0eba08a6c6a5f71a6bd9c1b0 Mon Sep 17 00:00:00 2001 From: Chris Zankel Date: Sun, 10 Dec 2006 02:18:47 -0800 Subject: [PATCH] xtensa: fix irq and misc fixes Update the architecture specific interrupt handling code for Xtensa to support the new API. Use generic BUG macros in bug.h, and some minor fixes. Signed-off-by: Chris Zankel Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/asm-xtensa/byteorder.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/asm-xtensa/byteorder.h') diff --git a/include/asm-xtensa/byteorder.h b/include/asm-xtensa/byteorder.h index 0b1552569aae..0ba72ddbf889 100644 --- a/include/asm-xtensa/byteorder.h +++ b/include/asm-xtensa/byteorder.h @@ -14,7 +14,7 @@ #include #include -static __inline__ __const__ __u32 ___arch__swab32(__u32 x) +static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) { __u32 res; /* instruction sequence from Xtensa ISA release 2/2000 */ @@ -29,7 +29,7 @@ static __inline__ __const__ __u32 ___arch__swab32(__u32 x) return res; } -static __inline__ __const__ __u16 ___arch__swab16(__u16 x) +static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) { /* Given that 'short' values are signed (i.e., can be negative), * we cannot assume that the upper 16-bits of the register are -- cgit v1.2.3