From 6399c94f4b90890de9fcaf56bad113d21cba7e8d Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 5 Jun 2024 14:18:26 +0300 Subject: drm/i915: Use REG_BIT() for bdw+ pipe interrupts MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace the hand rolled (1< Link: https://patchwork.freedesktop.org/patch/msgid/20240605111832.21373-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 54 ++++++++++++++++++++--------------------- 1 file changed, 27 insertions(+), 27 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8e4478194d11..02554a0fccc6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2499,33 +2499,33 @@ #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) -#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) -#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) -#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) -#define XELPD_PIPE_SOFT_UNDERRUN (1 << 22) -#define XELPD_PIPE_HARD_UNDERRUN (1 << 21) -#define GEN12_PIPE_VBLANK_UNMOD (1 << 19) -#define GEN8_PIPE_CURSOR_FAULT (1 << 10) -#define GEN8_PIPE_SPRITE_FAULT (1 << 9) -#define GEN8_PIPE_PRIMARY_FAULT (1 << 8) -#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) -#define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) -#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) -#define GEN8_PIPE_VSYNC (1 << 1) -#define GEN8_PIPE_VBLANK (1 << 0) -#define GEN9_PIPE_CURSOR_FAULT (1 << 11) -#define GEN11_PIPE_PLANE7_FAULT (1 << 22) -#define GEN11_PIPE_PLANE6_FAULT (1 << 21) -#define GEN11_PIPE_PLANE5_FAULT (1 << 20) -#define GEN9_PIPE_PLANE4_FAULT (1 << 10) -#define GEN9_PIPE_PLANE3_FAULT (1 << 9) -#define GEN9_PIPE_PLANE2_FAULT (1 << 8) -#define GEN9_PIPE_PLANE1_FAULT (1 << 7) -#define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) -#define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) -#define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) -#define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) -#define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) +#define GEN8_PIPE_FIFO_UNDERRUN REG_BIT(31) +#define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29) +#define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28) +#define XELPD_PIPE_SOFT_UNDERRUN REG_BIT(22) +#define XELPD_PIPE_HARD_UNDERRUN REG_BIT(21) +#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) +#define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) +#define GEN8_PIPE_SPRITE_FAULT REG_BIT(9) +#define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) +#define GEN8_PIPE_SPRITE_FLIP_DONE REG_BIT(5) +#define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) +#define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2) +#define GEN8_PIPE_VSYNC REG_BIT(1) +#define GEN8_PIPE_VBLANK REG_BIT(0) +#define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) +#define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) +#define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) +#define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) +#define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) +#define GEN9_PIPE_PLANE3_FAULT REG_BIT(9) +#define GEN9_PIPE_PLANE2_FAULT REG_BIT(8) +#define GEN9_PIPE_PLANE1_FAULT REG_BIT(7) +#define GEN9_PIPE_PLANE4_FLIP_DONE REG_BIT(6) +#define GEN9_PIPE_PLANE3_FLIP_DONE REG_BIT(5) +#define GEN9_PIPE_PLANE2_FLIP_DONE REG_BIT(4) +#define GEN9_PIPE_PLANE1_FLIP_DONE REG_BIT(3) +#define GEN9_PIPE_PLANE_FLIP_DONE(p) REG_BIT(3 + (p)) #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ (GEN8_PIPE_CURSOR_FAULT | \ GEN8_PIPE_SPRITE_FAULT | \ -- cgit v1.2.3 From 9994be5584292aa37aff667d9e6821691d9840ed Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 5 Jun 2024 14:18:27 +0300 Subject: drm/i915: Document bdw+ pipe interrupt bits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sprinkle some notes indicating which platforms have which pipe interrupt bits. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240605111832.21373-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 42 ++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 02554a0fccc6..caeeecc516e2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2502,30 +2502,30 @@ #define GEN8_PIPE_FIFO_UNDERRUN REG_BIT(31) #define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29) #define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28) -#define XELPD_PIPE_SOFT_UNDERRUN REG_BIT(22) -#define XELPD_PIPE_HARD_UNDERRUN REG_BIT(21) -#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) -#define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) -#define GEN8_PIPE_SPRITE_FAULT REG_BIT(9) -#define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) -#define GEN8_PIPE_SPRITE_FLIP_DONE REG_BIT(5) -#define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) +#define XELPD_PIPE_SOFT_UNDERRUN REG_BIT(22) /* adl/dg2+ */ +#define XELPD_PIPE_HARD_UNDERRUN REG_BIT(21) /* adl/dg2+ */ +#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */ +#define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */ +#define GEN8_PIPE_SPRITE_FAULT REG_BIT(9) /* bdw */ +#define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) /* bdw */ +#define GEN8_PIPE_SPRITE_FLIP_DONE REG_BIT(5) /* bdw */ +#define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */ #define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2) #define GEN8_PIPE_VSYNC REG_BIT(1) #define GEN8_PIPE_VBLANK REG_BIT(0) -#define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) -#define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) -#define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) -#define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) -#define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) -#define GEN9_PIPE_PLANE3_FAULT REG_BIT(9) -#define GEN9_PIPE_PLANE2_FAULT REG_BIT(8) -#define GEN9_PIPE_PLANE1_FAULT REG_BIT(7) -#define GEN9_PIPE_PLANE4_FLIP_DONE REG_BIT(6) -#define GEN9_PIPE_PLANE3_FLIP_DONE REG_BIT(5) -#define GEN9_PIPE_PLANE2_FLIP_DONE REG_BIT(4) -#define GEN9_PIPE_PLANE1_FLIP_DONE REG_BIT(3) -#define GEN9_PIPE_PLANE_FLIP_DONE(p) REG_BIT(3 + (p)) +#define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */ +#define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */ +#define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */ +#define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */ +#define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */ +#define GEN9_PIPE_PLANE3_FAULT REG_BIT(9) /* skl+ */ +#define GEN9_PIPE_PLANE2_FAULT REG_BIT(8) /* skl+ */ +#define GEN9_PIPE_PLANE1_FAULT REG_BIT(7) /* skl+ */ +#define GEN9_PIPE_PLANE4_FLIP_DONE REG_BIT(6) /* skl+ */ +#define GEN9_PIPE_PLANE3_FLIP_DONE REG_BIT(5) /* skl+ */ +#define GEN9_PIPE_PLANE2_FLIP_DONE REG_BIT(4) /* skl+ */ +#define GEN9_PIPE_PLANE1_FLIP_DONE REG_BIT(3) /* skl+ */ +#define GEN9_PIPE_PLANE_FLIP_DONE(p) REG_BIT(3 + (p)) /* skl+ */ #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ (GEN8_PIPE_CURSOR_FAULT | \ GEN8_PIPE_SPRITE_FAULT | \ -- cgit v1.2.3 From ad738e488981603a74d35ef3106e38b891bdfb7e Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 5 Jun 2024 14:18:28 +0300 Subject: drm/i915: Sort bdw+ pipe interrupt bits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's really hard to figure out which bdw+ pipe interrupt bits we've defined and which we have not. Sort the defines to make that a bit easier (still not super easy since the bits have been shuffled a bit over the years). Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240605111832.21373-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index caeeecc516e2..01112d15b86c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2503,29 +2503,29 @@ #define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29) #define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28) #define XELPD_PIPE_SOFT_UNDERRUN REG_BIT(22) /* adl/dg2+ */ -#define XELPD_PIPE_HARD_UNDERRUN REG_BIT(21) /* adl/dg2+ */ -#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */ -#define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */ -#define GEN8_PIPE_SPRITE_FAULT REG_BIT(9) /* bdw */ -#define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) /* bdw */ -#define GEN8_PIPE_SPRITE_FLIP_DONE REG_BIT(5) /* bdw */ -#define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */ -#define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2) -#define GEN8_PIPE_VSYNC REG_BIT(1) -#define GEN8_PIPE_VBLANK REG_BIT(0) -#define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */ #define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */ +#define XELPD_PIPE_HARD_UNDERRUN REG_BIT(21) /* adl/dg2+ */ #define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */ #define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */ +#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */ +#define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */ #define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */ +#define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */ #define GEN9_PIPE_PLANE3_FAULT REG_BIT(9) /* skl+ */ +#define GEN8_PIPE_SPRITE_FAULT REG_BIT(9) /* bdw */ #define GEN9_PIPE_PLANE2_FAULT REG_BIT(8) /* skl+ */ +#define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) /* bdw */ #define GEN9_PIPE_PLANE1_FAULT REG_BIT(7) /* skl+ */ #define GEN9_PIPE_PLANE4_FLIP_DONE REG_BIT(6) /* skl+ */ #define GEN9_PIPE_PLANE3_FLIP_DONE REG_BIT(5) /* skl+ */ +#define GEN8_PIPE_SPRITE_FLIP_DONE REG_BIT(5) /* bdw */ #define GEN9_PIPE_PLANE2_FLIP_DONE REG_BIT(4) /* skl+ */ +#define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */ #define GEN9_PIPE_PLANE1_FLIP_DONE REG_BIT(3) /* skl+ */ #define GEN9_PIPE_PLANE_FLIP_DONE(p) REG_BIT(3 + (p)) /* skl+ */ +#define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2) +#define GEN8_PIPE_VSYNC REG_BIT(1) +#define GEN8_PIPE_VBLANK REG_BIT(0) #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ (GEN8_PIPE_CURSOR_FAULT | \ GEN8_PIPE_SPRITE_FAULT | \ -- cgit v1.2.3 From fa63577ff38bf0d828d772b807ac082a55401495 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 5 Jun 2024 14:18:29 +0300 Subject: drm/i915: Extend GEN9_PIPE_PLANE_FLIP_DONE() to cover all universal planes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit GEN9_PIPE_PLANE_FLIP_DONE() only works for planes 1-4. Extend it handle planes 5-7 as well. Somewhat annoyingly the bits are spread around into two distinct clumps. Currently this doesn't achieve anything, but if we ever extend async flip support to more than just the first plane then we'll need this. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240605111832.21373-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 01112d15b86c..2bb1c268b475 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2508,6 +2508,9 @@ #define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */ #define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */ #define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */ +#define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */ +#define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */ +#define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */ #define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */ #define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */ #define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */ @@ -2522,7 +2525,8 @@ #define GEN9_PIPE_PLANE2_FLIP_DONE REG_BIT(4) /* skl+ */ #define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */ #define GEN9_PIPE_PLANE1_FLIP_DONE REG_BIT(3) /* skl+ */ -#define GEN9_PIPE_PLANE_FLIP_DONE(p) REG_BIT(3 + (p)) /* skl+ */ +#define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) \ + REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */ #define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2) #define GEN8_PIPE_VSYNC REG_BIT(1) #define GEN8_PIPE_VBLANK REG_BIT(0) -- cgit v1.2.3 From ba30cd246f10cdac784df096b95e00b33116d161 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 5 Jun 2024 14:18:30 +0300 Subject: drm/i915: Nuke the intermediate pipe fault bitmasks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit GEN8_DE_PIPE_IRQ_FAULT_ERRORS & co. don't really achieve anything. Get rid of them and just declare all the bits directly in gen8_de_pipe_fault_mask(). Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240605111832.21373-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 26 ++++++++++++++++++++---- drivers/gpu/drm/i915/i915_reg.h | 18 ---------------- 2 files changed, 22 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 82e1369e5d76..2b1aaf5c715b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -837,13 +837,31 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv) static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv) { if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv)) - return RKL_DE_PIPE_IRQ_FAULT_ERRORS; + return GEN9_PIPE_CURSOR_FAULT | + GEN11_PIPE_PLANE5_FAULT | + GEN9_PIPE_PLANE4_FAULT | + GEN9_PIPE_PLANE3_FAULT | + GEN9_PIPE_PLANE2_FAULT | + GEN9_PIPE_PLANE1_FAULT; else if (DISPLAY_VER(dev_priv) >= 11) - return GEN11_DE_PIPE_IRQ_FAULT_ERRORS; + return GEN9_PIPE_CURSOR_FAULT | + GEN11_PIPE_PLANE7_FAULT | + GEN11_PIPE_PLANE6_FAULT | + GEN11_PIPE_PLANE5_FAULT | + GEN9_PIPE_PLANE4_FAULT | + GEN9_PIPE_PLANE3_FAULT | + GEN9_PIPE_PLANE2_FAULT | + GEN9_PIPE_PLANE1_FAULT; else if (DISPLAY_VER(dev_priv) >= 9) - return GEN9_DE_PIPE_IRQ_FAULT_ERRORS; + return GEN9_PIPE_CURSOR_FAULT | + GEN9_PIPE_PLANE4_FAULT | + GEN9_PIPE_PLANE3_FAULT | + GEN9_PIPE_PLANE2_FAULT | + GEN9_PIPE_PLANE1_FAULT; else - return GEN8_DE_PIPE_IRQ_FAULT_ERRORS; + return GEN8_PIPE_CURSOR_FAULT | + GEN8_PIPE_SPRITE_FAULT | + GEN8_PIPE_PRIMARY_FAULT; } static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2bb1c268b475..6b4ab3ccc3e0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2530,24 +2530,6 @@ #define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2) #define GEN8_PIPE_VSYNC REG_BIT(1) #define GEN8_PIPE_VBLANK REG_BIT(0) -#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ - (GEN8_PIPE_CURSOR_FAULT | \ - GEN8_PIPE_SPRITE_FAULT | \ - GEN8_PIPE_PRIMARY_FAULT) -#define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ - (GEN9_PIPE_CURSOR_FAULT | \ - GEN9_PIPE_PLANE4_FAULT | \ - GEN9_PIPE_PLANE3_FAULT | \ - GEN9_PIPE_PLANE2_FAULT | \ - GEN9_PIPE_PLANE1_FAULT) -#define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \ - (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ - GEN11_PIPE_PLANE7_FAULT | \ - GEN11_PIPE_PLANE6_FAULT | \ - GEN11_PIPE_PLANE5_FAULT) -#define RKL_DE_PIPE_IRQ_FAULT_ERRORS \ - (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ - GEN11_PIPE_PLANE5_FAULT) #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1) -- cgit v1.2.3 From a669b81328cb09474bc7bee56ccca499457900ba Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 5 Jun 2024 14:18:31 +0300 Subject: drm/i915: Enable pipeDMC fault interrupts on tgl+ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PipeDMC has its own fault interrupt. Enable that so that we can know if things are failing. While at it, define the other pipeDMC interrupt as well, even though we're not currently using it. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240605111832.21373-7-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 15 +++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 15 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 2b1aaf5c715b..e255b4fdd37d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -837,13 +837,24 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv) static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv) { if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv)) - return GEN9_PIPE_CURSOR_FAULT | + return GEN12_PIPEDMC_FAULT | + GEN9_PIPE_CURSOR_FAULT | + GEN11_PIPE_PLANE5_FAULT | + GEN9_PIPE_PLANE4_FAULT | + GEN9_PIPE_PLANE3_FAULT | + GEN9_PIPE_PLANE2_FAULT | + GEN9_PIPE_PLANE1_FAULT; + else if (DISPLAY_VER(dev_priv) == 12) + return GEN12_PIPEDMC_FAULT | + GEN9_PIPE_CURSOR_FAULT | + GEN11_PIPE_PLANE7_FAULT | + GEN11_PIPE_PLANE6_FAULT | GEN11_PIPE_PLANE5_FAULT | GEN9_PIPE_PLANE4_FAULT | GEN9_PIPE_PLANE3_FAULT | GEN9_PIPE_PLANE2_FAULT | GEN9_PIPE_PLANE1_FAULT; - else if (DISPLAY_VER(dev_priv) >= 11) + else if (DISPLAY_VER(dev_priv) == 11) return GEN9_PIPE_CURSOR_FAULT | GEN11_PIPE_PLANE7_FAULT | GEN11_PIPE_PLANE6_FAULT | diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6b4ab3ccc3e0..bc838ecbbf8a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2502,6 +2502,8 @@ #define GEN8_PIPE_FIFO_UNDERRUN REG_BIT(31) #define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29) #define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28) +#define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */ +#define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl+ */ #define XELPD_PIPE_SOFT_UNDERRUN REG_BIT(22) /* adl/dg2+ */ #define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */ #define XELPD_PIPE_HARD_UNDERRUN REG_BIT(21) /* adl/dg2+ */ -- cgit v1.2.3 From 851de367dede776180e6c4c709089bc8becbb53a Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 5 Jun 2024 14:18:32 +0300 Subject: drm/i915: Enable plane/pipeDMC ATS fault interrupts on mtl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MTL has some new IOMMU thing that has a few new fault interrupts. Enable those so we can know if things are going poorly. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240605111832.21373-8-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 10 ++++++++++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 12 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index e255b4fdd37d..67b19d04d1f7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -836,6 +836,16 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv) static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv) { + if (DISPLAY_VER(dev_priv) >= 14) + return MTL_PIPEDMC_ATS_FAULT | + MTL_PLANE_ATS_FAULT | + GEN12_PIPEDMC_FAULT | + GEN9_PIPE_CURSOR_FAULT | + GEN11_PIPE_PLANE5_FAULT | + GEN9_PIPE_PLANE4_FAULT | + GEN9_PIPE_PLANE3_FAULT | + GEN9_PIPE_PLANE2_FAULT | + GEN9_PIPE_PLANE1_FAULT; if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv)) return GEN12_PIPEDMC_FAULT | GEN9_PIPE_CURSOR_FAULT | diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index bc838ecbbf8a..0e3d79227e3c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2504,12 +2504,14 @@ #define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28) #define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */ #define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl+ */ +#define MTL_PIPEDMC_ATS_FAULT REG_BIT(24) /* mtl+ */ #define XELPD_PIPE_SOFT_UNDERRUN REG_BIT(22) /* adl/dg2+ */ #define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */ #define XELPD_PIPE_HARD_UNDERRUN REG_BIT(21) /* adl/dg2+ */ #define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */ #define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */ #define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */ +#define MTL_PLANE_ATS_FAULT REG_BIT(18) /* mtl+ */ #define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */ #define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */ #define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */ -- cgit v1.2.3 From b493b26b069e22f67cf0ec40f1d00859ab168c96 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 11 Jun 2024 16:33:34 +0300 Subject: drm/i915: Extract intel_crtc_arm_vblank_event() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We'll need to arm the vblank event also from the future DSB based codepath. Extract the function that does the whold dance for us. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240611133344.30673-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_crtc.c | 29 +++++++++++++++++++---------- drivers/gpu/drm/i915/display/intel_crtc.h | 1 + 2 files changed, 20 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 54b529bfc935..6831060a792a 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -560,6 +560,23 @@ static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end) static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end) {} #endif +void intel_crtc_arm_vblank_event(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + unsigned long irqflags; + + if (!crtc_state->uapi.event) + return; + + drm_WARN_ON(crtc->base.dev, drm_crtc_vblank_get(&crtc->base) != 0); + + spin_lock_irqsave(&crtc->base.dev->event_lock, irqflags); + drm_crtc_arm_vblank_event(&crtc->base, crtc_state->uapi.event); + spin_unlock_irqrestore(&crtc->base.dev->event_lock, irqflags); + + crtc_state->uapi.event = NULL; +} + /** * intel_pipe_update_end() - end update of a set of display registers * @state: the atomic state @@ -601,16 +618,8 @@ void intel_pipe_update_end(struct intel_atomic_state *state, drm_vblank_work_schedule(&new_crtc_state->vblank_work, drm_crtc_accurate_vblank_count(&crtc->base) + 1, false); - } else if (new_crtc_state->uapi.event) { - drm_WARN_ON(&dev_priv->drm, - drm_crtc_vblank_get(&crtc->base) != 0); - - spin_lock(&crtc->base.dev->event_lock); - drm_crtc_arm_vblank_event(&crtc->base, - new_crtc_state->uapi.event); - spin_unlock(&crtc->base.dev->event_lock); - - new_crtc_state->uapi.event = NULL; + } else { + intel_crtc_arm_vblank_event(new_crtc_state); } /* diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h b/drivers/gpu/drm/i915/display/intel_crtc.h index 22d7993d1f0b..b615b7ab5ccd 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.h +++ b/drivers/gpu/drm/i915/display/intel_crtc.h @@ -28,6 +28,7 @@ struct intel_crtc_state; int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, int usecs); +void intel_crtc_arm_vblank_event(struct intel_crtc_state *crtc_state); u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state); int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe); struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc); -- cgit v1.2.3 From 91103ca3750c346fe3a4f7b42aab9299d31d0460 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 11 Jun 2024 16:33:35 +0300 Subject: drm/i915: Add async flip tracepoint MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a separate tracepoint for async flips vs. sync plane updates to make it a bit easier to figure out what is happening. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240611133344.30673-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_atomic_plane.c | 22 ++++++++++++++---- drivers/gpu/drm/i915/display/intel_atomic_plane.h | 4 ++++ drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- drivers/gpu/drm/i915/display/intel_display_trace.h | 27 ++++++++++++++++++++++ 4 files changed, 50 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 8ec1bab1b15d..79244ea06b9a 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -801,18 +801,30 @@ void intel_plane_update_noarm(struct intel_plane *plane, plane->update_noarm(plane, crtc_state, plane_state); } +void intel_plane_async_flip(struct intel_plane *plane, + const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state, + bool async_flip) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + trace_intel_plane_async_flip(plane, crtc, async_flip); + plane->async_flip(plane, crtc_state, plane_state, async_flip); +} + void intel_plane_update_arm(struct intel_plane *plane, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - trace_intel_plane_update_arm(plane, crtc); + if (crtc_state->do_async_flip && plane->async_flip) { + intel_plane_async_flip(plane, crtc_state, plane_state, true); + return; + } - if (crtc_state->do_async_flip && plane->async_flip) - plane->async_flip(plane, crtc_state, plane_state, true); - else - plane->update_arm(plane, crtc_state, plane_state); + trace_intel_plane_update_arm(plane, crtc); + plane->update_arm(plane, crtc_state, plane_state); } void intel_plane_disable_arm(struct intel_plane *plane, diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h index e7a0699f17c8..84541d97c67b 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h @@ -32,6 +32,10 @@ void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state, struct intel_crtc *crtc); void intel_plane_copy_hw_state(struct intel_plane_state *plane_state, const struct intel_plane_state *from_plane_state); +void intel_plane_async_flip(struct intel_plane *plane, + const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state, + bool async_flip); void intel_plane_update_noarm(struct intel_plane *plane, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7bc4f3de691e..9041dd3181ee 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1160,8 +1160,8 @@ static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, * Apart from the async flip bit we want to * preserve the old state for the plane. */ - plane->async_flip(plane, old_crtc_state, - old_plane_state, false); + intel_plane_async_flip(plane, old_crtc_state, + old_plane_state, false); need_vbl_wait = true; } } diff --git a/drivers/gpu/drm/i915/display/intel_display_trace.h b/drivers/gpu/drm/i915/display/intel_display_trace.h index 49a5e6d9dc0d..34c223ace5ea 100644 --- a/drivers/gpu/drm/i915/display/intel_display_trace.h +++ b/drivers/gpu/drm/i915/display/intel_display_trace.h @@ -308,6 +308,33 @@ TRACE_EVENT(vlv_fifo_size, __entry->sprite0_start, __entry->sprite1_start, __entry->fifo_size) ); +TRACE_EVENT(intel_plane_async_flip, + TP_PROTO(struct intel_plane *plane, struct intel_crtc *crtc, bool async_flip), + TP_ARGS(plane, crtc, async_flip), + + TP_STRUCT__entry( + __string(dev, __dev_name_kms(plane)) + __field(enum pipe, pipe) + __field(u32, frame) + __field(u32, scanline) + __field(bool, async_flip) + __string(name, plane->base.name) + ), + + TP_fast_assign( + __assign_str(dev); + __assign_str(name); + __entry->pipe = crtc->pipe; + __entry->frame = intel_crtc_get_vblank_counter(crtc); + __entry->scanline = intel_get_crtc_scanline(crtc); + __entry->async_flip = async_flip; + ), + + TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u, async_flip=%s", + __get_str(dev), pipe_name(__entry->pipe), __get_str(name), + __entry->frame, __entry->scanline, str_yes_no(__entry->async_flip)) +); + TRACE_EVENT(intel_plane_update_noarm, TP_PROTO(struct intel_plane *plane, struct intel_crtc *crtc), TP_ARGS(plane, crtc), -- cgit v1.2.3 From 367cf0d8a6760e244f30d36cd3b2120f890837a7 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 11 Jun 2024 16:33:36 +0300 Subject: drm/i915: Add flip done tracepoint MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a tracepoint to see exactly when async flips complete. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240611133344.30673-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 1 + drivers/gpu/drm/i915/display/intel_display_trace.h | 23 ++++++++++++++++++++++ 2 files changed, 24 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 67b19d04d1f7..5219ba295c74 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -346,6 +346,7 @@ static void flip_done_handler(struct drm_i915_private *i915, spin_lock(&i915->drm.event_lock); if (crtc->flip_done_event) { + trace_intel_crtc_flip_done(crtc); drm_crtc_send_vblank_event(&crtc->base, crtc->flip_done_event); crtc->flip_done_event = NULL; } diff --git a/drivers/gpu/drm/i915/display/intel_display_trace.h b/drivers/gpu/drm/i915/display/intel_display_trace.h index 34c223ace5ea..c734ef1fba3c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_trace.h +++ b/drivers/gpu/drm/i915/display/intel_display_trace.h @@ -78,6 +78,29 @@ TRACE_EVENT(intel_pipe_disable, __entry->frame[PIPE_C], __entry->scanline[PIPE_C]) ); +TRACE_EVENT(intel_crtc_flip_done, + TP_PROTO(struct intel_crtc *crtc), + TP_ARGS(crtc), + + TP_STRUCT__entry( + __string(dev, __dev_name_kms(crtc)) + __field(enum pipe, pipe) + __field(u32, frame) + __field(u32, scanline) + ), + + TP_fast_assign( + __assign_str(dev); + __entry->pipe = crtc->pipe; + __entry->frame = intel_crtc_get_vblank_counter(crtc); + __entry->scanline = intel_get_crtc_scanline(crtc); + ), + + TP_printk("dev %s, pipe %c, frame=%u, scanline=%u", + __get_str(dev), pipe_name(__entry->pipe), + __entry->frame, __entry->scanline) +); + TRACE_EVENT(intel_pipe_crc, TP_PROTO(struct intel_crtc *crtc, const u32 *crcs), TP_ARGS(crtc, crcs), -- cgit v1.2.3 From 294ffd2bfaa3bb0434d2b86321c5de54bd79732a Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 11 Jun 2024 16:33:37 +0300 Subject: drm/i915: Introduce intel_mode_vdisplay() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The DSB code will need to know the hardware's idea of vertical active, as that is also what defines the start of undelayed vblank. Introduce a helper that gives us that information, in line with the other intel_mode_v*() functions. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240611133344.30673-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vblank.c | 10 ++++++++++ drivers/gpu/drm/i915/display/intel_vblank.h | 1 + 2 files changed, 11 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index e5db54b1c632..5b065e1cd4e4 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -557,6 +557,16 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state, spin_unlock_irqrestore(&i915->drm.vblank_time_lock, irqflags); } +int intel_mode_vdisplay(const struct drm_display_mode *mode) +{ + int vdisplay = mode->crtc_vdisplay; + + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + vdisplay = DIV_ROUND_UP(vdisplay, 2); + + return vdisplay; +} + int intel_mode_vblank_start(const struct drm_display_mode *mode) { int vblank_start = mode->crtc_vblank_start; diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h index b51ae2c1039e..7e526f6861e4 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.h +++ b/drivers/gpu/drm/i915/display/intel_vblank.h @@ -20,6 +20,7 @@ struct intel_vblank_evade_ctx { bool need_vlv_dsi_wa; }; +int intel_mode_vdisplay(const struct drm_display_mode *mode); int intel_mode_vblank_start(const struct drm_display_mode *mode); int intel_mode_vblank_end(const struct drm_display_mode *mode); int intel_mode_vtotal(const struct drm_display_mode *mode); -- cgit v1.2.3 From 42c8065d83fa3e9267bf99d6de70512c5c071a3b Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 11 Jun 2024 16:33:38 +0300 Subject: drm/i915: Pass the whole atomic state to intel_color_prepare_commit() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We'll have need to examine both the old and new crtc states in intel_color_prepare_commit(), so let's just pass in the whole atomic state. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240611133344.30673-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_color.c | 11 ++++++++--- drivers/gpu/drm/i915/display/intel_color.h | 3 ++- drivers/gpu/drm/i915/display/intel_display.c | 8 +++----- 3 files changed, 13 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 98553e8a5149..8cfd497c2a92 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1902,15 +1902,20 @@ void intel_color_post_update(const struct intel_crtc_state *crtc_state) i915->display.funcs.color->color_post_update(crtc_state); } -void intel_color_prepare_commit(struct intel_crtc_state *crtc_state) +void intel_color_prepare_commit(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); if (!crtc_state->hw.active || intel_crtc_needs_modeset(crtc_state)) return; + if (!intel_crtc_needs_color_update(crtc_state)) + return; + if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut) return; diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h index 21ba4aa02e7b..79f230a1709a 100644 --- a/drivers/gpu/drm/i915/display/intel_color.h +++ b/drivers/gpu/drm/i915/display/intel_color.h @@ -19,7 +19,8 @@ int intel_color_init(struct drm_i915_private *i915); void intel_color_crtc_init(struct intel_crtc *crtc); int intel_color_check(struct intel_atomic_state *state, struct intel_crtc *crtc); -void intel_color_prepare_commit(struct intel_crtc_state *crtc_state); +void intel_color_prepare_commit(struct intel_atomic_state *state, + struct intel_crtc *crtc); void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state); bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state); void intel_color_wait_commit(const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9041dd3181ee..c782e65a7123 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6718,7 +6718,7 @@ int intel_atomic_check(struct drm_device *dev, static int intel_atomic_prepare_commit(struct intel_atomic_state *state) { - struct intel_crtc_state *crtc_state; + struct intel_crtc_state __maybe_unused *crtc_state; struct intel_crtc *crtc; int i, ret; @@ -6726,10 +6726,8 @@ static int intel_atomic_prepare_commit(struct intel_atomic_state *state) if (ret < 0) return ret; - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { - if (intel_crtc_needs_color_update(crtc_state)) - intel_color_prepare_commit(crtc_state); - } + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) + intel_color_prepare_commit(state, crtc); return 0; } -- cgit v1.2.3 From a6c8dfbfcd0137b2676f0e3c48752c3d618d9805 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 11 Jun 2024 16:33:39 +0300 Subject: drm/i915/dsb: Plumb the whole atomic state into intel_dsb_prepare() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The DSB code will need to examine both the old and new crtc states. Pass in the whole atomic state so we can dig up what we need. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240611133344.30673-7-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_color.c | 2 +- drivers/gpu/drm/i915/display/intel_dsb.c | 11 +++++++---- drivers/gpu/drm/i915/display/intel_dsb.h | 4 +++- 3 files changed, 11 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 8cfd497c2a92..7ac50aacec73 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1919,7 +1919,7 @@ void intel_color_prepare_commit(struct intel_atomic_state *state, if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut) return; - crtc_state->dsb = intel_dsb_prepare(crtc_state, INTEL_DSB_0, 1024); + crtc_state->dsb = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 1024); if (!crtc_state->dsb) return; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 5180b9722046..8ae7bcfa8403 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -434,7 +434,8 @@ void intel_dsb_wait(struct intel_dsb *dsb) /** * intel_dsb_prepare() - Allocate, pin and map the DSB command buffer. - * @crtc_state: the CRTC state + * @state: the atomic state + * @crtc: the CRTC * @dsb_id: the DSB engine to use * @max_cmds: number of commands we need to fit into command buffer * @@ -444,12 +445,14 @@ void intel_dsb_wait(struct intel_dsb *dsb) * Returns: * DSB context, NULL on failure */ -struct intel_dsb *intel_dsb_prepare(const struct intel_crtc_state *crtc_state, +struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, + struct intel_crtc *crtc, enum intel_dsb_id dsb_id, unsigned int max_cmds) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(state->base.dev); + const struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); intel_wakeref_t wakeref; struct intel_dsb *dsb; unsigned int size; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index 36fdb130af6e..bb42749f2ea4 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -10,6 +10,7 @@ #include "i915_reg_defs.h" +struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; struct intel_dsb; @@ -22,7 +23,8 @@ enum intel_dsb_id { I915_MAX_DSBS, }; -struct intel_dsb *intel_dsb_prepare(const struct intel_crtc_state *crtc_state, +struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, + struct intel_crtc *crtc, enum intel_dsb_id dsb_id, unsigned int max_cmds); void intel_dsb_finish(struct intel_dsb *dsb); -- cgit v1.2.3 From 4a74de91056d640aa6b4025fc01330313ce22fdc Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 11 Jun 2024 16:33:40 +0300 Subject: drm/i915/dsb: Convert the DSB code to use intel_display rather than i915 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The future direction will be to mainly use intel_display rather than i915 in the display code. Start on that path for the DSB code. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240611133344.30673-8-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dsb.c | 52 ++++++++++++++++---------------- 1 file changed, 26 insertions(+), 26 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 8ae7bcfa8403..bee48ac419ce 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -85,10 +85,10 @@ struct intel_dsb { static bool assert_dsb_has_room(struct intel_dsb *dsb) { struct intel_crtc *crtc = dsb->crtc; - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc->base.dev); /* each instruction is 2 dwords */ - return !drm_WARN(&i915->drm, dsb->free_pos > dsb->size - 2, + return !drm_WARN(display->drm, dsb->free_pos > dsb->size - 2, "[CRTC:%d:%s] DSB %d buffer overflow\n", crtc->base.base.id, crtc->base.name, dsb->id); } @@ -96,25 +96,25 @@ static bool assert_dsb_has_room(struct intel_dsb *dsb) static void intel_dsb_dump(struct intel_dsb *dsb) { struct intel_crtc *crtc = dsb->crtc; - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc->base.dev); int i; - drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] DSB %d commands {\n", + drm_dbg_kms(display->drm, "[CRTC:%d:%s] DSB %d commands {\n", crtc->base.base.id, crtc->base.name, dsb->id); for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4) - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, " 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", i * 4, intel_dsb_buffer_read(&dsb->dsb_buf, i), intel_dsb_buffer_read(&dsb->dsb_buf, i + 1), intel_dsb_buffer_read(&dsb->dsb_buf, i + 2), intel_dsb_buffer_read(&dsb->dsb_buf, i + 3)); - drm_dbg_kms(&i915->drm, "}\n"); + drm_dbg_kms(display->drm, "}\n"); } -static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe, +static bool is_dsb_busy(struct intel_display *display, enum pipe pipe, enum intel_dsb_id dsb_id) { - return intel_de_read_fw(i915, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY; + return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY; } static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw) @@ -343,27 +343,27 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, int dewake_scanline) { struct intel_crtc *crtc = dsb->crtc; - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc->base.dev); enum pipe pipe = crtc->pipe; u32 tail; tail = dsb->free_pos * 4; - if (drm_WARN_ON(&dev_priv->drm, !IS_ALIGNED(tail, CACHELINE_BYTES))) + if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES))) return; - if (is_dsb_busy(dev_priv, pipe, dsb->id)) { - drm_err(&dev_priv->drm, "[CRTC:%d:%s] DSB %d is busy\n", + if (is_dsb_busy(display, pipe, dsb->id)) { + drm_err(display->drm, "[CRTC:%d:%s] DSB %d is busy\n", crtc->base.base.id, crtc->base.name, dsb->id); return; } - intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id), + intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), ctrl | DSB_ENABLE); - intel_de_write_fw(dev_priv, DSB_CHICKEN(pipe, dsb->id), + intel_de_write_fw(display, DSB_CHICKEN(pipe, dsb->id), dsb_chicken(crtc)); - intel_de_write_fw(dev_priv, DSB_HEAD(pipe, dsb->id), + intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id), intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf)); if (dewake_scanline >= 0) { @@ -371,7 +371,7 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, hw_dewake_scanline = intel_crtc_scanline_to_hw(crtc, dewake_scanline); - intel_de_write_fw(dev_priv, DSB_PMCTRL(pipe, dsb->id), + intel_de_write_fw(display, DSB_PMCTRL(pipe, dsb->id), DSB_ENABLE_DEWAKE | DSB_SCANLINE_FOR_DEWAKE(hw_dewake_scanline)); @@ -380,12 +380,12 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, * or close to racing past the target scanline. */ diff = dewake_scanline - intel_get_crtc_scanline(crtc); - intel_de_write_fw(dev_priv, DSB_PMCTRL_2(pipe, dsb->id), + intel_de_write_fw(display, DSB_PMCTRL_2(pipe, dsb->id), (diff >= 0 && diff < 5 ? DSB_FORCE_DEWAKE : 0) | DSB_BLOCK_DEWAKE_EXTENSION); } - intel_de_write_fw(dev_priv, DSB_TAIL(pipe, dsb->id), + intel_de_write_fw(display, DSB_TAIL(pipe, dsb->id), intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + tail); } @@ -407,21 +407,21 @@ void intel_dsb_commit(struct intel_dsb *dsb, void intel_dsb_wait(struct intel_dsb *dsb) { struct intel_crtc *crtc = dsb->crtc; - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc->base.dev); enum pipe pipe = crtc->pipe; - if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) { + if (wait_for(!is_dsb_busy(display, pipe, dsb->id), 1)) { u32 offset = intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf); - intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id), + intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), DSB_ENABLE | DSB_HALT); - drm_err(&dev_priv->drm, + drm_err(display->drm, "[CRTC:%d:%s] DSB %d timed out waiting for idle (current head=0x%x, head=0x%x, tail=0x%x)\n", crtc->base.base.id, crtc->base.name, dsb->id, - intel_de_read_fw(dev_priv, DSB_CURRENT_HEAD(pipe, dsb->id)) - offset, - intel_de_read_fw(dev_priv, DSB_HEAD(pipe, dsb->id)) - offset, - intel_de_read_fw(dev_priv, DSB_TAIL(pipe, dsb->id)) - offset); + intel_de_read_fw(display, DSB_CURRENT_HEAD(pipe, dsb->id)) - offset, + intel_de_read_fw(display, DSB_HEAD(pipe, dsb->id)) - offset, + intel_de_read_fw(display, DSB_TAIL(pipe, dsb->id)) - offset); intel_dsb_dump(dsb); } @@ -429,7 +429,7 @@ void intel_dsb_wait(struct intel_dsb *dsb) /* Attempt to reset it */ dsb->free_pos = 0; dsb->ins_start_offset = 0; - intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id), 0); + intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), 0); } /** -- cgit v1.2.3 From 7562c88be8acf3898cd5d35cb5e83611139636f1 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 11 Jun 2024 16:33:41 +0300 Subject: drm/i915/dsb: Add i915.enable_dsb module parameter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As we extend the use of DSB for critical pipe/plane register programming, it'll be nice to have an escape valve at hand, in case things go very poorly. To that end, add a i915.enable_dsb modparam by which we can force the driver to take the pure mmio path instead. v2: Use 0400 permissions for the actual modparam (Jani) Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240611133344.30673-9-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++ drivers/gpu/drm/i915/display/intel_display_params.h | 1 + drivers/gpu/drm/i915/display/intel_dsb.c | 3 +++ 3 files changed, 7 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c index 79107607a6ff..e82bd72d32fa 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.c +++ b/drivers/gpu/drm/i915/display/intel_display_params.c @@ -54,6 +54,9 @@ intel_display_param_named_unsafe(enable_dc, int, 0400, intel_display_param_named_unsafe(enable_dpt, bool, 0400, "Enable display page table (DPT) (default: true)"); +intel_display_param_named_unsafe(enable_dsb, bool, 0400, + "Enable display state buffer (DSB) (default: true)"); + intel_display_param_named_unsafe(enable_sagv, bool, 0400, "Enable system agent voltage/frequency scaling (SAGV) (default: true)"); diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h index 1208a62c16d2..48c29c55c939 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.h +++ b/drivers/gpu/drm/i915/display/intel_display_params.h @@ -31,6 +31,7 @@ struct drm_i915_private; param(int, vbt_sdvo_panel_type, -1, 0400) \ param(int, enable_dc, -1, 0400) \ param(bool, enable_dpt, true, 0400) \ + param(bool, enable_dsb, true, 0600) \ param(bool, enable_sagv, true, 0600) \ param(int, disable_power_well, -1, 0400) \ param(bool, enable_ips, true, 0600) \ diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index bee48ac419ce..2ab3765f6c06 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -460,6 +460,9 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, if (!HAS_DSB(i915)) return NULL; + if (!i915->display.params.enable_dsb) + return NULL; + /* TODO: DSB is broken in Xe KMD, so disabling it until fixed */ if (!IS_ENABLED(I915)) return NULL; -- cgit v1.2.3 From 5bdd780180e3f261ca576e9d25e8cc356e97f4f4 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 11 Jun 2024 16:33:42 +0300 Subject: drm/i915: Drop useless intel_dsb.h include MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit intel_crtc.c doens't need intel_dsb.h so don't include it. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240611133344.30673-10-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_crtc.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 6831060a792a..a2b8953d7283 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -24,7 +24,6 @@ #include "intel_display_trace.h" #include "intel_display_types.h" #include "intel_drrs.h" -#include "intel_dsb.h" #include "intel_dsi.h" #include "intel_fifo_underrun.h" #include "intel_pipe_crc.h" -- cgit v1.2.3 From 67577e2eada5b6501e30d80adea9d045081ba7a1 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 11 Jun 2024 16:33:43 +0300 Subject: drm/i915/dsb: Document that the ATS fault bits are for mtl+ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ATS faults have something to do with some new iommu stuff on mtl+. Document that the relevant DSB interrupt bits aren't valid for earlier platforms. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240611133344.30673-11-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dsb_regs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_dsb_regs.h b/drivers/gpu/drm/i915/display/intel_dsb_regs.h index 210e2665441d..9c2664ff519a 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dsb_regs.h @@ -51,12 +51,12 @@ #define DSB_RESET_SM_STATE_MASK REG_GENMASK(5, 4) #define DSB_RUN_SM_STATE_MASK REG_GENMASK(2, 0) #define DSB_INTERRUPT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28) -#define DSB_ATS_FAULT_INT_EN REG_BIT(20) +#define DSB_ATS_FAULT_INT_EN REG_BIT(20) /* mtl+ */ #define DSB_GTT_FAULT_INT_EN REG_BIT(19) #define DSB_RSPTIMEOUT_INT_EN REG_BIT(18) #define DSB_POLL_ERR_INT_EN REG_BIT(17) #define DSB_PROG_INT_EN REG_BIT(16) -#define DSB_ATS_FAULT_INT_STATUS REG_BIT(4) +#define DSB_ATS_FAULT_INT_STATUS REG_BIT(4) /* mtl+ */ #define DSB_GTT_FAULT_INT_STATUS REG_BIT(3) #define DSB_RSPTIMEOUT_INT_STATUS REG_BIT(2) #define DSB_POLL_ERR_INT_STATUS REG_BIT(1) -- cgit v1.2.3 From cc2ee76a9003e1b5a7cd4f67ecf9b4b91d83299b Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 18 Jun 2024 15:52:53 +0300 Subject: drm/i915: Move encoder suspend/shutdown helpers to intel_encoder.c Move the encoder suspend/shutdown helpers to intel_encoder.c, this being the logical place for encoder functions. This also allows sharing the above helpers with the xe driver, done in a follow-up patch. While at it rename the functions using the usual intel_encoder prefix and in the functions rename the dev_priv parameter to i915. v2: Remove extra w/s in the include section. (Jani) Reviewed-by: Rodrigo Vivi # v1 Reviewed-by: Jani Nikula Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240618125255.4080303-1-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_encoder.c | 44 ++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_encoder.h | 4 +++ drivers/gpu/drm/i915/i915_driver.c | 51 +++------------------------- 3 files changed, 52 insertions(+), 47 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_encoder.c b/drivers/gpu/drm/i915/display/intel_encoder.c index dee55f56960f..8a1dccb893a3 100644 --- a/drivers/gpu/drm/i915/display/intel_encoder.c +++ b/drivers/gpu/drm/i915/display/intel_encoder.c @@ -37,3 +37,47 @@ void intel_encoder_link_check_queue_work(struct intel_encoder *encoder, int dela mod_delayed_work(i915->unordered_wq, &encoder->link_check_work, msecs_to_jiffies(delay_ms)); } + +void intel_encoder_suspend_all(struct drm_i915_private *i915) +{ + struct intel_encoder *encoder; + + if (!HAS_DISPLAY(i915)) + return; + + /* + * TODO: check and remove holding the modeset locks if none of + * the encoders depends on this. + */ + drm_modeset_lock_all(&i915->drm); + for_each_intel_encoder(&i915->drm, encoder) + if (encoder->suspend) + encoder->suspend(encoder); + drm_modeset_unlock_all(&i915->drm); + + for_each_intel_encoder(&i915->drm, encoder) + if (encoder->suspend_complete) + encoder->suspend_complete(encoder); +} + +void intel_encoder_shutdown_all(struct drm_i915_private *i915) +{ + struct intel_encoder *encoder; + + if (!HAS_DISPLAY(i915)) + return; + + /* + * TODO: check and remove holding the modeset locks if none of + * the encoders depends on this. + */ + drm_modeset_lock_all(&i915->drm); + for_each_intel_encoder(&i915->drm, encoder) + if (encoder->shutdown) + encoder->shutdown(encoder); + drm_modeset_unlock_all(&i915->drm); + + for_each_intel_encoder(&i915->drm, encoder) + if (encoder->shutdown_complete) + encoder->shutdown_complete(encoder); +} diff --git a/drivers/gpu/drm/i915/display/intel_encoder.h b/drivers/gpu/drm/i915/display/intel_encoder.h index 2cda054e2b15..04cfc0a72199 100644 --- a/drivers/gpu/drm/i915/display/intel_encoder.h +++ b/drivers/gpu/drm/i915/display/intel_encoder.h @@ -6,6 +6,7 @@ #ifndef __INTEL_ENCODER_H__ #define __INTEL_ENCODER_H__ +struct drm_i915_private; struct intel_encoder; void intel_encoder_link_check_init(struct intel_encoder *encoder, @@ -13,4 +14,7 @@ void intel_encoder_link_check_init(struct intel_encoder *encoder, void intel_encoder_link_check_queue_work(struct intel_encoder *encoder, int delay_ms); void intel_encoder_link_check_flush_work(struct intel_encoder *encoder); +void intel_encoder_suspend_all(struct drm_i915_private *i915); +void intel_encoder_shutdown_all(struct drm_i915_private *i915); + #endif /* __INTEL_ENCODER_H__ */ diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index 161b21eff694..e9e38ed246f6 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -53,6 +53,7 @@ #include "display/intel_dmc.h" #include "display/intel_dp.h" #include "display/intel_dpt.h" +#include "display/intel_encoder.h" #include "display/intel_fbdev.h" #include "display/intel_hotplug.h" #include "display/intel_overlay.h" @@ -933,50 +934,6 @@ static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) i915_gem_flush_free_objects(to_i915(dev)); } -static void intel_suspend_encoders(struct drm_i915_private *dev_priv) -{ - struct intel_encoder *encoder; - - if (!HAS_DISPLAY(dev_priv)) - return; - - /* - * TODO: check and remove holding the modeset locks if none of - * the encoders depends on this. - */ - drm_modeset_lock_all(&dev_priv->drm); - for_each_intel_encoder(&dev_priv->drm, encoder) - if (encoder->suspend) - encoder->suspend(encoder); - drm_modeset_unlock_all(&dev_priv->drm); - - for_each_intel_encoder(&dev_priv->drm, encoder) - if (encoder->suspend_complete) - encoder->suspend_complete(encoder); -} - -static void intel_shutdown_encoders(struct drm_i915_private *dev_priv) -{ - struct intel_encoder *encoder; - - if (!HAS_DISPLAY(dev_priv)) - return; - - /* - * TODO: check and remove holding the modeset locks if none of - * the encoders depends on this. - */ - drm_modeset_lock_all(&dev_priv->drm); - for_each_intel_encoder(&dev_priv->drm, encoder) - if (encoder->shutdown) - encoder->shutdown(encoder); - drm_modeset_unlock_all(&dev_priv->drm); - - for_each_intel_encoder(&dev_priv->drm, encoder) - if (encoder->shutdown_complete) - encoder->shutdown_complete(encoder); -} - void i915_driver_shutdown(struct drm_i915_private *i915) { disable_rpm_wakeref_asserts(&i915->runtime_pm); @@ -999,8 +956,8 @@ void i915_driver_shutdown(struct drm_i915_private *i915) if (HAS_DISPLAY(i915)) intel_display_driver_suspend_access(i915); - intel_suspend_encoders(i915); - intel_shutdown_encoders(i915); + intel_encoder_suspend_all(i915); + intel_encoder_shutdown_all(i915); intel_dmc_suspend(i915); @@ -1083,7 +1040,7 @@ static int i915_drm_suspend(struct drm_device *dev) if (HAS_DISPLAY(dev_priv)) intel_display_driver_suspend_access(dev_priv); - intel_suspend_encoders(dev_priv); + intel_encoder_suspend_all(dev_priv); /* Must be called before GGTT is suspended. */ intel_dpt_suspend(dev_priv); -- cgit v1.2.3 From b2c42f9d5ef0159635ba23f4dc2798c1fbcb7cb5 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 18 Jun 2024 15:52:54 +0300 Subject: drm/i915: Pass intel_display to the encoder suspend/shutdown helpers Pass intel_display to the encoder suspend/shutdown helpers instead of drm_i915_private for better isolation. v2: Pass intel_display to HAS_DISPLAY() as well, update commit log accordingly. (Jani) Cc: Jani Nikula Reviewed-by: Rodrigo Vivi # v1 Reviewed-by: Jani Nikula Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240618125255.4080303-2-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_encoder.c | 24 ++++++++++++------------ drivers/gpu/drm/i915/display/intel_encoder.h | 6 +++--- drivers/gpu/drm/i915/i915_driver.c | 6 +++--- 3 files changed, 18 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_encoder.c b/drivers/gpu/drm/i915/display/intel_encoder.c index 8a1dccb893a3..21d638535497 100644 --- a/drivers/gpu/drm/i915/display/intel_encoder.c +++ b/drivers/gpu/drm/i915/display/intel_encoder.c @@ -38,46 +38,46 @@ void intel_encoder_link_check_queue_work(struct intel_encoder *encoder, int dela &encoder->link_check_work, msecs_to_jiffies(delay_ms)); } -void intel_encoder_suspend_all(struct drm_i915_private *i915) +void intel_encoder_suspend_all(struct intel_display *display) { struct intel_encoder *encoder; - if (!HAS_DISPLAY(i915)) + if (!HAS_DISPLAY(display)) return; /* * TODO: check and remove holding the modeset locks if none of * the encoders depends on this. */ - drm_modeset_lock_all(&i915->drm); - for_each_intel_encoder(&i915->drm, encoder) + drm_modeset_lock_all(display->drm); + for_each_intel_encoder(display->drm, encoder) if (encoder->suspend) encoder->suspend(encoder); - drm_modeset_unlock_all(&i915->drm); + drm_modeset_unlock_all(display->drm); - for_each_intel_encoder(&i915->drm, encoder) + for_each_intel_encoder(display->drm, encoder) if (encoder->suspend_complete) encoder->suspend_complete(encoder); } -void intel_encoder_shutdown_all(struct drm_i915_private *i915) +void intel_encoder_shutdown_all(struct intel_display *display) { struct intel_encoder *encoder; - if (!HAS_DISPLAY(i915)) + if (!HAS_DISPLAY(display)) return; /* * TODO: check and remove holding the modeset locks if none of * the encoders depends on this. */ - drm_modeset_lock_all(&i915->drm); - for_each_intel_encoder(&i915->drm, encoder) + drm_modeset_lock_all(display->drm); + for_each_intel_encoder(display->drm, encoder) if (encoder->shutdown) encoder->shutdown(encoder); - drm_modeset_unlock_all(&i915->drm); + drm_modeset_unlock_all(display->drm); - for_each_intel_encoder(&i915->drm, encoder) + for_each_intel_encoder(display->drm, encoder) if (encoder->shutdown_complete) encoder->shutdown_complete(encoder); } diff --git a/drivers/gpu/drm/i915/display/intel_encoder.h b/drivers/gpu/drm/i915/display/intel_encoder.h index 04cfc0a72199..3fa5589f0b1c 100644 --- a/drivers/gpu/drm/i915/display/intel_encoder.h +++ b/drivers/gpu/drm/i915/display/intel_encoder.h @@ -6,7 +6,7 @@ #ifndef __INTEL_ENCODER_H__ #define __INTEL_ENCODER_H__ -struct drm_i915_private; +struct intel_display; struct intel_encoder; void intel_encoder_link_check_init(struct intel_encoder *encoder, @@ -14,7 +14,7 @@ void intel_encoder_link_check_init(struct intel_encoder *encoder, void intel_encoder_link_check_queue_work(struct intel_encoder *encoder, int delay_ms); void intel_encoder_link_check_flush_work(struct intel_encoder *encoder); -void intel_encoder_suspend_all(struct drm_i915_private *i915); -void intel_encoder_shutdown_all(struct drm_i915_private *i915); +void intel_encoder_suspend_all(struct intel_display *display); +void intel_encoder_shutdown_all(struct intel_display *display); #endif /* __INTEL_ENCODER_H__ */ diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index e9e38ed246f6..fb8e9c2fcea5 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -956,8 +956,8 @@ void i915_driver_shutdown(struct drm_i915_private *i915) if (HAS_DISPLAY(i915)) intel_display_driver_suspend_access(i915); - intel_encoder_suspend_all(i915); - intel_encoder_shutdown_all(i915); + intel_encoder_suspend_all(&i915->display); + intel_encoder_shutdown_all(&i915->display); intel_dmc_suspend(i915); @@ -1040,7 +1040,7 @@ static int i915_drm_suspend(struct drm_device *dev) if (HAS_DISPLAY(dev_priv)) intel_display_driver_suspend_access(dev_priv); - intel_encoder_suspend_all(dev_priv); + intel_encoder_suspend_all(&dev_priv->display); /* Must be called before GGTT is suspended. */ intel_dpt_suspend(dev_priv); -- cgit v1.2.3 From b1d90a862c890152bbaf847b7a78fc59af54159b Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 18 Jun 2024 15:52:55 +0300 Subject: drm/xe: Use the encoder suspend helper also used by the i915 driver Use the suspend encoders helper which is also used by the i915 driver. This fixes an issue in the xe driver where the encoder suspend_complete() hook is not called and was an overlook when this hook was added in commit b61fad5f7e5d ("drm/i915/tc: Call TypeC port flush_work/cleanup without modeset locks held") for i915, but not added to the xe driver (which was still in a separate source tree at the above point). v2: Fix checkpatch warn in commit log. (Rodrigo) Reviewed-by: Rodrigo Vivi Reviewed-by: Jani Nikula Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240618125255.4080303-3-imre.deak@intel.com --- drivers/gpu/drm/xe/display/xe_display.c | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c index 78cccbe28947..8b83dcff72e1 100644 --- a/drivers/gpu/drm/xe/display/xe_display.c +++ b/drivers/gpu/drm/xe/display/xe_display.c @@ -23,6 +23,7 @@ #include "intel_display_types.h" #include "intel_dmc.h" #include "intel_dp.h" +#include "intel_encoder.h" #include "intel_fbdev.h" #include "intel_hdcp.h" #include "intel_hotplug.h" @@ -270,21 +271,6 @@ void xe_display_irq_postinstall(struct xe_device *xe, struct xe_gt *gt) gen11_de_irq_postinstall(xe); } -static void intel_suspend_encoders(struct xe_device *xe) -{ - struct drm_device *dev = &xe->drm; - struct intel_encoder *encoder; - - if (has_display(xe)) - return; - - drm_modeset_lock_all(dev); - for_each_intel_encoder(dev, encoder) - if (encoder->suspend) - encoder->suspend(encoder); - drm_modeset_unlock_all(dev); -} - static bool suspend_to_idle(void) { #if IS_ENABLED(CONFIG_ACPI_SLEEP) @@ -315,7 +301,7 @@ void xe_display_pm_suspend(struct xe_device *xe, bool runtime) intel_hpd_cancel_work(xe); - intel_suspend_encoders(xe); + intel_encoder_suspend_all(&xe->display); intel_opregion_suspend(xe, s2idle ? PCI_D1 : PCI_D3cold); -- cgit v1.2.3 From 582e372f068c813c852a48000f27c175fb11bb61 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Thu, 20 Jun 2024 13:33:12 +0300 Subject: drm/i915/psr: Set DP_PSR_SU_REGION_SCANLINE_CAPTURE bit when needed MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Setting DP_PSR_SU_REGION_SCANLINE_CAPTURE (Selective Update Region Scan Line Capture Indication in spec) bit was dropped when psr_enable_sink was split to _psr_enable_sink and _panel_replay_enable_sink. Add setting it back. Fixes: 32f0045f905c ("drm/i915/psr: Split enabling sink for PSR and Panel Replay") Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240620103312.903977-1-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index a9d9383e4ee5..0dbcaf644624 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -732,6 +732,9 @@ static void _psr_enable_sink(struct intel_dp *intel_dp, val |= DP_PSR_CRC_VERIFICATION; } + if (crtc_state->req_psr2_sdp_prior_scanline) + val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; + if (crtc_state->enable_psr2_su_region_et) val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET; -- cgit v1.2.3 From 213cc30331e9e8c92458c57a9565efc47933f34b Mon Sep 17 00:00:00 2001 From: Mitul Golani Date: Fri, 21 Jun 2024 13:04:54 +0530 Subject: drm/i915/display: Consider adjusted_pixel_rate to be u64 Consider adjusted_pixel_rate to be a u64 to match the return type of mul_u32_u32() and avoid any compiler dependency for do_div. Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal") Cc: Mitul Golani Cc: Ankit Nautiyal Cc: Suraj Kandpal Cc: Jani Nikula Cc: Rodrigo Vivi Cc: Nathan Chancellor Cc: intel-xe@lists.freedesktop.org Reported-by: Nathan Chancellor Closes: https://lore.kernel.org/r/20240619154207.GA1125704@thelio-3990X Signed-off-by: Mitul Golani Reviewed-by: Rodrigo Vivi Signed-off-by: Suraj Kandpal Link: https://patchwork.freedesktop.org/patch/msgid/20240621073454.1421676-1-mitulkumar.ajitkumar.golani@intel.com --- drivers/gpu/drm/i915/display/intel_vrr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 6430da25957d..5a0da64c7db3 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -137,7 +137,7 @@ static unsigned int cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required) { int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate; - long long adjusted_pixel_rate; + u64 adjusted_pixel_rate; struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; desired_refresh_rate = drm_mode_vrefresh(adjusted_mode); -- cgit v1.2.3 From 1d36db2b5173258e51015200c8ae86325268edec Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 12 Jun 2024 23:47:04 +0300 Subject: drm: Rename drm_plane_check_pixel_format() to drm_plane_has_format() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename drm_plane_check_pixel_format() to drm_plane_has_format() and change the return type accordingly. Allows one to write more natural code. Also matches drm_any_plane_has_format() better. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240612204712.31404-2-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter Acked-by: Thomas Zimmermann --- drivers/gpu/drm/drm_atomic.c | 7 ++----- drivers/gpu/drm/drm_crtc.c | 6 ++---- drivers/gpu/drm/drm_crtc_internal.h | 4 ++-- drivers/gpu/drm/drm_plane.c | 22 ++++++++++------------ 4 files changed, 16 insertions(+), 23 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index a91737adf8e7..e22560213b8e 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -608,7 +608,6 @@ static int drm_atomic_plane_check(const struct drm_plane_state *old_plane_state, unsigned int fb_width, fb_height; struct drm_mode_rect *clips; uint32_t num_clips; - int ret; /* either *both* CRTC and FB must be set, or neither */ if (crtc && !fb) { @@ -635,14 +634,12 @@ static int drm_atomic_plane_check(const struct drm_plane_state *old_plane_state, } /* Check whether this plane supports the fb pixel format. */ - ret = drm_plane_check_pixel_format(plane, fb->format->format, - fb->modifier); - if (ret) { + if (!drm_plane_has_format(plane, fb->format->format, fb->modifier)) { drm_dbg_atomic(plane->dev, "[PLANE:%d:%s] invalid pixel format %p4cc, modifier 0x%llx\n", plane->base.id, plane->name, &fb->format->format, fb->modifier); - return ret; + return -EINVAL; } /* Give drivers some help against integer overflows */ diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 483969b84a30..3488ff067c69 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -789,12 +789,10 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, * case. */ if (!plane->format_default) { - ret = drm_plane_check_pixel_format(plane, - fb->format->format, - fb->modifier); - if (ret) { + if (!drm_plane_has_format(plane, fb->format->format, fb->modifier)) { drm_dbg_kms(dev, "Invalid pixel format %p4cc, modifier 0x%llx\n", &fb->format->format, fb->modifier); + ret = -EINVAL; goto out; } } diff --git a/drivers/gpu/drm/drm_crtc_internal.h b/drivers/gpu/drm/drm_crtc_internal.h index 25aaae937ceb..898e0e8b51be 100644 --- a/drivers/gpu/drm/drm_crtc_internal.h +++ b/drivers/gpu/drm/drm_crtc_internal.h @@ -272,8 +272,8 @@ int drm_mode_atomic_ioctl(struct drm_device *dev, /* drm_plane.c */ int drm_plane_register_all(struct drm_device *dev); void drm_plane_unregister_all(struct drm_device *dev); -int drm_plane_check_pixel_format(struct drm_plane *plane, - u32 format, u64 modifier); +bool drm_plane_has_format(struct drm_plane *plane, + u32 format, u64 modifier); struct drm_mode_rect * __drm_plane_get_damage_clips(const struct drm_plane_state *state); diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index 57662a1fd345..268aa2299df5 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -877,8 +877,8 @@ int drm_mode_getplane(struct drm_device *dev, void *data, return 0; } -int drm_plane_check_pixel_format(struct drm_plane *plane, - u32 format, u64 modifier) +bool drm_plane_has_format(struct drm_plane *plane, + u32 format, u64 modifier) { unsigned int i; @@ -887,24 +887,24 @@ int drm_plane_check_pixel_format(struct drm_plane *plane, break; } if (i == plane->format_count) - return -EINVAL; + return false; if (plane->funcs->format_mod_supported) { if (!plane->funcs->format_mod_supported(plane, format, modifier)) - return -EINVAL; + return false; } else { if (!plane->modifier_count) - return 0; + return true; for (i = 0; i < plane->modifier_count; i++) { if (modifier == plane->modifiers[i]) break; } if (i == plane->modifier_count) - return -EINVAL; + return false; } - return 0; + return true; } static int __setplane_check(struct drm_plane *plane, @@ -924,12 +924,10 @@ static int __setplane_check(struct drm_plane *plane, } /* Check whether this plane supports the fb pixel format. */ - ret = drm_plane_check_pixel_format(plane, fb->format->format, - fb->modifier); - if (ret) { + if (!drm_plane_has_format(plane, fb->format->format, fb->modifier)) { DRM_DEBUG_KMS("Invalid pixel format %p4cc, modifier 0x%llx\n", &fb->format->format, fb->modifier); - return ret; + return -EINVAL; } /* Give drivers some help against integer overflows */ @@ -964,7 +962,7 @@ bool drm_any_plane_has_format(struct drm_device *dev, struct drm_plane *plane; drm_for_each_plane(plane, dev) { - if (drm_plane_check_pixel_format(plane, format, modifier) == 0) + if (drm_plane_has_format(plane, format, modifier)) return true; } -- cgit v1.2.3 From 1c5f18d88eae348cf45f90aaee7b361f593b0701 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 19 Jun 2024 14:31:44 +0300 Subject: drm: Export drm_plane_has_format() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Export drm_plane_has_format() so that drivers can use it. v2: add kerneldoc Reviewed-by: Jani Nikula Reviewed-by: Daniel Vetter Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240619113144.1616-1-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter Acked-by: Daniel Stone Acked-by: Thomas Zimmermann --- drivers/gpu/drm/drm_crtc_internal.h | 2 -- drivers/gpu/drm/drm_plane.c | 10 ++++++++++ include/drm/drm_plane.h | 2 ++ 3 files changed, 12 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_crtc_internal.h b/drivers/gpu/drm/drm_crtc_internal.h index 898e0e8b51be..e207759ca045 100644 --- a/drivers/gpu/drm/drm_crtc_internal.h +++ b/drivers/gpu/drm/drm_crtc_internal.h @@ -272,8 +272,6 @@ int drm_mode_atomic_ioctl(struct drm_device *dev, /* drm_plane.c */ int drm_plane_register_all(struct drm_device *dev); void drm_plane_unregister_all(struct drm_device *dev); -bool drm_plane_has_format(struct drm_plane *plane, - u32 format, u64 modifier); struct drm_mode_rect * __drm_plane_get_damage_clips(const struct drm_plane_state *state); diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index 268aa2299df5..a28b22fdd7a4 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -877,6 +877,15 @@ int drm_mode_getplane(struct drm_device *dev, void *data, return 0; } +/** + * drm_plane_has_format - Check whether the plane supports this format and modifier combination + * @plane: drm plane + * @format: pixel format (DRM_FORMAT_*) + * @modifier: data layout modifier + * + * Returns: + * Whether the plane supports the specified format and modifier combination. + */ bool drm_plane_has_format(struct drm_plane *plane, u32 format, u64 modifier) { @@ -906,6 +915,7 @@ bool drm_plane_has_format(struct drm_plane *plane, return true; } +EXPORT_SYMBOL(drm_plane_has_format); static int __setplane_check(struct drm_plane *plane, struct drm_crtc *crtc, diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 9507542121fa..dd718c62ac31 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -972,6 +972,8 @@ static inline struct drm_plane *drm_plane_find(struct drm_device *dev, #define drm_for_each_plane(plane, dev) \ list_for_each_entry(plane, &(dev)->mode_config.plane_list, head) +bool drm_plane_has_format(struct drm_plane *plane, + u32 format, u64 modifier); bool drm_any_plane_has_format(struct drm_device *dev, u32 format, u64 modifier); -- cgit v1.2.3 From 195b7a0d2ebe5672a58210992f3629d19d5a95ae Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 12 Jun 2024 23:47:06 +0300 Subject: drm/i915: Introduce the plane->min_alignment() vfunc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Different hardware generations have different scanout alignment requirements. Introduce a new vfunc that will allow us to make that distinction without horrible if-ladders. For now we directly plug in the existing intel_surf_alignment() and intel_cursor_alignment() functions. For fbdev we (temporarily) introduce intel_fbdev_min_alignment() that simply queries the alignment from the primary plane of the first crtc. TODO: someone will need to fix xe's alignment handling Reviewed-by: Imre Deak Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240612204712.31404-4-ville.syrjala@linux.intel.com Acked-by: Rodrigo Vivi --- drivers/gpu/drm/i915/display/i9xx_plane.c | 8 +++-- drivers/gpu/drm/i915/display/intel_cursor.c | 2 ++ drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++ drivers/gpu/drm/i915/display/intel_fb.c | 22 ++++++------ drivers/gpu/drm/i915/display/intel_fb.h | 7 ++-- drivers/gpu/drm/i915/display/intel_fb_pin.c | 40 ++++++++++++++++------ drivers/gpu/drm/i915/display/intel_fb_pin.h | 3 +- drivers/gpu/drm/i915/display/intel_fbdev.c | 21 ++++++++++-- drivers/gpu/drm/i915/display/intel_sprite.c | 2 ++ drivers/gpu/drm/i915/display/skl_universal_plane.c | 11 +++--- drivers/gpu/drm/xe/display/xe_fb_pin.c | 3 +- drivers/gpu/drm/xe/display/xe_plane_initial.c | 4 +-- 12 files changed, 89 insertions(+), 37 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 864d94406894..53b18efaa88c 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -225,8 +225,8 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, int i9xx_check_plane_surface(struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; int src_x, src_y, src_w; u32 offset; @@ -267,7 +267,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) * despite them not using the linear offset anymore. */ if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) { - unsigned int alignment = intel_surf_alignment(fb, 0); + unsigned int alignment = plane->min_alignment(plane, fb, 0); int cpp = fb->format->cpp[0]; while ((src_x + src_w) * cpp > plane_state->view.color_plane[0].mapping_stride) { @@ -869,6 +869,8 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) plane->max_stride = ilk_primary_max_stride; } + plane->min_alignment = intel_surf_alignment; + if (IS_I830(dev_priv) || IS_I845G(dev_priv)) { plane->update_arm = i830_plane_update_arm; } else { diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 66436e526021..46f39ab17e43 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -954,6 +954,8 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, cursor->check_plane = i9xx_check_cursor; } + cursor->min_alignment = intel_cursor_alignment; + cursor->cursor.base = ~0; cursor->cursor.cntl = ~0; diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 8fe7942511f8..8a9fd307b81e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1566,6 +1566,9 @@ struct intel_plane { int (*max_height)(const struct drm_framebuffer *fb, int color_plane, unsigned int rotation); + unsigned int (*min_alignment)(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane); unsigned int (*max_stride)(struct intel_plane *plane, u32 pixel_format, u64 modifier, unsigned int rotation); diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 8069abf91c5e..b3a48754a417 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -776,8 +776,12 @@ bool intel_fb_uses_dpt(const struct drm_framebuffer *fb) intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier); } -unsigned int intel_cursor_alignment(const struct drm_i915_private *i915) +unsigned int intel_cursor_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) { + struct drm_i915_private *i915 = to_i915(plane->base.dev); + if (IS_I830(i915)) return 16 * 1024; else if (IS_I85X(i915)) @@ -801,10 +805,11 @@ static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_pr return 0; } -unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, +unsigned int intel_surf_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, int color_plane) { - struct drm_i915_private *dev_priv = to_i915(fb->dev); + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); if (intel_fb_uses_dpt(fb)) { /* AUX_DIST needs only 4K alignment */ @@ -1099,17 +1104,12 @@ u32 intel_plane_compute_aligned_offset(int *x, int *y, const struct intel_plane_state *state, int color_plane) { - struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane); - struct drm_i915_private *i915 = to_i915(intel_plane->base.dev); + struct intel_plane *plane = to_intel_plane(state->uapi.plane); + struct drm_i915_private *i915 = to_i915(plane->base.dev); const struct drm_framebuffer *fb = state->hw.fb; unsigned int rotation = state->hw.rotation; unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; - unsigned int alignment; - - if (intel_plane->id == PLANE_CURSOR) - alignment = intel_cursor_alignment(i915); - else - alignment = intel_surf_alignment(fb, color_plane); + unsigned int alignment = plane->min_alignment(plane, fb, color_plane); return intel_compute_aligned_offset(i915, x, y, fb, color_plane, pitch, rotation, alignment); diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index 23db6628f53e..86c01a3ce81e 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -60,8 +60,11 @@ unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane); unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, int color_plane, unsigned int height); -unsigned int intel_cursor_alignment(const struct drm_i915_private *i915); -unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, +unsigned int intel_cursor_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane); +unsigned int intel_surf_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, int color_plane); void intel_fb_plane_get_subsampling(int *hsub, int *vsub, diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index 1acc11fa19f4..9b0f1ea41b70 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -103,8 +103,9 @@ err: struct i915_vma * intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, - bool phys_cursor, const struct i915_gtt_view *view, + unsigned int alignment, + unsigned int phys_alignment, bool uses_fence, unsigned long *out_flags) { @@ -113,7 +114,6 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, struct drm_i915_gem_object *obj = intel_fb_obj(fb); intel_wakeref_t wakeref; struct i915_gem_ww_ctx ww; - unsigned int alignment; struct i915_vma *vma; unsigned int pinctl; int ret; @@ -121,10 +121,6 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj))) return ERR_PTR(-EINVAL); - if (phys_cursor) - alignment = intel_cursor_alignment(dev_priv); - else - alignment = intel_surf_alignment(fb, 0); if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment))) return ERR_PTR(-EINVAL); @@ -162,8 +158,8 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, i915_gem_ww_ctx_init(&ww, true); retry: ret = i915_gem_object_lock(obj, &ww); - if (!ret && phys_cursor) - ret = i915_gem_object_attach_phys(obj, alignment); + if (!ret && phys_alignment) + ret = i915_gem_object_attach_phys(obj, phys_alignment); else if (!ret && HAS_LMEM(dev_priv)) ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0); if (!ret) @@ -234,6 +230,27 @@ void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags) i915_vma_put(vma); } +static unsigned int +intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state) +{ + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); + const struct drm_framebuffer *fb = plane_state->hw.fb; + + return plane->min_alignment(plane, fb, 0); +} + +static unsigned int +intel_plane_fb_min_phys_alignment(const struct intel_plane_state *plane_state) +{ + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); + const struct drm_framebuffer *fb = plane_state->hw.fb; + + if (!intel_plane_needs_physical(plane)) + return 0; + + return plane->min_alignment(plane, fb, 0); +} + int intel_plane_pin_fb(struct intel_plane_state *plane_state) { struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); @@ -242,8 +259,9 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state) struct i915_vma *vma; if (!intel_fb_uses_dpt(&fb->base)) { - vma = intel_fb_pin_to_ggtt(&fb->base, intel_plane_needs_physical(plane), - &plane_state->view.gtt, + vma = intel_fb_pin_to_ggtt(&fb->base, &plane_state->view.gtt, + intel_plane_fb_min_alignment(plane_state), + intel_plane_fb_min_phys_alignment(plane_state), intel_plane_uses_fence(plane_state), &plane_state->flags); if (IS_ERR(vma)) @@ -261,7 +279,7 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state) plane_state->phys_dma_addr = i915_gem_object_get_dma_address(intel_fb_obj(&fb->base), 0); } else { - unsigned int alignment = intel_surf_alignment(&fb->base, 0); + unsigned int alignment = intel_plane_fb_min_alignment(plane_state); vma = intel_dpt_pin_to_ggtt(fb->dpt_vm, alignment / 512); if (IS_ERR(vma)) diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.h b/drivers/gpu/drm/i915/display/intel_fb_pin.h index 3f8245edcd15..ac0319b53af0 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.h +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.h @@ -15,8 +15,9 @@ struct i915_gtt_view; struct i915_vma * intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, - bool phys_cursor, const struct i915_gtt_view *view, + unsigned int alignment, + unsigned int phys_alignment, bool uses_fence, unsigned long *out_flags); diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index 37ae176bfeb0..6e5f88f20482 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -47,6 +47,7 @@ #include "gem/i915_gem_object.h" #include "i915_drv.h" +#include "intel_crtc.h" #include "intel_display_types.h" #include "intel_fb.h" #include "intel_fb_pin.h" @@ -172,6 +173,21 @@ static const struct fb_ops intelfb_ops = { __diag_pop(); +static unsigned int intel_fbdev_min_alignment(const struct drm_framebuffer *fb) +{ + struct drm_i915_private *i915 = to_i915(fb->dev); + struct intel_plane *plane; + struct intel_crtc *crtc; + + crtc = intel_first_crtc(i915); + if (!crtc) + return 0; + + plane = to_intel_plane(crtc->base.primary); + + return plane->min_alignment(plane, fb, 0); +} + static int intelfb_create(struct drm_fb_helper *helper, struct drm_fb_helper_surface_size *sizes) { @@ -228,8 +244,9 @@ static int intelfb_create(struct drm_fb_helper *helper, * This also validates that any existing fb inherited from the * BIOS is suitable for own access. */ - vma = intel_fb_pin_to_ggtt(&fb->base, false, - &view, false, &flags); + vma = intel_fb_pin_to_ggtt(&fb->base, &view, + intel_fbdev_min_alignment(&fb->base), 0, + false, &flags); if (IS_ERR(vma)) { ret = PTR_ERR(vma); goto out_unlock; diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index e1c907f601da..6f9ae83b095c 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -1622,6 +1622,8 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, } } + plane->min_alignment = intel_surf_alignment; + if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 8a66b1002a74..7e4417459c41 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1680,11 +1680,12 @@ skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, int main_x, int main_y, u32 main_offset, int ccs_plane) { + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); const struct drm_framebuffer *fb = plane_state->hw.fb; int aux_x = plane_state->view.color_plane[ccs_plane].x; int aux_y = plane_state->view.color_plane[ccs_plane].y; u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; - unsigned int alignment = intel_surf_alignment(fb, ccs_plane); + unsigned int alignment = plane->min_alignment(plane, fb, ccs_plane); int hsub; int vsub; @@ -1728,7 +1729,7 @@ int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, const struct drm_framebuffer *fb = plane_state->hw.fb; int aux_plane = skl_main_to_aux_plane(fb, 0); u32 aux_offset = plane_state->view.color_plane[aux_plane].offset; - unsigned int alignment = intel_surf_alignment(fb, 0); + unsigned int alignment = plane->min_alignment(plane, fb, 0); int w = drm_rect_width(&plane_state->uapi.src) >> 16; intel_add_fb_offsets(x, y, plane_state, 0); @@ -1784,7 +1785,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) int min_width = intel_plane_min_width(plane, fb, 0, rotation); int max_width = intel_plane_max_width(plane, fb, 0, rotation); int max_height = intel_plane_max_height(plane, fb, 0, rotation); - unsigned int alignment = intel_surf_alignment(fb, 0); + unsigned int alignment = plane->min_alignment(plane, fb, 0); int aux_plane = skl_main_to_aux_plane(fb, 0); u32 offset; int ret; @@ -1873,7 +1874,7 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) if (ccs_plane) { u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; - unsigned int alignment = intel_surf_alignment(fb, uv_plane); + unsigned int alignment = plane->min_alignment(plane, fb, uv_plane); if (offset > aux_offset) offset = intel_plane_adjust_aligned_offset(&x, &y, @@ -2430,6 +2431,8 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, else plane->max_stride = skl_plane_max_stride; + plane->min_alignment = intel_surf_alignment; + if (DISPLAY_VER(dev_priv) >= 11) { plane->update_noarm = icl_plane_update_noarm; plane->update_arm = icl_plane_update_arm; diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index a2f417209124..a807f869d39f 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -334,8 +334,9 @@ static void __xe_unpin_fb_vma(struct i915_vma *vma) struct i915_vma * intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, - bool phys_cursor, const struct i915_gtt_view *view, + unsigned int alignment, + unsigned int phys_alignment, bool uses_fence, unsigned long *out_flags) { diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c index e135b20962d9..5eccd6abb3ef 100644 --- a/drivers/gpu/drm/xe/display/xe_plane_initial.c +++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c @@ -210,8 +210,8 @@ intel_find_initial_plane_obj(struct intel_crtc *crtc, intel_fb_fill_view(to_intel_framebuffer(fb), plane_state->uapi.rotation, &plane_state->view); - vma = intel_fb_pin_to_ggtt(fb, false, &plane_state->view.gtt, - false, &plane_state->flags); + vma = intel_fb_pin_to_ggtt(fb, &plane_state->view.gtt, + 0, 0, false, &plane_state->flags); if (IS_ERR(vma)) goto nofb; -- cgit v1.2.3 From c7bfd98f00f954e40356cbd80db2dc1992230e94 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 12 Jun 2024 23:47:07 +0300 Subject: drm/i915: Introduce fb->min_alignment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Different planes could have different alignment requirements even for the same format/modifier. Collect the alignment requirements across all planes capable of scanning out the fb such that the alignment is satisfactory to all those planes. So far this was sort of handled by making sure intel_surf_alignment() declares the superset of all planes' alignment requirements, but maintaining that manually is annoying. So we're going to move towards each plane declaring only its own requirements, and thus we need code to generate the superset. v2: Drop the borked per-plane vma optimization (Imre) Assert that the plane's declared alignment is POT (Imre) Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240612204712.31404-5-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_display_types.h | 2 ++ drivers/gpu/drm/i915/display/intel_fb.c | 29 ++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_fb_pin.c | 5 ++-- drivers/gpu/drm/i915/display/intel_fbdev.c | 18 +------------- 4 files changed, 34 insertions(+), 20 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 8a9fd307b81e..ae069993913f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -146,6 +146,8 @@ struct intel_framebuffer { }; struct i915_address_space *dpt_vm; + + unsigned int min_alignment; }; enum intel_hotplug_state { diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index b3a48754a417..0abb80972885 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -11,6 +11,7 @@ #include "gem/i915_gem_object.h" #include "i915_drv.h" +#include "intel_atomic_plane.h" #include "intel_display.h" #include "intel_display_types.h" #include "intel_dpt.h" @@ -1617,6 +1618,32 @@ bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb) fb->base.modifier == I915_FORMAT_MOD_Yf_TILED; } +static unsigned int intel_fb_min_alignment(const struct drm_framebuffer *fb) +{ + struct drm_i915_private *i915 = to_i915(fb->dev); + struct intel_plane *plane; + unsigned int min_alignment = 0; + + for_each_intel_plane(&i915->drm, plane) { + unsigned int plane_min_alignment; + + if (!drm_plane_has_format(&plane->base, fb->format->format, fb->modifier)) + continue; + + plane_min_alignment = plane->min_alignment(plane, fb, 0); + + drm_WARN_ON(&i915->drm, plane_min_alignment && + !is_power_of_2(plane_min_alignment)); + + if (intel_plane_needs_physical(plane)) + continue; + + min_alignment = max(min_alignment, plane_min_alignment); + } + + return min_alignment; +} + int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb) { struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base); @@ -1699,6 +1726,8 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer * return -EINVAL; } + fb->min_alignment = intel_fb_min_alignment(&fb->base); + return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index 9b0f1ea41b70..575b271e012b 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -233,10 +233,9 @@ void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags) static unsigned int intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state) { - struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - const struct drm_framebuffer *fb = plane_state->hw.fb; + const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); - return plane->min_alignment(plane, fb, 0); + return fb->min_alignment; } static unsigned int diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index 6e5f88f20482..49a1ac4f5491 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -47,7 +47,6 @@ #include "gem/i915_gem_object.h" #include "i915_drv.h" -#include "intel_crtc.h" #include "intel_display_types.h" #include "intel_fb.h" #include "intel_fb_pin.h" @@ -173,21 +172,6 @@ static const struct fb_ops intelfb_ops = { __diag_pop(); -static unsigned int intel_fbdev_min_alignment(const struct drm_framebuffer *fb) -{ - struct drm_i915_private *i915 = to_i915(fb->dev); - struct intel_plane *plane; - struct intel_crtc *crtc; - - crtc = intel_first_crtc(i915); - if (!crtc) - return 0; - - plane = to_intel_plane(crtc->base.primary); - - return plane->min_alignment(plane, fb, 0); -} - static int intelfb_create(struct drm_fb_helper *helper, struct drm_fb_helper_surface_size *sizes) { @@ -245,7 +229,7 @@ static int intelfb_create(struct drm_fb_helper *helper, * BIOS is suitable for own access. */ vma = intel_fb_pin_to_ggtt(&fb->base, &view, - intel_fbdev_min_alignment(&fb->base), 0, + fb->min_alignment, 0, false, &flags); if (IS_ERR(vma)) { ret = PTR_ERR(vma); -- cgit v1.2.3 From dde7b1d04433def5cf19123178db2e1e911d4059 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 12 Jun 2024 23:47:08 +0300 Subject: drm/i915: Split cursor alignment to per-platform vfuncs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Split intel_cursor_alignment() into per-platform variants. Reviewed-by: Imre Deak Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240612204712.31404-6-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_cursor.c | 40 +++++++++++++++++++++++++++-- drivers/gpu/drm/i915/display/intel_fb.c | 16 ------------ drivers/gpu/drm/i915/display/intel_fb.h | 3 --- 3 files changed, 38 insertions(+), 21 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 46f39ab17e43..2bd8d02f8703 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -194,6 +194,13 @@ i845_cursor_max_stride(struct intel_plane *plane, return 2048; } +static unsigned int i845_cursor_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + return 32; +} + static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) { u32 cntl = 0; @@ -344,6 +351,28 @@ i9xx_cursor_max_stride(struct intel_plane *plane, return plane->base.dev->mode_config.cursor_width * 4; } +static unsigned int i830_cursor_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + /* "AlmadorM Errata – Requires 32-bpp cursor data to be 16KB aligned." */ + return 16 * 1024; /* physical */ +} + +static unsigned int i85x_cursor_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + return 256; /* physical */ +} + +static unsigned int i9xx_cursor_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + return 4 * 1024; /* physical for i915/i945 */ +} + static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -942,20 +971,27 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { cursor->max_stride = i845_cursor_max_stride; + cursor->min_alignment = i845_cursor_min_alignment; cursor->update_arm = i845_cursor_update_arm; cursor->disable_arm = i845_cursor_disable_arm; cursor->get_hw_state = i845_cursor_get_hw_state; cursor->check_plane = i845_check_cursor; } else { cursor->max_stride = i9xx_cursor_max_stride; + + if (IS_I830(dev_priv)) + cursor->min_alignment = i830_cursor_min_alignment; + else if (IS_I85X(dev_priv)) + cursor->min_alignment = i85x_cursor_min_alignment; + else + cursor->min_alignment = i9xx_cursor_min_alignment; + cursor->update_arm = i9xx_cursor_update_arm; cursor->disable_arm = i9xx_cursor_disable_arm; cursor->get_hw_state = i9xx_cursor_get_hw_state; cursor->check_plane = i9xx_check_cursor; } - cursor->min_alignment = intel_cursor_alignment; - cursor->cursor.base = ~0; cursor->cursor.cntl = ~0; diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 0abb80972885..b5d31ccf013a 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -777,22 +777,6 @@ bool intel_fb_uses_dpt(const struct drm_framebuffer *fb) intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier); } -unsigned int intel_cursor_alignment(struct intel_plane *plane, - const struct drm_framebuffer *fb, - int color_plane) -{ - struct drm_i915_private *i915 = to_i915(plane->base.dev); - - if (IS_I830(i915)) - return 16 * 1024; - else if (IS_I85X(i915)) - return 256; - else if (IS_I845G(i915) || IS_I865G(i915)) - return 32; - else - return 4 * 1024; -} - static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) { if (DISPLAY_VER(dev_priv) >= 9) diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index 86c01a3ce81e..16ebb573643f 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -60,9 +60,6 @@ unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane); unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, int color_plane, unsigned int height); -unsigned int intel_cursor_alignment(struct intel_plane *plane, - const struct drm_framebuffer *fb, - int color_plane); unsigned int intel_surf_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane); -- cgit v1.2.3 From e1488b7ccf3b71407c6479ccd4255c356a941697 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 12 Jun 2024 23:47:09 +0300 Subject: drm/i915: Split pre-skl platforms out from intel_surf_alignment() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Extract the necessary chunks from intel_surf_alignment() into per-platform variants for all pre-skl primary/sprite planes. Reviewed-by: Imre Deak Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240612204712.31404-7-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/i9xx_plane.c | 69 ++++++++++++++++++++++++++++- drivers/gpu/drm/i915/display/intel_fb.c | 17 +------ drivers/gpu/drm/i915/display/intel_sprite.c | 28 +++++++++++- 3 files changed, 96 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 53b18efaa88c..9447f7229b60 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -764,6 +764,66 @@ i8xx_plane_max_stride(struct intel_plane *plane, return 8 * 1024; } +static unsigned int vlv_primary_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + struct drm_i915_private *i915 = to_i915(plane->base.dev); + + switch (fb->modifier) { + case I915_FORMAT_MOD_X_TILED: + if (HAS_ASYNC_FLIPS(i915)) + return 256 * 1024; + return 4 * 1024; + case DRM_FORMAT_MOD_LINEAR: + return 128 * 1024; + default: + MISSING_CASE(fb->modifier); + return 0; + } +} + +static unsigned int g4x_primary_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + struct drm_i915_private *i915 = to_i915(plane->base.dev); + + switch (fb->modifier) { + case I915_FORMAT_MOD_X_TILED: + if (HAS_ASYNC_FLIPS(i915)) + return 256 * 1024; + return 4 * 1024; + case DRM_FORMAT_MOD_LINEAR: + return 4 * 1024; + default: + MISSING_CASE(fb->modifier); + return 0; + } +} + +static unsigned int i965_plane_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + switch (fb->modifier) { + case I915_FORMAT_MOD_X_TILED: + return 4 * 1024; + case DRM_FORMAT_MOD_LINEAR: + return 128 * 1024; + default: + MISSING_CASE(fb->modifier); + return 0; + } +} + +static unsigned int i9xx_plane_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + return 0; +} + static const struct drm_plane_funcs i965_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, @@ -869,7 +929,14 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) plane->max_stride = ilk_primary_max_stride; } - plane->min_alignment = intel_surf_alignment; + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + plane->min_alignment = vlv_primary_min_alignment; + else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) + plane->min_alignment = g4x_primary_min_alignment; + else if (DISPLAY_VER(dev_priv) == 4) + plane->min_alignment = i965_plane_min_alignment; + else + plane->min_alignment = i9xx_plane_min_alignment; if (IS_I830(dev_priv) || IS_I845G(dev_priv)) { plane->update_arm = i830_plane_update_arm; diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index b5d31ccf013a..7f6a3de07cad 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -777,19 +777,6 @@ bool intel_fb_uses_dpt(const struct drm_framebuffer *fb) intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier); } -static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) -{ - if (DISPLAY_VER(dev_priv) >= 9) - return 256 * 1024; - else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || - IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - return 128 * 1024; - else if (DISPLAY_VER(dev_priv) >= 4) - return 4 * 1024; - else - return 0; -} - unsigned int intel_surf_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane) @@ -825,7 +812,7 @@ unsigned int intel_surf_alignment(struct intel_plane *plane, */ if (DISPLAY_VER(dev_priv) >= 12) { if (fb->modifier == DRM_FORMAT_MOD_LINEAR) - return intel_linear_alignment(dev_priv); + return 256 * 1024; return intel_tile_row_size(fb, color_plane); } @@ -837,7 +824,7 @@ unsigned int intel_surf_alignment(struct intel_plane *plane, switch (fb->modifier) { case DRM_FORMAT_MOD_LINEAR: - return intel_linear_alignment(dev_priv); + return 256 * 1024; case I915_FORMAT_MOD_X_TILED: if (HAS_ASYNC_FLIPS(dev_priv)) return 256 * 1024; diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 6f9ae83b095c..f8cceb3e5d8e 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -253,6 +253,21 @@ int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state, return DIV_ROUND_UP(pixel_rate * num, den); } +static unsigned int vlv_sprite_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + switch (fb->modifier) { + case I915_FORMAT_MOD_X_TILED: + return 4 * 1024; + case DRM_FORMAT_MOD_LINEAR: + return 128 * 1024; + default: + MISSING_CASE(fb->modifier); + return 0; + } +} + static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) { u32 sprctl = 0; @@ -964,6 +979,13 @@ hsw_sprite_max_stride(struct intel_plane *plane, return min(8192 * cpp, 16 * 1024); } +static unsigned int g4x_sprite_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + return 4 * 1024; +} + static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) { u32 dvscntr = 0; @@ -1570,6 +1592,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->get_hw_state = vlv_sprite_get_hw_state; plane->check_plane = vlv_sprite_check; plane->max_stride = i965_plane_max_stride; + plane->min_alignment = vlv_sprite_min_alignment; plane->min_cdclk = vlv_plane_min_cdclk; if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { @@ -1596,6 +1619,8 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->min_cdclk = ivb_sprite_min_cdclk; } + plane->min_alignment = g4x_sprite_min_alignment; + formats = snb_sprite_formats; num_formats = ARRAY_SIZE(snb_sprite_formats); @@ -1607,6 +1632,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->get_hw_state = g4x_sprite_get_hw_state; plane->check_plane = g4x_sprite_check; plane->max_stride = g4x_sprite_max_stride; + plane->min_alignment = g4x_sprite_min_alignment; plane->min_cdclk = g4x_sprite_min_cdclk; if (IS_SANDYBRIDGE(dev_priv)) { @@ -1622,8 +1648,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, } } - plane->min_alignment = intel_surf_alignment; - if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | -- cgit v1.2.3 From ee3c3e332d2f2c08a745a7652064dd05a9afeec5 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 12 Jun 2024 23:47:10 +0300 Subject: drm/i915: Move intel_surf_alignment() into skl_univerals_plane.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that all pre-skl platforms have their own .min_alignment() functions the remainder of intel_surf_alignment() can be hoisted into skl_univerals_plane.c (and renamed appropriately). Reviewed-by: Imre Deak Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240612204712.31404-8-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_fb.c | 77 +--------------------- drivers/gpu/drm/i915/display/intel_fb.h | 4 +- drivers/gpu/drm/i915/display/skl_universal_plane.c | 77 +++++++++++++++++++++- 3 files changed, 78 insertions(+), 80 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 7f6a3de07cad..a11c1cf6f548 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -585,7 +585,7 @@ static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_pl return intel_fb_rc_ccs_cc_plane(fb) == color_plane; } -static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane) +bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane) { return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && color_plane == 1; @@ -777,81 +777,6 @@ bool intel_fb_uses_dpt(const struct drm_framebuffer *fb) intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier); } -unsigned int intel_surf_alignment(struct intel_plane *plane, - const struct drm_framebuffer *fb, - int color_plane) -{ - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); - - if (intel_fb_uses_dpt(fb)) { - /* AUX_DIST needs only 4K alignment */ - if (intel_fb_is_ccs_aux_plane(fb, color_plane)) - return 512 * 4096; - - /* - * FIXME ADL sees GGTT/DMAR faults with async - * flips unless we align to 16k at least. - * Figure out what's going on here... - */ - if (IS_ALDERLAKE_P(dev_priv) && - !intel_fb_is_ccs_modifier(fb->modifier) && - HAS_ASYNC_FLIPS(dev_priv)) - return 512 * 16 * 1024; - - return 512 * 4096; - } - - /* AUX_DIST needs only 4K alignment */ - if (intel_fb_is_ccs_aux_plane(fb, color_plane)) - return 4096; - - if (is_semiplanar_uv_plane(fb, color_plane)) { - /* - * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes - * alignment for linear UV planes on all platforms. - */ - if (DISPLAY_VER(dev_priv) >= 12) { - if (fb->modifier == DRM_FORMAT_MOD_LINEAR) - return 256 * 1024; - - return intel_tile_row_size(fb, color_plane); - } - - return 4096; - } - - drm_WARN_ON(&dev_priv->drm, color_plane != 0); - - switch (fb->modifier) { - case DRM_FORMAT_MOD_LINEAR: - return 256 * 1024; - case I915_FORMAT_MOD_X_TILED: - if (HAS_ASYNC_FLIPS(dev_priv)) - return 256 * 1024; - return 0; - case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: - case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: - case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: - case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: - return 16 * 1024; - case I915_FORMAT_MOD_Y_TILED_CCS: - case I915_FORMAT_MOD_Yf_TILED_CCS: - case I915_FORMAT_MOD_Y_TILED: - case I915_FORMAT_MOD_4_TILED: - case I915_FORMAT_MOD_Yf_TILED: - return 1 * 1024 * 1024; - case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: - case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: - case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: - return 16 * 1024; - default: - MISSING_CASE(fb->modifier); - return 0; - } -} - void intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane) diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index 16ebb573643f..1b1fef2dc39a 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -34,6 +34,7 @@ bool intel_fb_is_ccs_modifier(u64 modifier); bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier); bool intel_fb_is_mc_ccs_modifier(u64 modifier); +bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane); bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane); int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb); @@ -60,9 +61,6 @@ unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane); unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, int color_plane, unsigned int height); -unsigned int intel_surf_alignment(struct intel_plane *plane, - const struct drm_framebuffer *fb, - int color_plane); void intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 7e4417459c41..d4c1db3fb9e3 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -503,6 +503,81 @@ skl_plane_max_stride(struct intel_plane *plane, max_pixels, max_bytes); } +static unsigned int skl_plane_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + + if (intel_fb_uses_dpt(fb)) { + /* AUX_DIST needs only 4K alignment */ + if (intel_fb_is_ccs_aux_plane(fb, color_plane)) + return 512 * 4096; + + /* + * FIXME ADL sees GGTT/DMAR faults with async + * flips unless we align to 16k at least. + * Figure out what's going on here... + */ + if (IS_ALDERLAKE_P(dev_priv) && + !intel_fb_is_ccs_modifier(fb->modifier) && + HAS_ASYNC_FLIPS(dev_priv)) + return 512 * 16 * 1024; + + return 512 * 4096; + } + + /* AUX_DIST needs only 4K alignment */ + if (intel_fb_is_ccs_aux_plane(fb, color_plane)) + return 4096; + + if (is_semiplanar_uv_plane(fb, color_plane)) { + /* + * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes + * alignment for linear UV planes on all platforms. + */ + if (DISPLAY_VER(dev_priv) >= 12) { + if (fb->modifier == DRM_FORMAT_MOD_LINEAR) + return 256 * 1024; + + return intel_tile_row_size(fb, color_plane); + } + + return 4096; + } + + drm_WARN_ON(&dev_priv->drm, color_plane != 0); + + switch (fb->modifier) { + case DRM_FORMAT_MOD_LINEAR: + return 256 * 1024; + case I915_FORMAT_MOD_X_TILED: + if (HAS_ASYNC_FLIPS(dev_priv)) + return 256 * 1024; + return 0; + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: + return 16 * 1024; + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: + case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_4_TILED: + case I915_FORMAT_MOD_Yf_TILED: + return 1 * 1024 * 1024; + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: + return 16 * 1024; + default: + MISSING_CASE(fb->modifier); + return 0; + } +} + /* Preoffset values for YUV to RGB Conversion */ #define PREOFF_YUV_TO_RGB_HI 0x1800 #define PREOFF_YUV_TO_RGB_ME 0x0000 @@ -2431,7 +2506,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, else plane->max_stride = skl_plane_max_stride; - plane->min_alignment = intel_surf_alignment; + plane->min_alignment = skl_plane_min_alignment; if (DISPLAY_VER(dev_priv) >= 11) { plane->update_noarm = icl_plane_update_noarm; -- cgit v1.2.3 From 7652126ce7070ddcd1b3f8791efcf7537a9ec01e Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 12 Jun 2024 23:47:11 +0300 Subject: drm/i915: Update plane alignment requirements for TGL+ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently we still use the SKL+ PLANE_SURF alignment even for TGL+ even though the hardware no longer needs it. Introduce a separate tgl_plane_min_alignment() and update it to more accurately reflect the hardware requirements. v2: Don't screw up DPT+semiplanar 2MiB alignment Reviewed-by: Imre Deak Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240612204712.31404-9-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 99 ++++++++++++---------- 1 file changed, 56 insertions(+), 43 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index d4c1db3fb9e3..a1c4778cf656 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -503,75 +503,85 @@ skl_plane_max_stride(struct intel_plane *plane, max_pixels, max_bytes); } -static unsigned int skl_plane_min_alignment(struct intel_plane *plane, - const struct drm_framebuffer *fb, - int color_plane) +static u32 tgl_plane_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); - - if (intel_fb_uses_dpt(fb)) { - /* AUX_DIST needs only 4K alignment */ - if (intel_fb_is_ccs_aux_plane(fb, color_plane)) - return 512 * 4096; - - /* - * FIXME ADL sees GGTT/DMAR faults with async - * flips unless we align to 16k at least. - * Figure out what's going on here... - */ - if (IS_ALDERLAKE_P(dev_priv) && - !intel_fb_is_ccs_modifier(fb->modifier) && - HAS_ASYNC_FLIPS(dev_priv)) - return 512 * 16 * 1024; - - return 512 * 4096; - } + struct drm_i915_private *i915 = to_i915(plane->base.dev); + /* PLANE_SURF GGTT -> DPT alignment */ + int mult = intel_fb_uses_dpt(fb) ? 512 : 1; /* AUX_DIST needs only 4K alignment */ if (intel_fb_is_ccs_aux_plane(fb, color_plane)) - return 4096; + return mult * 4 * 1024; if (is_semiplanar_uv_plane(fb, color_plane)) { + if (intel_fb_uses_dpt(fb)) + return 512 * 4 * 1024; + /* * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes * alignment for linear UV planes on all platforms. */ - if (DISPLAY_VER(dev_priv) >= 12) { - if (fb->modifier == DRM_FORMAT_MOD_LINEAR) - return 256 * 1024; - - return intel_tile_row_size(fb, color_plane); - } + if (fb->modifier == DRM_FORMAT_MOD_LINEAR) + return 256 * 1024; - return 4096; + return intel_tile_row_size(fb, color_plane); } - drm_WARN_ON(&dev_priv->drm, color_plane != 0); - switch (fb->modifier) { case DRM_FORMAT_MOD_LINEAR: - return 256 * 1024; case I915_FORMAT_MOD_X_TILED: - if (HAS_ASYNC_FLIPS(dev_priv)) - return 256 * 1024; - return 0; + case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_4_TILED: + /* + * FIXME ADL sees GGTT/DMAR faults with async + * flips unless we align to 16k at least. + * Figure out what's going on here... + */ + if (IS_ALDERLAKE_P(i915) && HAS_ASYNC_FLIPS(i915)) + return mult * 16 * 1024; + return mult * 4 * 1024; case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: - return 16 * 1024; + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: + /* + * Align to at least 4x1 main surface + * tiles (16K) to match 64B of AUX. + */ + return max(mult * 4 * 1024, 16 * 1024); + default: + MISSING_CASE(fb->modifier); + return 0; + } +} + +static u32 skl_plane_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) +{ + /* + * AUX_DIST needs only 4K alignment, + * as does ICL UV PLANE_SURF. + */ + if (color_plane != 0) + return 4 * 1024; + + switch (fb->modifier) { + case DRM_FORMAT_MOD_LINEAR: + case I915_FORMAT_MOD_X_TILED: + return 256 * 1024; case I915_FORMAT_MOD_Y_TILED_CCS: case I915_FORMAT_MOD_Yf_TILED_CCS: case I915_FORMAT_MOD_Y_TILED: - case I915_FORMAT_MOD_4_TILED: case I915_FORMAT_MOD_Yf_TILED: return 1 * 1024 * 1024; - case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: - case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: - case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: - return 16 * 1024; default: MISSING_CASE(fb->modifier); return 0; @@ -2506,7 +2516,10 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, else plane->max_stride = skl_plane_max_stride; - plane->min_alignment = skl_plane_min_alignment; + if (DISPLAY_VER(dev_priv) >= 12) + plane->min_alignment = tgl_plane_min_alignment; + else + plane->min_alignment = skl_plane_min_alignment; if (DISPLAY_VER(dev_priv) >= 11) { plane->update_noarm = icl_plane_update_noarm; -- cgit v1.2.3 From f8fa26f4e09230137a304a5275d2633a6de11c7d Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 12 Jun 2024 23:47:12 +0300 Subject: drm/i915: Nuke the TGL+ chroma plane tile row alignment stuff MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I don't think the display hardware really has such chroma plane tile row alignment requirements as outlined in commit d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned") Bspec had the same exact thing to say about earlier hardware as well, but we never cared and things work just fine. The one thing mentioned in that commit that is definitely true however is the fence alignment issue. But we don't deal with that on earlier hardware either. We do have code to deal with that issue for the first color plane, but not the chroma planes. So I think if we did want to check this more extensively we should do it in the same places where we already check the first color plane (namely convert_plane_offset_to_xy() and intel_fb_bo_framebuffer_init()). Reviewed-by: Imre Deak Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240612204712.31404-10-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_fb.c | 12 +----------- drivers/gpu/drm/i915/display/intel_fb.h | 1 - drivers/gpu/drm/i915/display/skl_universal_plane.c | 14 -------------- 3 files changed, 1 insertion(+), 26 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index a11c1cf6f548..f23547a88b1f 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -585,12 +585,6 @@ static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_pl return intel_fb_rc_ccs_cc_plane(fb) == color_plane; } -bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane) -{ - return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && - color_plane == 1; -} - bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane) { return fb->modifier == DRM_FORMAT_MOD_LINEAR || @@ -1020,11 +1014,7 @@ static int intel_fb_offset_to_xy(int *x, int *y, struct drm_i915_private *i915 = to_i915(fb->dev); unsigned int height, alignment, unused; - if (DISPLAY_VER(i915) >= 12 && - !intel_fb_needs_pot_stride_remap(to_intel_framebuffer(fb)) && - is_semiplanar_uv_plane(fb, color_plane)) - alignment = intel_tile_row_size(fb, color_plane); - else if (fb->modifier != DRM_FORMAT_MOD_LINEAR) + if (fb->modifier != DRM_FORMAT_MOD_LINEAR) alignment = intel_tile_size(i915); else alignment = 0; diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index 1b1fef2dc39a..6dee0c8b7f22 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -34,7 +34,6 @@ bool intel_fb_is_ccs_modifier(u64 modifier); bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier); bool intel_fb_is_mc_ccs_modifier(u64 modifier); -bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane); bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane); int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb); diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index a1c4778cf656..ba5a628b4757 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -515,20 +515,6 @@ static u32 tgl_plane_min_alignment(struct intel_plane *plane, if (intel_fb_is_ccs_aux_plane(fb, color_plane)) return mult * 4 * 1024; - if (is_semiplanar_uv_plane(fb, color_plane)) { - if (intel_fb_uses_dpt(fb)) - return 512 * 4 * 1024; - - /* - * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes - * alignment for linear UV planes on all platforms. - */ - if (fb->modifier == DRM_FORMAT_MOD_LINEAR) - return 256 * 1024; - - return intel_tile_row_size(fb, color_plane); - } - switch (fb->modifier) { case DRM_FORMAT_MOD_LINEAR: case I915_FORMAT_MOD_X_TILED: -- cgit v1.2.3 From 12f84e8793af19357e2270b24b9e8d453bb3a1f2 Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Wed, 22 May 2024 07:33:39 +0200 Subject: drm: Add drm_vblank_work_flush_all(). In some cases we want to flush all vblank work, right before vblank_off for example. Add a simple function to make this possible. Check that both pending_work and running work are empty when flushing. Co-Developed-by: Chaitanya Kumar Borah Signed-off-by: Maarten Lankhorst Reviewed-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20240522053341.137592-2-maarten.lankhorst@linux.intel.com --- drivers/gpu/drm/drm_vblank_work.c | 22 ++++++++++++++++++++++ include/drm/drm_vblank_work.h | 2 ++ 2 files changed, 24 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_vblank_work.c b/drivers/gpu/drm/drm_vblank_work.c index 4fe9b1d3b00f..1752ffb44e1d 100644 --- a/drivers/gpu/drm/drm_vblank_work.c +++ b/drivers/gpu/drm/drm_vblank_work.c @@ -232,6 +232,28 @@ void drm_vblank_work_flush(struct drm_vblank_work *work) } EXPORT_SYMBOL(drm_vblank_work_flush); +/** + * drm_vblank_work_flush_all - flush all currently pending vblank work on crtc. + * @crtc: crtc for which vblank work to flush + * + * Wait until all currently queued vblank work on @crtc + * has finished executing once. + */ +void drm_vblank_work_flush_all(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(crtc)]; + + spin_lock_irq(&dev->event_lock); + wait_event_lock_irq(vblank->work_wait_queue, + list_empty(&vblank->pending_work), + dev->event_lock); + spin_unlock_irq(&dev->event_lock); + + kthread_flush_worker(vblank->worker); +} +EXPORT_SYMBOL(drm_vblank_work_flush_all); + /** * drm_vblank_work_init - initialize a vblank work item * @work: vblank work item diff --git a/include/drm/drm_vblank_work.h b/include/drm/drm_vblank_work.h index eb41d0810c4f..e04d436b7297 100644 --- a/include/drm/drm_vblank_work.h +++ b/include/drm/drm_vblank_work.h @@ -17,6 +17,7 @@ struct drm_crtc; * drm_vblank_work_init() * drm_vblank_work_cancel_sync() * drm_vblank_work_flush() + * drm_vblank_work_flush_all() */ struct drm_vblank_work { /** @@ -67,5 +68,6 @@ void drm_vblank_work_init(struct drm_vblank_work *work, struct drm_crtc *crtc, void (*func)(struct kthread_work *work)); bool drm_vblank_work_cancel_sync(struct drm_vblank_work *work); void drm_vblank_work_flush(struct drm_vblank_work *work); +void drm_vblank_work_flush_all(struct drm_crtc *crtc); #endif /* !_DRM_VBLANK_WORK_H_ */ -- cgit v1.2.3 From bb8624de096340daec29137f56ea711fbcdea450 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 22 May 2024 07:33:40 +0200 Subject: drm/i915: Use vblank worker to unpin old legacy cursor fb safely MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The cursor hardware only does sync updates, and thus the hardware will be scanning out from the old fb until the next start of vblank. So in order to make the legacy cursor fastpath actually safe we should not unpin the old fb until we're sure the hardware has ceased accessing it. The simplest approach is to just use a vblank work here to do the delayed unpin. Not 100% sure it's a good idea to put this onto the same high priority vblank worker as eg. our timing critical gamma updates. But let's keep it simple for now, and it we later discover that this is causing problems we can think about adding a lower priority worker for such things. This patch is slightly reworked by Maarten Cc: Maarten Lankhorst Signed-off-by: Ville Syrjälä Signed-off-by: Maarten Lankhorst Reviewed-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20240522053341.137592-3-maarten.lankhorst@linux.intel.com --- drivers/gpu/drm/i915/display/intel_cursor.c | 26 ++++++++++++++++++++-- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++ 3 files changed, 30 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 2bd8d02f8703..1c5bc3cf4a68 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -761,6 +761,17 @@ static bool intel_cursor_format_mod_supported(struct drm_plane *_plane, return format == DRM_FORMAT_ARGB8888; } +static void intel_cursor_unpin_work(struct kthread_work *base) +{ + struct drm_vblank_work *work = to_drm_vblank_work(base); + struct intel_plane_state *plane_state = + container_of(work, typeof(*plane_state), unpin_work); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); + + intel_plane_unpin_fb(plane_state); + intel_plane_destroy_state(&plane->base, &plane_state->uapi); +} + static int intel_legacy_cursor_update(struct drm_plane *_plane, struct drm_crtc *_crtc, @@ -904,14 +915,25 @@ intel_legacy_cursor_update(struct drm_plane *_plane, intel_psr_unlock(crtc_state); - intel_plane_unpin_fb(old_plane_state); + if (old_plane_state->ggtt_vma != new_plane_state->ggtt_vma) { + drm_vblank_work_init(&old_plane_state->unpin_work, &crtc->base, + intel_cursor_unpin_work); + + drm_vblank_work_schedule(&old_plane_state->unpin_work, + drm_crtc_accurate_vblank_count(&crtc->base) + 1, + false); + + old_plane_state = NULL; + } else { + intel_plane_unpin_fb(old_plane_state); + } out_free: if (new_crtc_state) intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi); if (ret) intel_plane_destroy_state(&plane->base, &new_plane_state->uapi); - else + else if (old_plane_state) intel_plane_destroy_state(&plane->base, &old_plane_state->uapi); return ret; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c782e65a7123..c2c388212e2e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -68,6 +68,7 @@ #include "intel_crtc_state_dump.h" #include "intel_cursor_regs.h" #include "intel_cx0_phy.h" +#include "intel_cursor.h" #include "intel_ddi.h" #include "intel_de.h" #include "intel_display_driver.h" @@ -7020,6 +7021,8 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state) continue; intel_crtc_disable_planes(state, crtc); + + drm_vblank_work_flush_all(&crtc->base); } /* Only disable port sync and MST slaves */ diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index ae069993913f..8713835e2307 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -744,6 +744,9 @@ struct intel_plane_state { struct intel_fb_view view; u32 phys_dma_addr; /* for cursor_needs_physical */ + /* for legacy cursor fb unpin */ + struct drm_vblank_work unpin_work; + /* Plane pxp decryption state */ bool decrypt; -- cgit v1.2.3 From a441c0aca4552a1b959b26526854a97544d10ecb Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Wed, 22 May 2024 07:33:41 +0200 Subject: drm/i915: Use the same vblank worker for atomic unpin In case of legacy cursor update, the cursor VMA needs to be unpinned only after vblank. This exceeds the lifetime of the whole atomic commit. Any trick I attempted to keep the atomic commit alive didn't work, as drm_atomic_helper_setup_commit() force throttles on any old commit that wasn't cleaned up. The only option remaining is to remove the plane from the atomic commit, and use the same path as the legacy cursor update to clean the state after vblank. Changes since previous version: - Call the memset for plane state immediately when scheduling vblank, this prevents a use-after-free in cursor cleanup. Signed-off-by: Maarten Lankhorst Reviewed-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20240522053341.137592-4-maarten.lankhorst@linux.intel.com --- drivers/gpu/drm/i915/display/intel_atomic_plane.c | 13 +++++++++- drivers/gpu/drm/i915/display/intel_atomic_plane.h | 2 ++ drivers/gpu/drm/i915/display/intel_crtc.c | 31 +++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_cursor.c | 2 +- drivers/gpu/drm/i915/display/intel_cursor.h | 3 +++ 5 files changed, 49 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 79244ea06b9a..e979786aa5cf 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -43,6 +43,7 @@ #include "i9xx_plane_regs.h" #include "intel_atomic_plane.h" #include "intel_cdclk.h" +#include "intel_cursor.h" #include "intel_display_rps.h" #include "intel_display_trace.h" #include "intel_display_types.h" @@ -1201,7 +1202,6 @@ intel_cleanup_plane_fb(struct drm_plane *plane, intel_display_rps_mark_interactive(dev_priv, state, false); - /* Should only be called after a successful intel_prepare_plane_fb()! */ intel_plane_unpin_fb(old_plane_state); } @@ -1214,3 +1214,14 @@ void intel_plane_helper_add(struct intel_plane *plane) { drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); } + +void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_plane_state, + struct intel_plane_state *new_plane_state) +{ + if (!old_plane_state->ggtt_vma || + old_plane_state->ggtt_vma == new_plane_state->ggtt_vma) + return; + + drm_vblank_work_init(&old_plane_state->unpin_work, old_plane_state->uapi.crtc, + intel_cursor_unpin_work); +} diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h index 84541d97c67b..6c4fe3596465 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h @@ -71,5 +71,7 @@ void intel_plane_set_invisible(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state); void intel_plane_helper_add(struct intel_plane *plane); bool intel_plane_needs_physical(struct intel_plane *plane); +void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_plane_state, + struct intel_plane_state *new_plane_state); #endif /* __INTEL_ATOMIC_PLANE_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index a2b8953d7283..1b578cad2813 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -496,6 +496,19 @@ void intel_pipe_update_start(struct intel_atomic_state *state, if (intel_crtc_needs_vblank_work(new_crtc_state)) intel_crtc_vblank_work_init(new_crtc_state); + if (state->base.legacy_cursor_update) { + struct intel_plane *plane; + struct intel_plane_state *old_plane_state, *new_plane_state; + int i; + + for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, + new_plane_state, i) { + if (old_plane_state->uapi.crtc == &crtc->base) + intel_plane_init_cursor_vblank_work(old_plane_state, + new_plane_state); + } + } + intel_vblank_evade_init(old_crtc_state, new_crtc_state, &evade); if (drm_WARN_ON(&dev_priv->drm, drm_crtc_vblank_get(&crtc->base))) @@ -621,6 +634,24 @@ void intel_pipe_update_end(struct intel_atomic_state *state, intel_crtc_arm_vblank_event(new_crtc_state); } + if (state->base.legacy_cursor_update) { + struct intel_plane *plane; + struct intel_plane_state *old_plane_state; + int i; + + for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { + if (old_plane_state->uapi.crtc == &crtc->base && + old_plane_state->unpin_work.vblank) { + drm_vblank_work_schedule(&old_plane_state->unpin_work, + drm_crtc_accurate_vblank_count(&crtc->base) + 1, + false); + + /* Remove plane from atomic state, cleanup/free is done from vblank worker. */ + memset(&state->base.planes[i], 0, sizeof(state->base.planes[i])); + } + } + } + /* * Send VRR Push to terminate Vblank. If we are already in vblank * this has to be done _after_ sampling the frame counter, as diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 1c5bc3cf4a68..9ad53e1cbbd0 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -761,7 +761,7 @@ static bool intel_cursor_format_mod_supported(struct drm_plane *_plane, return format == DRM_FORMAT_ARGB8888; } -static void intel_cursor_unpin_work(struct kthread_work *base) +void intel_cursor_unpin_work(struct kthread_work *base) { struct drm_vblank_work *work = to_drm_vblank_work(base); struct intel_plane_state *plane_state = diff --git a/drivers/gpu/drm/i915/display/intel_cursor.h b/drivers/gpu/drm/i915/display/intel_cursor.h index ce333bf4c2d5..e2d9ec710a86 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.h +++ b/drivers/gpu/drm/i915/display/intel_cursor.h @@ -9,9 +9,12 @@ enum pipe; struct drm_i915_private; struct intel_plane; +struct kthread_work; struct intel_plane * intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe); +void intel_cursor_unpin_work(struct kthread_work *base); + #endif -- cgit v1.2.3 From 897d29ce229569bb497861c9673e6f828521384d Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Wed, 19 Jun 2024 09:21:21 +0300 Subject: drm/i915/psr: Check panel ALPM capability for eDP Panel Replay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Our HW doesn't support Panel Replay without AUX_LESS ALPM on eDP. Check panel support for this and prevent eDP panel replay if it doesn't exits. Bspec: 68920 v3: remove excessive parens v2: use intel_alpm_aux_less_wake_supported Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-2-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 0dbcaf644624..777aaa26464e 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -571,6 +571,13 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); + if (intel_dp_is_edp(intel_dp) && + !intel_alpm_aux_less_wake_supported(intel_dp)) { + drm_dbg_kms(&i915->drm, + "Panel doesn't support AUX-less ALPM, eDP Panel Replay not possible\n"); + return; + } + intel_dp->psr.sink_panel_replay_support = true; if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT) -- cgit v1.2.3 From dfeb3a249f11787b269eb15d0de6c91dc4e3292f Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Wed, 19 Jun 2024 09:21:22 +0300 Subject: drm/i915/psr: Inform Panel Replay source support on eDP as well MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Display version >= 20 support eDP 1.5. Inform Panel Replay source support on eDP for display version >= 20. Bspec: 68920 Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-3-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 777aaa26464e..f4626699a37e 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3115,9 +3115,11 @@ void intel_psr_init(struct intel_dp *intel_dp) return; } - if (HAS_DP20(dev_priv) && !intel_dp_is_edp(intel_dp)) + if ((HAS_DP20(dev_priv) && !intel_dp_is_edp(intel_dp)) || + DISPLAY_VER(dev_priv) >= 20) intel_dp->psr.source_panel_replay_support = true; - else + + if (HAS_PSR(dev_priv) && intel_dp_is_edp(intel_dp)) intel_dp->psr.source_support = true; /* Set link_standby x link_off defaults */ -- cgit v1.2.3 From 67cf05473704e926d2b5302a68433a6aefde6fc5 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Wed, 19 Jun 2024 09:21:23 +0300 Subject: drm/i915/psr: enable sink for eDP1.5 Panel Replay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit eDP1.5 allows Panel Replay on eDP as well. Take this into account when enabling sink PSR/Panel Replay. Write also PANEL_REPLAY_CONFIG2 register accordingly. v3: - set DP_PANEL_REPLAY_CRC_VERIFICATION in PANEL_REPLAY_CONFIG2 - PANEL_REPLAY_CONFIG2 is available in DP2.1 as well v2: do not configure ALPM for DP2.0 Panel Replay Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-4-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 36 ++++++++++++++++++++++++++------ 1 file changed, 30 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index f4626699a37e..253888c7ea1d 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -713,6 +713,7 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp, DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN | DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN | DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN; + u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION; if (crtc_state->has_sel_update) val |= DP_PANEL_REPLAY_SU_ENABLE; @@ -720,7 +721,14 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp, if (crtc_state->enable_psr2_su_region_et) val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET; + if (crtc_state->req_psr2_sdp_prior_scanline) + panel_replay_config2 |= + DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE; + drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val); + + drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2, + panel_replay_config2); } static void _psr_enable_sink(struct intel_dp *intel_dp, @@ -751,15 +759,31 @@ static void _psr_enable_sink(struct intel_dp *intel_dp, drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); } +static void intel_psr_enable_sink_alpm(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + u8 val; + + /* + * eDP Panel Replay uses always ALPM + * PSR2 uses ALPM but PSR1 doesn't + */ + if (!intel_dp_is_edp(intel_dp) || (!crtc_state->has_panel_replay && + !crtc_state->has_sel_update)) + return; + + val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE; + + if (crtc_state->has_panel_replay) + val |= DP_ALPM_MODE_AUX_LESS; + + drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val); +} + void intel_psr_enable_sink(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { - /* Enable ALPM at sink for psr2 */ - if (!crtc_state->has_panel_replay && crtc_state->has_sel_update) - drm_dp_dpcd_writeb(&intel_dp->aux, - DP_RECEIVER_ALPM_CONFIG, - DP_ALPM_ENABLE | - DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); + intel_psr_enable_sink_alpm(intel_dp, crtc_state); crtc_state->has_panel_replay ? _panel_replay_enable_sink(intel_dp, crtc_state) : -- cgit v1.2.3 From 5d9993f88378a68458af101bfda82754d80fb33f Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Wed, 19 Jun 2024 09:21:24 +0300 Subject: drm/i915/psr: Check panel Early Transport capability for eDP PR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Our HW doesn't support panel replay without Early Transport on eDP. Bspec: 68920 Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-5-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 253888c7ea1d..8e367a4f4da3 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -571,11 +571,18 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); - if (intel_dp_is_edp(intel_dp) && - !intel_alpm_aux_less_wake_supported(intel_dp)) { - drm_dbg_kms(&i915->drm, - "Panel doesn't support AUX-less ALPM, eDP Panel Replay not possible\n"); - return; + if (intel_dp_is_edp(intel_dp)) { + if (!intel_alpm_aux_less_wake_supported(intel_dp)) { + drm_dbg_kms(&i915->drm, + "Panel doesn't support AUX-less ALPM, eDP Panel Replay not possible\n"); + return; + } + + if (!(intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) { + drm_dbg_kms(&i915->drm, + "Panel doesn't support early transport, eDP Panel Replay not possible\n"); + return; + } } intel_dp->psr.sink_panel_replay_support = true; -- cgit v1.2.3 From 397b51ef1ab28b1c807c042f455b47c720984473 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Wed, 19 Jun 2024 09:21:25 +0300 Subject: drm/i915/psr: 128b/132b Panel Replay is not supported on eDP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Take into account that 128b/132b Panel Replay is not supported on eDP. Bspec: 68920 v2: - make crtc_state as const - add debug message to print out why Panel Replay is not possible Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-6-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 8e367a4f4da3..8f8148afe8e8 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1517,7 +1517,10 @@ static bool _psr_compute_config(struct intel_dp *intel_dp, return true; } -static bool _panel_replay_compute_config(struct intel_dp *intel_dp) +static bool +_panel_replay_compute_config(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -1529,6 +1532,18 @@ static bool _panel_replay_compute_config(struct intel_dp *intel_dp) return false; } + if (!intel_dp_is_edp(intel_dp)) + return true; + + /* Remaining checks are for eDP only */ + + /* 128b/132b Panel Replay is not supported on eDP */ + if (intel_dp_is_uhbr(crtc_state)) { + drm_dbg_kms(&i915->drm, + "Panel Replay is not supported with 128b/132b\n"); + return false; + } + return true; } @@ -1567,7 +1582,9 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, return; } - crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp); + crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp, + crtc_state, + conn_state); crtc_state->has_psr = crtc_state->has_panel_replay ? true : _psr_compute_config(intel_dp, crtc_state); -- cgit v1.2.3 From 0bc96a4ba99a9ef35a9cac55cc1772016ff890a2 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Wed, 19 Jun 2024 09:21:26 +0300 Subject: drm/i915/psr: HW will not allow PR on eDP when HDCP enabled MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Take into account in Panel Replay compute config that HW will not allow PR on eDP when HDCP enabled. v2: add debug message to print out why Panel Replay is not possible Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-7-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 8f8148afe8e8..91c9b3f8b705 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1523,6 +1523,9 @@ _panel_replay_compute_config(struct intel_dp *intel_dp, const struct drm_connector_state *conn_state) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct intel_connector *connector = + to_intel_connector(conn_state->connector); + struct intel_hdcp *hdcp = &connector->hdcp; if (!CAN_PANEL_REPLAY(intel_dp)) return false; @@ -1544,6 +1547,17 @@ _panel_replay_compute_config(struct intel_dp *intel_dp, return false; } + /* HW will not allow Panel Replay on eDP when HDCP enabled */ + if (conn_state->content_protection == + DRM_MODE_CONTENT_PROTECTION_DESIRED || + (conn_state->content_protection == + DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value == + DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) { + drm_dbg_kms(&i915->drm, + "Panel Replay is not supported with HDCP\n"); + return false; + } + return true; } -- cgit v1.2.3 From 5d81c2986926d61dec0eb7dc5e96c4b40bf3d95e Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Wed, 19 Jun 2024 09:21:27 +0300 Subject: drm/i915/alpm: Make crtc_state as const in intel_alpm_compute_params MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Intel_alpm_compute_params doesn't change crtc_state. Let's convert it as const. Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-8-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_alpm.c | 9 +++++---- drivers/gpu/drm/i915/display/intel_alpm.h | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index c7092af7da33..866b3b409c4d 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -135,8 +135,9 @@ static int _lnl_compute_aux_less_wake_time(int port_clock) t1 + tcds, 1000); } -static int _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp, - struct intel_crtc_state *crtc_state) +static int +_lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); int aux_less_wake_time, aux_less_wake_lines, silence_period, @@ -168,7 +169,7 @@ static int _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp, } static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp, - struct intel_crtc_state *crtc_state) + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); int check_entry_lines; @@ -220,7 +221,7 @@ static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state) } bool intel_alpm_compute_params(struct intel_dp *intel_dp, - struct intel_crtc_state *crtc_state) + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time; diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h index d4fb60393c91..8c409b10dce6 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.h +++ b/drivers/gpu/drm/i915/display/intel_alpm.h @@ -15,7 +15,7 @@ struct intel_connector; void intel_alpm_init_dpcd(struct intel_dp *intel_dp); bool intel_alpm_compute_params(struct intel_dp *intel_dp, - struct intel_crtc_state *crtc_state); + const struct intel_crtc_state *crtc_state); void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state); -- cgit v1.2.3 From a18114ebaaa89284d9da7d0f80bafcf8848ef520 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Wed, 19 Jun 2024 09:21:28 +0300 Subject: drm/i915/psr: Perform psr2 checks related to ALPM for Panel Replay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit eDP1.5 support ALPM with Panel Replay as well. We need to check ALPM related things for Panel Replay as well. Bspec: 68920 v5: - instead of using crtc_state->has_panel_replay provide aux_less flag v4: - do not move _compute_psr2_sdp_prior_scanline_indication - move ALPM related checks to separate function v3: move vblank check as well v2: do not move Vblank >= PSR2_CTL Block Count Number maximum line count check Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-9-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 41 ++++++++++++++++++++++---------- 1 file changed, 28 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 91c9b3f8b705..ba6497622435 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1306,14 +1306,15 @@ static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp, } static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state) + const struct intel_crtc_state *crtc_state, + bool aux_less) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end - crtc_state->hw.adjusted_mode.crtc_vblank_start; int wake_lines; - if (crtc_state->has_panel_replay) + if (aux_less) wake_lines = intel_dp->alpm_parameters.aux_less_wake_lines; else wake_lines = DISPLAY_VER(i915) < 20 ? @@ -1330,6 +1331,27 @@ static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp, return true; } +static bool alpm_config_valid(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + bool aux_less) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + if (!intel_alpm_compute_params(intel_dp, crtc_state)) { + drm_dbg_kms(&i915->drm, + "PSR2/Panel Replay not enabled, Unable to use long enough wake times\n"); + return false; + } + + if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less)) { + drm_dbg_kms(&i915->drm, + "PSR2/Panel Replay not enabled, too short vblank time\n"); + return false; + } + + return true; +} + static bool intel_psr2_config_valid(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { @@ -1413,18 +1435,8 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - if (!intel_alpm_compute_params(intel_dp, crtc_state)) { - drm_dbg_kms(&dev_priv->drm, - "PSR2 not enabled, Unable to use long enough wake times\n"); + if (!alpm_config_valid(intel_dp, crtc_state, false)) return false; - } - - /* Vblank >= PSR2_CTL Block Count Number maximum line count */ - if (!wake_lines_fit_into_vblank(intel_dp, crtc_state)) { - drm_dbg_kms(&dev_priv->drm, - "PSR2 not enabled, too short vblank time\n"); - return false; - } if (!crtc_state->enable_psr2_sel_fetch && (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { @@ -1558,6 +1570,9 @@ _panel_replay_compute_config(struct intel_dp *intel_dp, return false; } + if (!alpm_config_valid(intel_dp, crtc_state, true)) + return false; + return true; } -- cgit v1.2.3 From 0cd2bdbf19ac4d77be47564a678618fa70681474 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Wed, 19 Jun 2024 09:21:29 +0300 Subject: drm/i915/psr: Perform scanline indication check for Panel Replay as well MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Scanline indication needs to be checked and configure for both PSR2 and Panel Replay Selective Update. Move this check to intel_sel_update_config_valid. Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-10-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index ba6497622435..ea5a254aa942 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1429,12 +1429,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { - drm_dbg_kms(&dev_priv->drm, - "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n"); - return false; - } - if (!alpm_config_valid(intel_dp, crtc_state, false)) return false; @@ -1476,6 +1470,12 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp, if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state)) goto unsupported; + if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { + drm_dbg_kms(&dev_priv->drm, + "Selective update not enabled, SDP indication do not fit in hblank\n"); + goto unsupported; + } + if (crtc_state->has_panel_replay && (DISPLAY_VER(dev_priv) < 14 || !intel_dp->psr.sink_panel_replay_su_support)) goto unsupported; -- cgit v1.2.3 From 623ad75a014864d3551ca2aa83ce19458ef1299e Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Wed, 19 Jun 2024 09:21:30 +0300 Subject: drm/i915/psr: Check Early Transport for Panel Replay as well MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move Early Transport validity check to be performed for Panel Replay as well and use Early Transport for eDP Panel Replay always. v2:set crtc_state->enable_psr2_su_region_et directly (not in if block) Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-11-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index ea5a254aa942..d40715d4b5d5 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1443,9 +1443,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); - if (psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay)) - crtc_state->enable_psr2_su_region_et = true; - return true; } @@ -1492,6 +1489,9 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp, goto unsupported; } + crtc_state->enable_psr2_su_region_et = + psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay); + return true; unsupported: -- cgit v1.2.3 From 85582ad0bc44960def44c78674c0c9b8dc007817 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Wed, 19 Jun 2024 09:21:31 +0300 Subject: drm/i915/psr: Modify dg2_activate_panel_replay to support eDP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are couple of bits in PSR2_CTL which needs to be written in case of eDP Panel Replay Bspec: 68920 v2: use boolean instead of assuming eDP Panel Replay mean Early Transport Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-12-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index d40715d4b5d5..9cb1cdaaeefa 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -951,6 +951,19 @@ static u8 frames_before_su_entry(struct intel_dp *intel_dp) static void dg2_activate_panel_replay(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct intel_psr *psr = &intel_dp->psr; + enum transcoder cpu_transcoder = intel_dp->psr.transcoder; + + if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) { + u32 val = psr->su_region_et_enabled ? + LNL_EDP_PSR2_SU_REGION_ET_ENABLE : 0; + + if (intel_dp->psr.req_psr2_sdp_prior_scanline) + val |= EDP_PSR2_SU_SDP_SCANLINE; + + intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder), + val); + } intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(dev_priv, intel_dp->psr.transcoder), -- cgit v1.2.3 From aaf9dc86bd806458f848c39057d59e5aa652a399 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 25 Jun 2024 14:18:40 +0300 Subject: drm/i915/display: For MTL+ platforms skip mg dp programming For MTL+ platforms we use PICA chips for Type-C support and hence mg programming is not needed. Fixes issue with drm warn of TC port not being in legacy mode. Cc: stable@vger.kernel.org Signed-off-by: Mika Kahola Signed-off-by: Imre Deak Reviewed-by: Gustavo Sousa Link: https://patchwork.freedesktop.org/patch/msgid/20240625111840.597574-1-mika.kahola@intel.com --- drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index bb13a3ca8c7c..6672fc162c4f 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2096,6 +2096,9 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port, u32 ln0, ln1, pin_assignment; u8 width; + if (DISPLAY_VER(dev_priv) >= 14) + return; + if (!intel_encoder_is_tc(&dig_port->base) || intel_tc_port_in_tbt_alt_mode(dig_port)) return; -- cgit v1.2.3 From a9422ec92a6388c8a19fad759f7ed0d533734cc6 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 11 Jun 2024 16:33:44 +0300 Subject: drm/i915/dsb: Try to document that DSB_STATUS bit 16 is level triggered MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DSB_STATUS bit 16 is supposed to be a sticky bit informing us whether the DSB was idle or not when the pipe's delayed vblank (when double buffered registers latch) occurred. Unfortunately it turns out this is a level triggred signal, ie. the bit will be set whenever the DSB is busy during the scanline window between start of delayed vblank and vtotal. Try to document that fact by renaming the bit. Sadly this also thwarts my plan to use this bit to sanity check that the (to be introduced) DSB based vblank evasion did its job correctly. That would require an edge triggered signal instead. So looks like we'll have to rely mostly on luck instead :( Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240611133344.30673-12-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dsb_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_dsb_regs.h b/drivers/gpu/drm/i915/display/intel_dsb_regs.h index 9c2664ff519a..cb6e0e5624a6 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dsb_regs.h @@ -45,7 +45,7 @@ #define DSB_TLBTRANS_SM_STATE_MASK REG_GENMASK(21, 20) #define DSB_SAFE_WINDOW REG_BIT(19) #define DSB_POINTERS_SM_STATE_MASK REG_GENMASK(18, 17) -#define DSB_BUSY_ON_DELAYED_VBLANK REG_BIT(16) +#define DSB_BUSY_DURING_DELAYED_VBLANK REG_BIT(16) #define DSB_MMIO_ARB_SM_STATE_MASK REG_GENMASK(15, 13) #define DSB_MMIO_INST_SM_STATE_MASK REG_GENMASK(11, 7) #define DSB_RESET_SM_STATE_MASK REG_GENMASK(5, 4) -- cgit v1.2.3 From 32a120f52a4c0121bca8f2328d4680d283693d60 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Wed, 26 Jun 2024 20:08:13 +0300 Subject: drm/i915/mtl: Skip PLL state verification in TBT mode In TBT-alt mode the driver doesn't program the PHY's PLL, which is handled instead by Thunderbolt driver/FW components, hence the PLL's HW vs. SW state verification should be skipped. During HW readout set a flag in the PLL state if the port was at the moment in TBT-alt mode and skip the verification of PLL parameters in this case. Fixes: 45fe957ae769 ("drm/i915/display: Add compare config for MTL+ platforms") Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11258 Cc: Mika Kahola Reviewed-by: Mika Kahola Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240626170813.806470-1-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 ++++++++--- drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++----- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + 3 files changed, 12 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 41f684c970dc..4a6c3040ca15 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -3279,6 +3279,10 @@ void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder, { pll_state->use_c10 = false; + pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)); + if (pll_state->tbt_mode) + return; + if (intel_encoder_is_c10phy(encoder)) { intel_c10pll_readout_hw_state(encoder, &pll_state->c10); pll_state->use_c10 = true; @@ -3325,6 +3329,8 @@ static bool mtl_compare_hw_state_c20(const struct intel_c20pll_state *a, bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a, const struct intel_cx0pll_state *b) { + if (a->tbt_mode || b->tbt_mode) + return true; if (a->use_c10 != b->use_c10) return false; @@ -3420,12 +3426,11 @@ void intel_cx0pll_state_verify(struct intel_atomic_state *state, return; encoder = intel_get_crtc_new_encoder(state, new_crtc_state); + intel_cx0pll_readout_hw_state(encoder, &mpll_hw_state); - if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) + if (mpll_hw_state.tbt_mode) return; - intel_cx0pll_readout_hw_state(encoder, &mpll_hw_state); - if (intel_encoder_is_c10phy(encoder)) intel_c10pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c10); else diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 6672fc162c4f..a07aca96e551 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4027,14 +4027,12 @@ void intel_ddi_get_clock(struct intel_encoder *encoder, static void mtl_ddi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { - struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); - if (intel_tc_port_in_tbt_alt_mode(dig_port)) { + if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); - } else { - intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); + else crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); - } intel_ddi_get_config(encoder, crtc_state); } diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index 36baed75b89a..6af325b8e27d 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -265,6 +265,7 @@ struct intel_cx0pll_state { }; bool ssc_enabled; bool use_c10; + bool tbt_mode; }; struct intel_dpll_hw_state { -- cgit v1.2.3