From 263ac3908516abb0392747bbf595af2b13df5fa2 Mon Sep 17 00:00:00 2001 From: Zong Li Date: Wed, 9 Dec 2020 17:49:15 +0800 Subject: clk: sifive: Fix the wrong bit field shift The clk enable bit should be 31 instead of 24. Signed-off-by: Zong Li Reported-by: Pragnesh Patel Link: https://lore.kernel.org/r/20201209094916.17383-5-zong.li@sifive.com Signed-off-by: Stephen Boyd --- drivers/clk/sifive/sifive-prci.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h index 7e509dfb72d1..88493f3b9edf 100644 --- a/drivers/clk/sifive/sifive-prci.h +++ b/drivers/clk/sifive/sifive-prci.h @@ -59,7 +59,7 @@ /* DDRPLLCFG1 */ #define PRCI_DDRPLLCFG1_OFFSET 0x10 -#define PRCI_DDRPLLCFG1_CKE_SHIFT 24 +#define PRCI_DDRPLLCFG1_CKE_SHIFT 31 #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) /* GEMGXLPLLCFG0 */ @@ -81,7 +81,7 @@ /* GEMGXLPLLCFG1 */ #define PRCI_GEMGXLPLLCFG1_OFFSET 0x20 -#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24 +#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31 #define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT) /* CORECLKSEL */ -- cgit v1.2.3