From 499e364cd2508c2115ac251f42bb47c9548cf358 Mon Sep 17 00:00:00 2001 From: Tam Nguyen Date: Tue, 29 Nov 2022 18:03:04 +0100 Subject: soc: renesas: r8a779g0-sysc: Add missing A3DUL power domain Add the power domain structure for the A3DUL domain (PAP-Subsystem), as described in the R-Car V4H Series Hardware User's Manual Rev. 0.51 and later. Signed-off-by: Tam Nguyen [geert: Manual reference] Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/14bd8a8de16ced703ff824f6a241e89d1ead6b07.1669740926.git.geert+renesas@glider.be --- drivers/soc/renesas/r8a779g0-sysc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/renesas/r8a779g0-sysc.c b/drivers/soc/renesas/r8a779g0-sysc.c index a452709f066d..b932eba1b804 100644 --- a/drivers/soc/renesas/r8a779g0-sysc.c +++ b/drivers/soc/renesas/r8a779g0-sysc.c @@ -37,6 +37,7 @@ static struct rcar_gen4_sysc_area r8a779g0_areas[] __initdata = { { "a3vip0", R8A779G0_PD_A3VIP0, R8A779G0_PD_ALWAYS_ON }, { "a3vip1", R8A779G0_PD_A3VIP1, R8A779G0_PD_ALWAYS_ON }, { "a3vip2", R8A779G0_PD_A3VIP2, R8A779G0_PD_ALWAYS_ON }, + { "a3dul", R8A779G0_PD_A3DUL, R8A779G0_PD_ALWAYS_ON }, { "a3isp0", R8A779G0_PD_A3ISP0, R8A779G0_PD_ALWAYS_ON }, { "a3isp1", R8A779G0_PD_A3ISP1, R8A779G0_PD_ALWAYS_ON }, { "a3ir", R8A779G0_PD_A3IR, R8A779G0_PD_ALWAYS_ON }, -- cgit v1.2.3 From 6635e91648ce0868481fd6dd591d5ac796d8a635 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Tue, 20 Dec 2022 09:12:45 +0800 Subject: soc: sifive: ccache: Add StarFive JH7110 support This adds support for the StarFive JH7110 SoC which also features this SiFive cache controller. Signed-off-by: Emil Renner Berthing Signed-off-by: Hal Feng Signed-off-by: Conor Dooley --- drivers/soc/Makefile | 2 +- drivers/soc/sifive/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index fff513bd522d..129135b3b90d 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -27,7 +27,7 @@ obj-y += qcom/ obj-y += renesas/ obj-y += rockchip/ obj-$(CONFIG_SOC_SAMSUNG) += samsung/ -obj-$(CONFIG_SOC_SIFIVE) += sifive/ +obj-y += sifive/ obj-y += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig index ed4c571f8771..e86870be34c9 100644 --- a/drivers/soc/sifive/Kconfig +++ b/drivers/soc/sifive/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 -if SOC_SIFIVE +if SOC_SIFIVE || SOC_STARFIVE config SIFIVE_CCACHE bool "Sifive Composable Cache controller" -- cgit v1.2.3 From a723c95fa137f7a1e86dc77a150ef6e2affe977d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 17 Nov 2022 14:29:56 +0100 Subject: soc: qcom: Add Qualcomm Ramp Controller driver The Ramp Controller is used to program the sequence ID for pulse swallowing, enable sequence and linking sequence IDs for the CPU cores on some Qualcomm SoCs. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221117132956.169432-3-angelogioacchino.delregno@collabora.com --- drivers/soc/qcom/Kconfig | 9 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/ramp_controller.c | 342 +++++++++++++++++++++++++++++++++++++ 3 files changed, 352 insertions(+) create mode 100644 drivers/soc/qcom/ramp_controller.c (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index ae504c43d9e7..df46108e58ce 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -96,6 +96,15 @@ config QCOM_QMI_HELPERS tristate depends on NET +config QCOM_RAMP_CTRL + tristate "Qualcomm Ramp Controller driver" + depends on ARCH_QCOM || COMPILE_TEST + help + The Ramp Controller is used to program the sequence ID for pulse + swallowing, enable sequence and link sequence IDs for the CPU + cores on some Qualcomm SoCs. + Say y here to enable support for the ramp controller. + config QCOM_RMTFS_MEM tristate "Qualcomm Remote Filesystem memory driver" depends on ARCH_QCOM diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index d66604aff2b0..6e02333c4080 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_QCOM_OCMEM) += ocmem.o obj-$(CONFIG_QCOM_PDR_HELPERS) += pdr_interface.o obj-$(CONFIG_QCOM_QMI_HELPERS) += qmi_helpers.o qmi_helpers-y += qmi_encdec.o qmi_interface.o +obj-$(CONFIG_QCOM_RAMP_CTRL) += ramp_controller.o obj-$(CONFIG_QCOM_RMTFS_MEM) += rmtfs_mem.o obj-$(CONFIG_QCOM_RPMH) += qcom_rpmh.o qcom_rpmh-y += rpmh-rsc.o diff --git a/drivers/soc/qcom/ramp_controller.c b/drivers/soc/qcom/ramp_controller.c new file mode 100644 index 000000000000..8f8c514b7288 --- /dev/null +++ b/drivers/soc/qcom/ramp_controller.c @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm Ramp Controller driver + * Copyright (c) 2022, AngeloGioacchino Del Regno + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#define RC_UPDATE_EN BIT(0) +#define RC_ROOT_EN BIT(1) + +#define RC_REG_CFG_UPDATE 0x60 +#define RC_CFG_UPDATE_EN BIT(8) +#define RC_CFG_ACK GENMASK(31, 16) + +#define RC_DCVS_CFG_SID 2 +#define RC_LINK_SID 3 +#define RC_LMH_SID 6 +#define RC_DFS_SID 14 + +#define RC_UPDATE_TIMEOUT_US 500 + +/** + * struct qcom_ramp_controller_desc - SoC specific parameters + * @cfg_dfs_sid: Dynamic Frequency Scaling SID configuration + * @cfg_link_sid: Link SID configuration + * @cfg_lmh_sid: Limits Management hardware SID configuration + * @cfg_ramp_en: Ramp Controller enable sequence + * @cfg_ramp_dis: Ramp Controller disable sequence + * @cmd_reg: Command register offset + * @num_dfs_sids: Number of DFS SIDs (max 8) + * @num_link_sids: Number of Link SIDs (max 3) + * @num_lmh_sids: Number of LMh SIDs (max 8) + * @num_ramp_en: Number of entries in enable sequence + * @num_ramp_dis: Number of entries in disable sequence + */ +struct qcom_ramp_controller_desc { + const struct reg_sequence *cfg_dfs_sid; + const struct reg_sequence *cfg_link_sid; + const struct reg_sequence *cfg_lmh_sid; + const struct reg_sequence *cfg_ramp_en; + const struct reg_sequence *cfg_ramp_dis; + u8 cmd_reg; + u8 num_dfs_sids; + u8 num_link_sids; + u8 num_lmh_sids; + u8 num_ramp_en; + u8 num_ramp_dis; +}; + +/** + * struct qcom_ramp_controller - Main driver structure + * @regmap: Regmap handle + * @desc: SoC specific parameters + */ +struct qcom_ramp_controller { + struct regmap *regmap; + const struct qcom_ramp_controller_desc *desc; +}; + +/** + * rc_wait_for_update() - Wait for Ramp Controller root update + * @qrc: Main driver structure + * + * Return: Zero for success or negative number for failure + */ +static int rc_wait_for_update(struct qcom_ramp_controller *qrc) +{ + const struct qcom_ramp_controller_desc *d = qrc->desc; + struct regmap *r = qrc->regmap; + u32 val; + int ret; + + ret = regmap_set_bits(r, d->cmd_reg, RC_ROOT_EN); + if (ret) + return ret; + + return regmap_read_poll_timeout(r, d->cmd_reg, val, !(val & RC_UPDATE_EN), + 1, RC_UPDATE_TIMEOUT_US); +} + +/** + * rc_set_cfg_update() - Ramp Controller configuration update + * @qrc: Main driver structure + * @ce: Configuration entry to update + * + * Return: Zero for success or negative number for failure + */ +static int rc_set_cfg_update(struct qcom_ramp_controller *qrc, u8 ce) +{ + const struct qcom_ramp_controller_desc *d = qrc->desc; + struct regmap *r = qrc->regmap; + u32 ack, val; + int ret; + + /* The ack bit is between bits 16-31 of RC_REG_CFG_UPDATE */ + ack = FIELD_PREP(RC_CFG_ACK, BIT(ce)); + + /* Write the configuration type first... */ + ret = regmap_set_bits(r, d->cmd_reg + RC_REG_CFG_UPDATE, ce); + if (ret) + return ret; + + /* ...and after that, enable the update bit to sync the changes */ + ret = regmap_set_bits(r, d->cmd_reg + RC_REG_CFG_UPDATE, RC_CFG_UPDATE_EN); + if (ret) + return ret; + + /* Wait for the changes to go through */ + ret = regmap_read_poll_timeout(r, d->cmd_reg + RC_REG_CFG_UPDATE, val, + val & ack, 1, RC_UPDATE_TIMEOUT_US); + if (ret) + return ret; + + /* + * Configuration update success! The CFG_UPDATE register will not be + * cleared automatically upon applying the configuration, so we have + * to do that manually in order to leave the ramp controller in a + * predictable and clean state. + */ + ret = regmap_write(r, d->cmd_reg + RC_REG_CFG_UPDATE, 0); + if (ret) + return ret; + + /* Wait for the update bit cleared ack */ + return regmap_read_poll_timeout(r, d->cmd_reg + RC_REG_CFG_UPDATE, + val, !(val & RC_CFG_ACK), 1, + RC_UPDATE_TIMEOUT_US); +} + +/** + * rc_write_cfg - Send configuration sequence + * @qrc: Main driver structure + * @seq: Register sequence to send before asking for update + * @ce: Configuration SID + * @nsids: Total number of SIDs + * + * Returns: Zero for success or negative number for error + */ +static int rc_write_cfg(struct qcom_ramp_controller *qrc, + const struct reg_sequence *seq, + u16 ce, u8 nsids) +{ + int ret; + u8 i; + + /* Check if, and wait until the ramp controller is ready */ + ret = rc_wait_for_update(qrc); + if (ret) + return ret; + + /* Write the sequence */ + ret = regmap_multi_reg_write(qrc->regmap, seq, nsids); + if (ret) + return ret; + + /* Pull the trigger: do config update starting from the last sid */ + for (i = 0; i < nsids; i++) { + ret = rc_set_cfg_update(qrc, (u8)ce - i); + if (ret) + return ret; + } + + return 0; +} + +/** + * rc_ramp_ctrl_enable() - Enable Ramp up/down Control + * @qrc: Main driver structure + * + * Return: Zero for success or negative number for error + */ +static int rc_ramp_ctrl_enable(struct qcom_ramp_controller *qrc) +{ + const struct qcom_ramp_controller_desc *d = qrc->desc; + int i, ret; + + for (i = 0; i < d->num_ramp_en; i++) { + ret = rc_write_cfg(qrc, &d->cfg_ramp_en[i], RC_DCVS_CFG_SID, 1); + if (ret) + return ret; + } + + return 0; +} + +/** + * qcom_ramp_controller_start() - Initialize and start the ramp controller + * @qrc: Main driver structure + * + * The Ramp Controller needs to be initialized by programming the relevant + * registers with SoC-specific configuration: once programming is done, + * the hardware will take care of the rest (no further handling required). + * + * Return: Zero for success or negative number for error + */ +static int qcom_ramp_controller_start(struct qcom_ramp_controller *qrc) +{ + const struct qcom_ramp_controller_desc *d = qrc->desc; + int ret; + + /* Program LMH, DFS, Link SIDs */ + ret = rc_write_cfg(qrc, d->cfg_lmh_sid, RC_LMH_SID, d->num_lmh_sids); + if (ret) + return ret; + + ret = rc_write_cfg(qrc, d->cfg_dfs_sid, RC_DFS_SID, d->num_dfs_sids); + if (ret) + return ret; + + ret = rc_write_cfg(qrc, d->cfg_link_sid, RC_LINK_SID, d->num_link_sids); + if (ret) + return ret; + + /* Everything is ready! Enable the ramp up/down control */ + return rc_ramp_ctrl_enable(qrc); +} + +static const struct regmap_config qrc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x68, + .fast_io = true, +}; + +const struct reg_sequence msm8976_cfg_dfs_sid[] = { + { 0x10, 0xfefebff7 }, + { 0x14, 0xfdff7fef }, + { 0x18, 0xfbffdefb }, + { 0x1c, 0xb69b5555 }, + { 0x20, 0x24929249 }, + { 0x24, 0x49241112 }, + { 0x28, 0x11112111 }, + { 0x2c, 0x8102 } +}; + +const struct reg_sequence msm8976_cfg_link_sid[] = { + { 0x40, 0xfc987 } +}; + +const struct reg_sequence msm8976_cfg_lmh_sid[] = { + { 0x30, 0x77706db }, + { 0x34, 0x5550249 }, + { 0x38, 0x111 } +}; + +const struct reg_sequence msm8976_cfg_ramp_en[] = { + { 0x50, 0x800 }, /* pre_en */ + { 0x50, 0xc00 }, /* en */ + { 0x50, 0x400 } /* post_en */ +}; + +const struct reg_sequence msm8976_cfg_ramp_dis[] = { + { 0x50, 0x0 } +}; + +static const struct qcom_ramp_controller_desc msm8976_rc_cfg = { + .cfg_dfs_sid = msm8976_cfg_dfs_sid, + .num_dfs_sids = ARRAY_SIZE(msm8976_cfg_dfs_sid), + + .cfg_link_sid = msm8976_cfg_link_sid, + .num_link_sids = ARRAY_SIZE(msm8976_cfg_link_sid), + + .cfg_lmh_sid = msm8976_cfg_lmh_sid, + .num_lmh_sids = ARRAY_SIZE(msm8976_cfg_lmh_sid), + + .cfg_ramp_en = msm8976_cfg_ramp_en, + .num_ramp_en = ARRAY_SIZE(msm8976_cfg_ramp_en), + + .cfg_ramp_dis = msm8976_cfg_ramp_dis, + .num_ramp_dis = ARRAY_SIZE(msm8976_cfg_ramp_dis), + + .cmd_reg = 0x0, +}; + +static int qcom_ramp_controller_probe(struct platform_device *pdev) +{ + struct qcom_ramp_controller *qrc; + void __iomem *base; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + qrc = devm_kmalloc(&pdev->dev, sizeof(*qrc), GFP_KERNEL); + if (!qrc) + return -ENOMEM; + + qrc->desc = device_get_match_data(&pdev->dev); + if (!qrc) + return -EINVAL; + + qrc->regmap = devm_regmap_init_mmio(&pdev->dev, base, &qrc_regmap_config); + if (IS_ERR(qrc->regmap)) + return PTR_ERR(qrc->regmap); + + platform_set_drvdata(pdev, qrc); + + return qcom_ramp_controller_start(qrc); +} + +static int qcom_ramp_controller_remove(struct platform_device *pdev) +{ + struct qcom_ramp_controller *qrc = platform_get_drvdata(pdev); + + return rc_write_cfg(qrc, qrc->desc->cfg_ramp_dis, + RC_DCVS_CFG_SID, qrc->desc->num_ramp_dis); +} + +static const struct of_device_id qcom_ramp_controller_match_table[] = { + { .compatible = "qcom,msm8976-ramp-controller", .data = &msm8976_rc_cfg }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, qcom_ramp_controller_match_table); + +static struct platform_driver qcom_ramp_controller_driver = { + .driver = { + .name = "qcom-ramp-controller", + .of_match_table = qcom_ramp_controller_match_table, + .suppress_bind_attrs = true, + }, + .probe = qcom_ramp_controller_probe, + .remove = qcom_ramp_controller_remove, +}; + +static int __init qcom_ramp_controller_init(void) +{ + return platform_driver_register(&qcom_ramp_controller_driver); +} +arch_initcall(qcom_ramp_controller_init); + +MODULE_AUTHOR("AngeloGioacchino Del Regno "); +MODULE_DESCRIPTION("Qualcomm Ramp Controller driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 4cbe60cf5ad622f7f45ccc4fa369c9f7a71903b9 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Tue, 27 Dec 2022 20:52:46 +0530 Subject: soc: qcom: dcc: Add driver support for Data Capture and Compare unit(DCC) The DCC is a DMA Engine designed to capture and store data during system crash or software triggers. The DCC operates based on user inputs via the debugfs interface. The user gives addresses as inputs and these addresses are stored in the dcc sram. In case of a system crash or a manual software trigger by the user through the debugfs interface, the dcc captures and stores the values at these addresses. This patch contains the driver which has all the methods pertaining to the debugfs interface, auxiliary functions to support all the four fundamental operations of dcc namely read, write, read/modify/write and loop. The probe method here instantiates all the resources necessary for dcc to operate mainly the dedicated dcc sram where it stores the values. The DCC driver can be used for debugging purposes without going for a reboot since it can perform software triggers as well based on user inputs. Also add the documentation for debugfs entries which explains the functionalities of each debugfs file that has been created for dcc. The following is the justification of using debugfs interface over the other alternatives like sysfs/ioctls i) As can be seen from the debugfs attribute descriptions, some of the debugfs attribute files here contains multiple arguments which needs to be accepted from the user. This goes against the design style of sysfs. ii) The user input patterns have been made simple and convenient in this case with the use of debugfs interface as user doesn't need to shuffle between different files to execute one instruction as was the case on using other alternatives. Signed-off-by: Souradeep Chowdhury Reviewed-by: Alex Elder [bjorn: Fixed up a few indents and line wraps] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/644b4f66a358492a8a6738454035c3b120092fe7.1672148732.git.quic_schowdhu@quicinc.com --- Documentation/ABI/testing/debugfs-driver-dcc | 98 ++ drivers/soc/qcom/Kconfig | 8 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/dcc.c | 1299 ++++++++++++++++++++++++++ 4 files changed, 1406 insertions(+) create mode 100644 Documentation/ABI/testing/debugfs-driver-dcc create mode 100644 drivers/soc/qcom/dcc.c (limited to 'drivers/soc') diff --git a/Documentation/ABI/testing/debugfs-driver-dcc b/Documentation/ABI/testing/debugfs-driver-dcc new file mode 100644 index 000000000000..a46809502059 --- /dev/null +++ b/Documentation/ABI/testing/debugfs-driver-dcc @@ -0,0 +1,98 @@ +What: /sys/kernel/debug/dcc/.../ready +Date: December 2022 +Contact: Souradeep Chowdhury +Description: + This file is used to check the status of the dcc + hardware if it's ready to take the inputs. A 'Y' + here indicates dcc is in a ready condition. + Example: + cat /sys/kernel/debug/dcc/.../ready + +What: /sys/kernel/debug/dcc/.../trigger +Date: December 2022 +Contact: Souradeep Chowdhury +Description: + This is the debugfs interface for manual software + triggers. The user can simply enter a 1 against + the debugfs file and enable a manual trigger. + Example: + echo 1 > /sys/kernel/debug/dcc/.../trigger + +What: /sys/kernel/debug/dcc/.../config_reset +Date: December 2022 +Contact: Souradeep Chowdhury +Description: + This file is used to reset the configuration of + a dcc driver to the default configuration. This + means that all the previous addresses stored in + the driver gets removed and user needs to enter + the address values from the start. + Example: + echo 1 > /sys/kernel/debug/dcc/../config_reset + +What: /sys/kernel/debug/dcc/.../[list-number]/config +Date: December 2022 +Contact: Souradeep Chowdhury +Description: + This stores the addresses of the registers which + should be read in case of a hardware crash or + manual software triggers. The addresses entered here + are considered under all the 4 types of dcc + instructions Read type, Write type, Read Modify Write + type and Loop type. The lists need to be configured + sequentially and not in a overlapping manner. As an + example user can jump to list x only after list y is + configured and enabled. The format for entering all + types of instructions are explained in examples as + follows. + Example: + i)Read Type Instruction + echo R <1> <2> <3> >/sys/kernel/debug/dcc/../[list-number]/config + 1->Address to be considered for reading the value. + 2->The word count of the addresses, read n words + starting from address <1>. Each word is of 32 bits. + If not entered 1 is considered. + 3->Can be 'apb' or 'ahb' which indicates if it is apb or ahb + bus respectively. If not entered ahb is considered. + ii)Write Type Instruction + echo W <1> <2> <3> > /sys/kernel/debug/dcc/../[list-number]/config + 1->Address to be considered for writing the value. + 2->The value that needs to be written at the location. + 3->Can be a 'apb' or 'ahb' which indicates if it is apb or ahb + but respectively. + iii)Read Modify Write type instruction + echo RW <1> <2> <3> > /sys/kernel/debug/dcc/../[list-number]/config + 1->The address which needs to be considered for read then write. + 2->The value that needs to be written on the address. + 3->The mask of the value to be written. + iv)Loop Type Instruction + echo L <1> <2> <3> > /sys/kernel/debug/dcc/../[list-number]/config + 1->The loop count, the number of times the value of the addresses will be + captured. + 2->The address count, total number of addresses to be entered in this + instruction. + 3->The series of addresses to be entered separated by a space like + ... and so on. + +What: /sys/kernel/debug/dcc/.../[list-number]/enable +Date: December 2022 +Contact: Souradeep Chowdhury +Description: + This debugfs interface is used for enabling the + the dcc hardware. Enable file is kept under the + directory list number for which the user wants + to enable it. For example if the user wants to + enable list 1, then he should go for + echo 1 > /sys/kernel/debug/dcc/.../1/enable. + On enabling the dcc, all the addresses entered + by the user for the corresponding list is written + into dcc sram which is read by the dcc hardware + on manual or crash induced triggers. Lists should + be enabled sequentially.For example after configuring + addresses for list 1 and enabling it, a user can + proceed to enable list 2 or vice versa. + Example: + echo 0 > /sys/kernel/debug/dcc/.../[list-number]/enable + (disable dcc for the corresponding list number) + echo 1 > /sys/kernel/debug/dcc/.../[list-number]/enable + (enable dcc for the corresponding list number) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index df46108e58ce..21c4ce2315ba 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -70,6 +70,14 @@ config QCOM_LLCC SDM845. This provides interfaces to clients that use the LLCC. Say yes here to enable LLCC slice driver. +config QCOM_DCC + tristate "Qualcomm Technologies, Inc. Data Capture and Compare(DCC) engine driver" + depends on ARCH_QCOM || COMPILE_TEST + help + This option enables driver for Data Capture and Compare engine. DCC + driver provides interface to configure DCC block and read back + captured data from DCC's internal SRAM. + config QCOM_KRYO_L2_ACCESSORS bool depends on ARCH_QCOM && ARM64 || COMPILE_TEST diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 6e02333c4080..3b92c6c8e0ec 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_QCOM_AOSS_QMP) += qcom_aoss.o obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o obj-$(CONFIG_QCOM_CPR) += cpr.o +obj-$(CONFIG_QCOM_DCC) += dcc.o obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o obj-$(CONFIG_QCOM_OCMEM) += ocmem.o diff --git a/drivers/soc/qcom/dcc.c b/drivers/soc/qcom/dcc.c new file mode 100644 index 000000000000..d4101f79cb5d --- /dev/null +++ b/drivers/soc/qcom/dcc.c @@ -0,0 +1,1299 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define STATUS_READY_TIMEOUT 5000 /* microseconds */ + +#define DCC_SRAM_NODE "dcc_sram" + +/* DCC registers */ +#define DCC_HW_INFO 0x04 +#define DCC_LL_NUM_INFO 0x10 +#define DCC_STATUS(vers) ((vers) == 1 ? 0x0c : 0x1c) +#define DCC_LL_LOCK 0x00 +#define DCC_LL_CFG 0x04 +#define DCC_LL_BASE 0x08 +#define DCC_FD_BASE 0x0c +#define DCC_LL_TIMEOUT 0x10 +#define DCC_LL_INT_ENABLE 0x18 +#define DCC_LL_INT_STATUS 0x1c +#define DCC_LL_SW_TRIGGER 0x2c +#define DCC_LL_BUS_ACCESS_STATUS 0x30 + +/* Default value used if a bit 6 in the HW_INFO register is set. */ +#define DCC_FIX_LOOP_OFFSET 16 + +/* Mask to find version info from HW_Info register */ +#define DCC_VER_INFO_MASK BIT(9) + +#define MAX_DCC_OFFSET GENMASK(9, 2) +#define MAX_DCC_LEN GENMASK(6, 0) +#define MAX_LOOP_CNT GENMASK(7, 0) +#define MAX_LOOP_ADDR 10 + +#define DCC_ADDR_DESCRIPTOR 0x00 +#define DCC_ADDR_LIMIT 27 +#define DCC_WORD_SIZE sizeof(u32) +#define DCC_ADDR_RANGE_MASK GENMASK(31, 4) +#define DCC_LOOP_DESCRIPTOR BIT(30) +#define DCC_RD_MOD_WR_DESCRIPTOR BIT(31) +#define DCC_LINK_DESCRIPTOR GENMASK(31, 30) +#define DCC_STATUS_MASK GENMASK(1, 0) +#define DCC_LOCK_MASK BIT(0) +#define DCC_LOOP_OFFSET_MASK BIT(6) +#define DCC_TRIGGER_MASK BIT(9) + +#define DCC_WRITE_MASK BIT(15) +#define DCC_WRITE_OFF_MASK GENMASK(7, 0) +#define DCC_WRITE_LEN_MASK GENMASK(14, 8) + +#define DCC_READ_IND 0x00 +#define DCC_WRITE_IND (BIT(28)) + +#define DCC_AHB_IND 0x00 +#define DCC_APB_IND BIT(29) + +#define DCC_MAX_LINK_LIST 8 + +#define DCC_VER_MASK2 GENMASK(5, 0) + +#define DCC_SRAM_WORD_LENGTH 4 + +#define DCC_RD_MOD_WR_ADDR 0xc105e + +enum dcc_descriptor_type { + DCC_READ_TYPE, + DCC_LOOP_TYPE, + DCC_READ_WRITE_TYPE, + DCC_WRITE_TYPE +}; + +struct dcc_config_entry { + u32 base; + u32 offset; + u32 len; + u32 loop_cnt; + u32 write_val; + u32 mask; + bool apb_bus; + enum dcc_descriptor_type desc_type; + struct list_head list; +}; + +/** + * struct dcc_drvdata - configuration information related to a dcc device + * @base: Base Address of the dcc device + * @dev: The device attached to the driver data + * @mutex: Lock to protect access and manipulation of dcc_drvdata + * @ram_base: Base address for the SRAM dedicated for the dcc device + * @ram_size: Total size of the SRAM dedicated for the dcc device + * @ram_offset: Offset to the SRAM dedicated for dcc device + * @mem_map_ver: Memory map version of DCC hardware + * @ram_cfg: Used for address limit calculation for dcc + * @ram_start: Starting address of DCC SRAM + * @sram_dev: Miscellaneous device equivalent of dcc SRAM + * @cfg_head: Points to the head of the linked list of addresses + * @dbg_dir: The dcc debugfs directory under which all the debugfs files are placed + * @nr_link_list: Total number of linkedlists supported by the DCC configuration + * @loop_shift: Loop offset bits range for the addresses + * @enable_bitmap: Bitmap to capture the enabled status of each linked list of addresses + */ +struct dcc_drvdata { + void __iomem *base; + void __iomem *ram_base; + struct device *dev; + struct mutex mutex; + size_t ram_size; + size_t ram_offset; + int mem_map_ver; + unsigned int ram_cfg; + unsigned int ram_start; + struct miscdevice sram_dev; + struct list_head *cfg_head; + struct dentry *dbg_dir; + size_t nr_link_list; + u8 loop_shift; + unsigned long *enable_bitmap; +}; + +struct dcc_cfg_attr { + u32 addr; + u32 prev_addr; + u32 prev_off; + u32 link; + u32 sram_offset; +}; + +struct dcc_cfg_loop_attr { + u32 loop_cnt; + u32 loop_len; + u32 loop_off; + bool loop_start; +}; + +static inline u32 dcc_list_offset(int version) +{ + return version == 1 ? 0x1c : version == 2 ? 0x2c : 0x34; +} + +static inline void dcc_list_writel(struct dcc_drvdata *drvdata, + u32 ll, u32 val, u32 off) +{ + u32 offset = dcc_list_offset(drvdata->mem_map_ver) + off; + + writel(val, drvdata->base + ll * 0x80 + offset); +} + +static inline u32 dcc_list_readl(struct dcc_drvdata *drvdata, u32 ll, u32 off) +{ + u32 offset = dcc_list_offset(drvdata->mem_map_ver) + off; + + return readl(drvdata->base + ll * 0x80 + offset); +} + +static void dcc_sram_write_auto(struct dcc_drvdata *drvdata, + u32 val, u32 *off) +{ + /* If the overflow condition is met increment the offset + * and return to indicate that overflow has occurred + */ + if (unlikely(*off > drvdata->ram_size - 4)) { + *off += 4; + return; + } + + writel(val, drvdata->ram_base + *off); + + *off += 4; +} + +static int dcc_sw_trigger(struct dcc_drvdata *drvdata) +{ + void __iomem *addr; + int ret = 0; + int i; + u32 status; + u32 ll_cfg; + u32 tmp_ll_cfg; + u32 val; + + mutex_lock(&drvdata->mutex); + + for (i = 0; i < drvdata->nr_link_list; i++) { + if (!test_bit(i, drvdata->enable_bitmap)) + continue; + ll_cfg = dcc_list_readl(drvdata, i, DCC_LL_CFG); + tmp_ll_cfg = ll_cfg & ~DCC_TRIGGER_MASK; + dcc_list_writel(drvdata, tmp_ll_cfg, i, DCC_LL_CFG); + dcc_list_writel(drvdata, 1, i, DCC_LL_SW_TRIGGER); + dcc_list_writel(drvdata, ll_cfg, i, DCC_LL_CFG); + } + + addr = drvdata->base + DCC_STATUS(drvdata->mem_map_ver); + if (readl_poll_timeout(addr, val, !FIELD_GET(DCC_STATUS_MASK, val), + 1, STATUS_READY_TIMEOUT)) { + dev_err(drvdata->dev, "DCC is busy after receiving sw trigger\n"); + ret = -EBUSY; + goto out_unlock; + } + + for (i = 0; i < drvdata->nr_link_list; i++) { + if (!test_bit(i, drvdata->enable_bitmap)) + continue; + + status = dcc_list_readl(drvdata, i, DCC_LL_BUS_ACCESS_STATUS); + if (!status) + continue; + + dev_err(drvdata->dev, "Read access error for list %d err: 0x%x\n", + i, status); + ll_cfg = dcc_list_readl(drvdata, i, DCC_LL_CFG); + tmp_ll_cfg = ll_cfg & ~DCC_TRIGGER_MASK; + dcc_list_writel(drvdata, tmp_ll_cfg, i, DCC_LL_CFG); + dcc_list_writel(drvdata, DCC_STATUS_MASK, i, DCC_LL_BUS_ACCESS_STATUS); + dcc_list_writel(drvdata, ll_cfg, i, DCC_LL_CFG); + ret = -ENODATA; + break; + } + +out_unlock: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static void dcc_ll_cfg_reset_link(struct dcc_cfg_attr *cfg) +{ + cfg->addr = 0x00; + cfg->link = 0; + cfg->prev_off = 0; + cfg->prev_addr = cfg->addr; +} + +static void dcc_emit_read_write(struct dcc_drvdata *drvdata, + struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg) +{ + if (cfg->link) { + /* + * write new offset = 1 to continue + * processing the list + */ + + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + + /* Reset link and prev_off */ + dcc_ll_cfg_reset_link(cfg); + } + + cfg->addr = DCC_RD_MOD_WR_DESCRIPTOR; + dcc_sram_write_auto(drvdata, cfg->addr, &cfg->sram_offset); + + dcc_sram_write_auto(drvdata, entry->mask, &cfg->sram_offset); + + dcc_sram_write_auto(drvdata, entry->write_val, &cfg->sram_offset); + + cfg->addr = 0; +} + +static void dcc_emit_loop(struct dcc_drvdata *drvdata, struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg, + struct dcc_cfg_loop_attr *cfg_loop, + u32 *total_len) +{ + int loop; + + /* Check if we need to write link of prev entry */ + if (cfg->link) + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + + if (cfg_loop->loop_start) { + loop = (cfg->sram_offset - cfg_loop->loop_off) / 4; + loop |= (cfg_loop->loop_cnt << drvdata->loop_shift) & + GENMASK(DCC_ADDR_LIMIT, drvdata->loop_shift); + loop |= DCC_LOOP_DESCRIPTOR; + *total_len += (*total_len - cfg_loop->loop_len) * cfg_loop->loop_cnt; + + dcc_sram_write_auto(drvdata, loop, &cfg->sram_offset); + + cfg_loop->loop_start = false; + cfg_loop->loop_len = 0; + cfg_loop->loop_off = 0; + } else { + cfg_loop->loop_start = true; + cfg_loop->loop_cnt = entry->loop_cnt - 1; + cfg_loop->loop_len = *total_len; + cfg_loop->loop_off = cfg->sram_offset; + } + + /* Reset link and prev_off */ + dcc_ll_cfg_reset_link(cfg); +} + +static void dcc_emit_write(struct dcc_drvdata *drvdata, + struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg) +{ + u32 off; + + if (cfg->link) { + /* + * write new offset = 1 to continue + * processing the list + */ + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + + /* Reset link and prev_off */ + cfg->addr = 0x00; + cfg->prev_off = 0; + cfg->prev_addr = cfg->addr; + } + + off = entry->offset / 4; + /* write new offset-length pair to correct position */ + cfg->link |= ((off & DCC_WRITE_OFF_MASK) | DCC_WRITE_MASK | + FIELD_PREP(DCC_WRITE_LEN_MASK, entry->len)); + cfg->link |= DCC_LINK_DESCRIPTOR; + + /* Address type */ + cfg->addr = (entry->base >> 4) & GENMASK(DCC_ADDR_LIMIT, 0); + if (entry->apb_bus) + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_APB_IND; + else + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_AHB_IND; + dcc_sram_write_auto(drvdata, cfg->addr, &cfg->sram_offset); + + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + + dcc_sram_write_auto(drvdata, entry->write_val, &cfg->sram_offset); + + cfg->addr = 0x00; + cfg->link = 0; +} + +static int dcc_emit_read(struct dcc_drvdata *drvdata, + struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg, + u32 *pos, u32 *total_len) +{ + u32 off; + u32 temp_off; + + cfg->addr = (entry->base >> 4) & GENMASK(27, 0); + + if (entry->apb_bus) + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_APB_IND; + else + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_AHB_IND; + + off = entry->offset / 4; + + *total_len += entry->len * 4; + + if (!cfg->prev_addr || cfg->prev_addr != cfg->addr || cfg->prev_off > off) { + /* Check if we need to write prev link entry */ + if (cfg->link) + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + dev_dbg(drvdata->dev, "DCC: sram address 0x%x\n", cfg->sram_offset); + + /* Write address */ + dcc_sram_write_auto(drvdata, cfg->addr, &cfg->sram_offset); + + /* Reset link and prev_off */ + cfg->link = 0; + cfg->prev_off = 0; + } + + if ((off - cfg->prev_off) > 0xff || entry->len > MAX_DCC_LEN) { + dev_err(drvdata->dev, "DCC: Programming error Base: 0x%x, offset 0x%x\n", + entry->base, entry->offset); + return -EINVAL; + } + + if (cfg->link) { + /* + * link already has one offset-length so new + * offset-length needs to be placed at + * bits [29:15] + */ + *pos = 15; + + /* Clear bits [31:16] */ + cfg->link &= GENMASK(14, 0); + } else { + /* + * link is empty, so new offset-length needs + * to be placed at bits [15:0] + */ + *pos = 0; + cfg->link = 1 << 15; + } + + /* write new offset-length pair to correct position */ + temp_off = (off - cfg->prev_off) & GENMASK(7, 0); + cfg->link |= temp_off | ((entry->len << 8) & GENMASK(14, 8)) << *pos; + + cfg->link |= DCC_LINK_DESCRIPTOR; + + if (*pos) { + dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); + cfg->link = 0; + } + + cfg->prev_off = off + entry->len - 1; + cfg->prev_addr = cfg->addr; + return 0; +} + +static int dcc_emit_config(struct dcc_drvdata *drvdata, unsigned int curr_list) +{ + int ret; + u32 total_len, pos; + struct dcc_config_entry *entry; + struct dcc_cfg_attr cfg; + struct dcc_cfg_loop_attr cfg_loop; + + memset(&cfg, 0, sizeof(cfg)); + memset(&cfg_loop, 0, sizeof(cfg_loop)); + cfg.sram_offset = drvdata->ram_cfg * 4; + total_len = 0; + + list_for_each_entry(entry, &drvdata->cfg_head[curr_list], list) { + switch (entry->desc_type) { + case DCC_READ_WRITE_TYPE: + dcc_emit_read_write(drvdata, entry, &cfg); + break; + + case DCC_LOOP_TYPE: + dcc_emit_loop(drvdata, entry, &cfg, &cfg_loop, &total_len); + break; + + case DCC_WRITE_TYPE: + dcc_emit_write(drvdata, entry, &cfg); + break; + + case DCC_READ_TYPE: + ret = dcc_emit_read(drvdata, entry, &cfg, &pos, &total_len); + if (ret) + goto err; + break; + } + } + + if (cfg.link) + dcc_sram_write_auto(drvdata, cfg.link, &cfg.sram_offset); + + if (cfg_loop.loop_start) { + dev_err(drvdata->dev, "DCC: Programming error: Loop unterminated\n"); + ret = -EINVAL; + goto err; + } + + /* Handling special case of list ending with a rd_mod_wr */ + if (cfg.addr == DCC_RD_MOD_WR_DESCRIPTOR) { + cfg.addr = (DCC_RD_MOD_WR_ADDR) & GENMASK(27, 0); + cfg.addr |= DCC_ADDR_DESCRIPTOR; + dcc_sram_write_auto(drvdata, cfg.addr, &cfg.sram_offset); + } + + /* Setting zero to indicate end of the list */ + cfg.link = DCC_LINK_DESCRIPTOR; + dcc_sram_write_auto(drvdata, cfg.link, &cfg.sram_offset); + + /* Check if sram offset exceeds the ram size */ + if (cfg.sram_offset > drvdata->ram_size) + goto overstep; + + /* Update ram_cfg and check if the data will overstep */ + drvdata->ram_cfg = (cfg.sram_offset + total_len) / 4; + + if (cfg.sram_offset + total_len > drvdata->ram_size) { + cfg.sram_offset += total_len; + goto overstep; + } + + drvdata->ram_start = cfg.sram_offset / 4; + return 0; +overstep: + ret = -EINVAL; + memset_io(drvdata->ram_base, 0, drvdata->ram_size); + +err: + return ret; +} + +static bool dcc_valid_list(struct dcc_drvdata *drvdata, unsigned int curr_list) +{ + u32 lock_reg; + + if (list_empty(&drvdata->cfg_head[curr_list])) + return false; + + if (test_bit(curr_list, drvdata->enable_bitmap)) { + dev_err(drvdata->dev, "List %d is already enabled\n", curr_list); + return false; + } + + lock_reg = dcc_list_readl(drvdata, curr_list, DCC_LL_LOCK); + if (lock_reg & DCC_LOCK_MASK) { + dev_err(drvdata->dev, "List %d is already locked\n", curr_list); + return false; + } + + return true; +} + +static bool is_dcc_enabled(struct dcc_drvdata *drvdata) +{ + int list; + + for (list = 0; list < drvdata->nr_link_list; list++) + if (test_bit(list, drvdata->enable_bitmap)) + return true; + + return false; +} + +static int dcc_enable(struct dcc_drvdata *drvdata, unsigned int curr_list) +{ + int ret; + u32 ram_cfg_base; + + mutex_lock(&drvdata->mutex); + + if (!dcc_valid_list(drvdata, curr_list)) { + ret = -EINVAL; + goto out_unlock; + } + + /* Fill dcc sram with the poison value. + * This helps in understanding bus + * hang from registers returning a zero + */ + if (!is_dcc_enabled(drvdata)) + memset_io(drvdata->ram_base, 0xde, drvdata->ram_size); + + /* 1. Take ownership of the list */ + dcc_list_writel(drvdata, DCC_LOCK_MASK, curr_list, DCC_LL_LOCK); + + /* 2. Program linked-list in the SRAM */ + ram_cfg_base = drvdata->ram_cfg; + ret = dcc_emit_config(drvdata, curr_list); + if (ret) { + dcc_list_writel(drvdata, 0, curr_list, DCC_LL_LOCK); + goto out_unlock; + } + + /* 3. Program DCC_RAM_CFG reg */ + dcc_list_writel(drvdata, ram_cfg_base + + drvdata->ram_offset / 4, curr_list, DCC_LL_BASE); + dcc_list_writel(drvdata, drvdata->ram_start + + drvdata->ram_offset / 4, curr_list, DCC_FD_BASE); + dcc_list_writel(drvdata, 0xFFF, curr_list, DCC_LL_TIMEOUT); + + /* 4. Clears interrupt status register */ + dcc_list_writel(drvdata, 0, curr_list, DCC_LL_INT_ENABLE); + dcc_list_writel(drvdata, (BIT(0) | BIT(1) | BIT(2)), + curr_list, DCC_LL_INT_STATUS); + + set_bit(curr_list, drvdata->enable_bitmap); + + /* 5. Configure trigger */ + dcc_list_writel(drvdata, DCC_TRIGGER_MASK, + curr_list, DCC_LL_CFG); + +out_unlock: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static void dcc_disable(struct dcc_drvdata *drvdata, int curr_list) +{ + mutex_lock(&drvdata->mutex); + + if (!test_bit(curr_list, drvdata->enable_bitmap)) + goto out_unlock; + dcc_list_writel(drvdata, 0, curr_list, DCC_LL_CFG); + dcc_list_writel(drvdata, 0, curr_list, DCC_LL_BASE); + dcc_list_writel(drvdata, 0, curr_list, DCC_FD_BASE); + dcc_list_writel(drvdata, 0, curr_list, DCC_LL_LOCK); + clear_bit(curr_list, drvdata->enable_bitmap); +out_unlock: + mutex_unlock(&drvdata->mutex); +} + +static u32 dcc_filp_curr_list(const struct file *filp) +{ + struct dentry *dentry = file_dentry(filp); + int curr_list, ret; + + ret = kstrtoint(dentry->d_parent->d_name.name, 0, &curr_list); + if (ret) + return ret; + + return curr_list; +} + +static ssize_t enable_read(struct file *filp, char __user *userbuf, + size_t count, loff_t *ppos) +{ + char *buf; + struct dcc_drvdata *drvdata = filp->private_data; + + mutex_lock(&drvdata->mutex); + + if (is_dcc_enabled(drvdata)) + buf = "Y\n"; + else + buf = "N\n"; + + mutex_unlock(&drvdata->mutex); + + return simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf)); +} + +static ssize_t enable_write(struct file *filp, const char __user *userbuf, + size_t count, loff_t *ppos) +{ + int ret = 0, curr_list; + bool val; + struct dcc_drvdata *drvdata = filp->private_data; + + curr_list = dcc_filp_curr_list(filp); + if (curr_list < 0) + return curr_list; + + ret = kstrtobool_from_user(userbuf, count, &val); + if (ret < 0) + return ret; + + if (val) { + ret = dcc_enable(drvdata, curr_list); + if (ret) + return ret; + } else { + dcc_disable(drvdata, curr_list); + } + + return count; +} + +static const struct file_operations enable_fops = { + .read = enable_read, + .write = enable_write, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +static ssize_t trigger_write(struct file *filp, + const char __user *user_buf, size_t count, + loff_t *ppos) +{ + int ret; + unsigned int val; + struct dcc_drvdata *drvdata = filp->private_data; + + ret = kstrtouint_from_user(user_buf, count, 0, &val); + if (ret < 0) + return ret; + + if (val != 1) + return -EINVAL; + + ret = dcc_sw_trigger(drvdata); + if (ret < 0) + return ret; + + return count; +} + +static const struct file_operations trigger_fops = { + .write = trigger_write, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +static int dcc_config_add(struct dcc_drvdata *drvdata, unsigned int addr, + unsigned int len, bool apb_bus, int curr_list) +{ + int ret = 0; + struct dcc_config_entry *entry, *pentry; + unsigned int base, offset; + + mutex_lock(&drvdata->mutex); + + if (!len || len > drvdata->ram_size / DCC_WORD_SIZE) { + dev_err(drvdata->dev, "DCC: Invalid length\n"); + ret = -EINVAL; + goto out_unlock; + } + + base = addr & DCC_ADDR_RANGE_MASK; + + if (!list_empty(&drvdata->cfg_head[curr_list])) { + pentry = list_last_entry(&drvdata->cfg_head[curr_list], + struct dcc_config_entry, list); + + if (pentry->desc_type == DCC_READ_TYPE && + addr >= (pentry->base + pentry->offset) && + addr <= (pentry->base + pentry->offset + MAX_DCC_OFFSET)) { + /* Re-use base address from last entry */ + base = pentry->base; + + if ((pentry->len * 4 + pentry->base + pentry->offset) + == addr) { + len += pentry->len; + + if (len > MAX_DCC_LEN) + pentry->len = MAX_DCC_LEN; + else + pentry->len = len; + + addr = pentry->base + pentry->offset + + pentry->len * 4; + len -= pentry->len; + } + } + } + + offset = addr - base; + + while (len) { + entry = kzalloc(sizeof(*entry), GFP_KERNEL); + if (!entry) { + ret = -ENOMEM; + goto out_unlock; + } + + entry->base = base; + entry->offset = offset; + entry->len = min_t(u32, len, MAX_DCC_LEN); + entry->desc_type = DCC_READ_TYPE; + entry->apb_bus = apb_bus; + INIT_LIST_HEAD(&entry->list); + list_add_tail(&entry->list, &drvdata->cfg_head[curr_list]); + + len -= entry->len; + offset += MAX_DCC_LEN * 4; + } + +out_unlock: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static ssize_t dcc_config_add_read(struct dcc_drvdata *drvdata, char *buf, int curr_list) +{ + bool bus; + int len, nval; + unsigned int base; + char apb_bus[4]; + + nval = sscanf(buf, "%x %i %3s", &base, &len, apb_bus); + if (nval <= 0 || nval > 3) + return -EINVAL; + + if (nval == 1) { + len = 1; + bus = false; + } else if (nval == 2) { + bus = false; + } else if (!strcmp("apb", apb_bus)) { + bus = true; + } else if (!strcmp("ahb", apb_bus)) { + bus = false; + } else { + return -EINVAL; + } + + return dcc_config_add(drvdata, base, len, bus, curr_list); +} + +static void dcc_config_reset(struct dcc_drvdata *drvdata) +{ + struct dcc_config_entry *entry, *temp; + int curr_list; + + mutex_lock(&drvdata->mutex); + + for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) { + list_for_each_entry_safe(entry, temp, + &drvdata->cfg_head[curr_list], list) { + list_del(&entry->list); + kfree(entry); + } + } + drvdata->ram_start = 0; + drvdata->ram_cfg = 0; + mutex_unlock(&drvdata->mutex); +} + +static ssize_t config_reset_write(struct file *filp, + const char __user *user_buf, size_t count, + loff_t *ppos) +{ + unsigned int val, ret; + struct dcc_drvdata *drvdata = filp->private_data; + + ret = kstrtouint_from_user(user_buf, count, 0, &val); + if (ret < 0) + return ret; + + if (val) + dcc_config_reset(drvdata); + + return count; +} + +static const struct file_operations config_reset_fops = { + .write = config_reset_write, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +static ssize_t ready_read(struct file *filp, char __user *userbuf, + size_t count, loff_t *ppos) +{ + int ret = 0; + char *buf; + struct dcc_drvdata *drvdata = filp->private_data; + + mutex_lock(&drvdata->mutex); + + if (!is_dcc_enabled(drvdata)) { + ret = -EINVAL; + goto out_unlock; + } + + if (!FIELD_GET(BIT(1), readl(drvdata->base + DCC_STATUS(drvdata->mem_map_ver)))) + buf = "Y\n"; + else + buf = "N\n"; +out_unlock: + mutex_unlock(&drvdata->mutex); + + if (ret < 0) + return -EINVAL; + else + return simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf) + 1); +} + +static const struct file_operations ready_fops = { + .read = ready_read, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +static int dcc_add_loop(struct dcc_drvdata *drvdata, unsigned long loop_cnt, int curr_list) +{ + struct dcc_config_entry *entry; + + entry = kzalloc(sizeof(*entry), GFP_KERNEL); + if (!entry) + return -ENOMEM; + + entry->loop_cnt = min_t(u32, loop_cnt, MAX_LOOP_CNT); + entry->desc_type = DCC_LOOP_TYPE; + INIT_LIST_HEAD(&entry->list); + list_add_tail(&entry->list, &drvdata->cfg_head[curr_list]); + + return 0; +} + +static ssize_t dcc_config_add_loop(struct dcc_drvdata *drvdata, char *buf, int curr_list) +{ + int ret, i = 0; + char *token, *input; + char delim[2] = " "; + unsigned int val[MAX_LOOP_ADDR]; + + input = buf; + + while ((token = strsep(&input, delim)) && i < MAX_LOOP_ADDR) { + ret = kstrtoint(token, 0, &val[i++]); + if (ret) + return ret; + } + + if (token) { + dev_err(drvdata->dev, "Max limit %u of loop address exceeded", + MAX_LOOP_ADDR); + return -EINVAL; + } + + if (val[1] < 1 || val[1] > 8) + return -EINVAL; + + ret = dcc_add_loop(drvdata, val[0], curr_list); + if (ret) + return ret; + + for (i = 0; i < val[1]; i++) + dcc_config_add(drvdata, val[i + 2], 1, false, curr_list); + + return dcc_add_loop(drvdata, 1, curr_list); +} + +static int dcc_rd_mod_wr_add(struct dcc_drvdata *drvdata, unsigned int mask, + unsigned int val, int curr_list) +{ + int ret = 0; + struct dcc_config_entry *entry; + + mutex_lock(&drvdata->mutex); + + if (list_empty(&drvdata->cfg_head[curr_list])) { + dev_err(drvdata->dev, "DCC: No read address programmed\n"); + ret = -EPERM; + goto out_unlock; + } + + entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL); + if (!entry) { + ret = -ENOMEM; + goto out_unlock; + } + + entry->desc_type = DCC_READ_WRITE_TYPE; + entry->mask = mask; + entry->write_val = val; + list_add_tail(&entry->list, &drvdata->cfg_head[curr_list]); +out_unlock: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static ssize_t dcc_config_add_read_write(struct dcc_drvdata *drvdata, char *buf, int curr_list) +{ + int ret; + int nval; + unsigned int addr, mask, val; + + nval = sscanf(buf, "%x %x %x", &addr, &mask, &val); + + if (nval <= 1 || nval > 3) + return -EINVAL; + + ret = dcc_config_add(drvdata, addr, 1, false, curr_list); + if (ret) + return ret; + + return dcc_rd_mod_wr_add(drvdata, mask, val, curr_list); +} + +static int dcc_add_write(struct dcc_drvdata *drvdata, unsigned int addr, + unsigned int write_val, int apb_bus, int curr_list) +{ + struct dcc_config_entry *entry; + + entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL); + if (!entry) + return -ENOMEM; + + entry->desc_type = DCC_WRITE_TYPE; + entry->base = addr & GENMASK(31, 4); + entry->offset = addr - entry->base; + entry->write_val = write_val; + entry->len = 1; + entry->apb_bus = apb_bus; + list_add_tail(&entry->list, &drvdata->cfg_head[curr_list]); + + return 0; +} + +static ssize_t dcc_config_add_write(struct dcc_drvdata *drvdata, char *buf, int curr_list) +{ + bool bus; + int nval; + unsigned int addr, write_val; + char apb_bus[4]; + + nval = sscanf(buf, "%x %x %3s", &addr, &write_val, apb_bus); + + if (nval <= 1 || nval > 3) + return -EINVAL; + + if (nval == 2) + bus = true; + + if (nval == 3) { + if (!strcmp("apb", apb_bus)) + bus = true; + else if (!strcmp("ahb", apb_bus)) + bus = false; + else + return -EINVAL; + } + + return dcc_add_write(drvdata, addr, write_val, bus, curr_list); +} + +static int config_show(struct seq_file *m, void *data) +{ + struct dcc_drvdata *drvdata = m->private; + struct dcc_config_entry *entry; + int index = 0, curr_list; + + curr_list = dcc_filp_curr_list(m->file); + if (curr_list < 0) + return curr_list; + + mutex_lock(&drvdata->mutex); + + list_for_each_entry(entry, &drvdata->cfg_head[curr_list], list) { + index++; + switch (entry->desc_type) { + case DCC_READ_WRITE_TYPE: + seq_printf(m, "RW mask: 0x%x, val: 0x%x\n index: 0x%x\n", + entry->mask, entry->write_val, index); + break; + case DCC_LOOP_TYPE: + seq_printf(m, "L index: 0x%x Loop: %d\n", index, entry->loop_cnt); + break; + case DCC_WRITE_TYPE: + seq_printf(m, "W Base:0x%x, Offset: 0x%x, val: 0x%x, APB: %d\n, Index: 0x%x\n", + entry->base, entry->offset, entry->write_val, entry->apb_bus, + index); + break; + case DCC_READ_TYPE: + seq_printf(m, "R Base:0x%x, Offset: 0x%x, len: 0x%x, APB: %d\n, Index: 0x%x\n", + entry->base, entry->offset, entry->len, entry->apb_bus, index); + } + } + mutex_unlock(&drvdata->mutex); + return 0; +} + +static int config_open(struct inode *inode, struct file *file) +{ + struct dcc_drvdata *drvdata = inode->i_private; + + return single_open(file, config_show, drvdata); +} + +static ssize_t config_write(struct file *filp, + const char __user *user_buf, size_t count, + loff_t *ppos) +{ + int ret, curr_list; + char *token, buf[50]; + char *bufp = buf; + char *delim = " "; + struct dcc_drvdata *drvdata = filp->private_data; + + if (count > sizeof(buf) || count == 0) + return -EINVAL; + + ret = copy_from_user(buf, user_buf, count); + if (ret) + return -EFAULT; + + curr_list = dcc_filp_curr_list(filp); + if (curr_list < 0) + return curr_list; + + if (buf[count - 1] == '\n') + buf[count - 1] = '\0'; + else + return -EINVAL; + + token = strsep(&bufp, delim); + + if (!strcmp("R", token)) { + ret = dcc_config_add_read(drvdata, bufp, curr_list); + } else if (!strcmp("W", token)) { + ret = dcc_config_add_write(drvdata, bufp, curr_list); + } else if (!strcmp("RW", token)) { + ret = dcc_config_add_read_write(drvdata, bufp, curr_list); + } else if (!strcmp("L", token)) { + ret = dcc_config_add_loop(drvdata, bufp, curr_list); + } else { + dev_err(drvdata->dev, "%s is not a correct input\n", token); + return -EINVAL; + } + + if (ret) + return ret; + + return count; +} + +static const struct file_operations config_fops = { + .open = config_open, + .read = seq_read, + .write = config_write, + .llseek = seq_lseek, + .release = single_release, +}; + +static void dcc_delete_debug_dir(struct dcc_drvdata *drvdata) +{ + debugfs_remove_recursive(drvdata->dbg_dir); +}; + +static void dcc_create_debug_dir(struct dcc_drvdata *drvdata) +{ + int i; + char list_num[10]; + struct dentry *list; + struct device *dev = drvdata->dev; + + drvdata->dbg_dir = debugfs_create_dir(dev_name(dev), NULL); + if (IS_ERR(drvdata->dbg_dir)) { + pr_err("can't create debugfs dir\n"); + return; + } + + for (i = 0; i <= drvdata->nr_link_list; i++) { + sprintf(list_num, "%d", i); + list = debugfs_create_dir(list_num, drvdata->dbg_dir); + debugfs_create_file("enable", 0600, list, drvdata, &enable_fops); + debugfs_create_file("config", 0600, list, drvdata, &config_fops); + } + + debugfs_create_file("trigger", 0200, drvdata->dbg_dir, drvdata, &trigger_fops); + debugfs_create_file("ready", 0400, drvdata->dbg_dir, drvdata, &ready_fops); + debugfs_create_file("config_reset", 0200, drvdata->dbg_dir, + drvdata, &config_reset_fops); +} + +static ssize_t dcc_sram_read(struct file *file, char __user *data, + size_t len, loff_t *ppos) +{ + struct dcc_drvdata *drvdata = container_of(file->private_data, struct dcc_drvdata, sram_dev); + unsigned char *buf; + + /* EOF check */ + if (*ppos >= drvdata->ram_size) + return 0; + + if ((*ppos + len) > drvdata->ram_size) + len = (drvdata->ram_size - *ppos); + + buf = kzalloc(len, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + memcpy_fromio(buf, drvdata->ram_base + *ppos, len); + + if (copy_to_user(data, buf, len)) { + kfree(buf); + return -EFAULT; + } + + *ppos += len; + + kfree(buf); + + return len; +} + +static const struct file_operations dcc_sram_fops = { + .owner = THIS_MODULE, + .read = dcc_sram_read, + .llseek = no_llseek, +}; + +static int dcc_sram_dev_init(struct dcc_drvdata *drvdata) +{ + drvdata->sram_dev.minor = MISC_DYNAMIC_MINOR; + drvdata->sram_dev.name = DCC_SRAM_NODE; + drvdata->sram_dev.fops = &dcc_sram_fops; + + return misc_register(&drvdata->sram_dev); +} + +static void dcc_sram_dev_exit(struct dcc_drvdata *drvdata) +{ + misc_deregister(&drvdata->sram_dev); +} + +static int dcc_probe(struct platform_device *pdev) +{ + u32 val; + int ret = 0, i; + struct device *dev = &pdev->dev; + struct dcc_drvdata *drvdata; + struct resource *res; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->dev = &pdev->dev; + platform_set_drvdata(pdev, drvdata); + + drvdata->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(drvdata->base)) + return PTR_ERR(drvdata->base); + + drvdata->ram_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); + if (IS_ERR(drvdata->ram_base)) + return PTR_ERR(drvdata->ram_base); + + drvdata->ram_size = resource_size(res); + + drvdata->ram_offset = (size_t)of_device_get_match_data(&pdev->dev); + + val = readl(drvdata->base + DCC_HW_INFO); + + if (FIELD_GET(DCC_VER_INFO_MASK, val)) { + drvdata->mem_map_ver = 3; + drvdata->nr_link_list = readl(drvdata->base + DCC_LL_NUM_INFO); + if (!drvdata->nr_link_list) + return -EINVAL; + } else if ((val & DCC_VER_MASK2) == DCC_VER_MASK2) { + drvdata->mem_map_ver = 2; + drvdata->nr_link_list = readl(drvdata->base + DCC_LL_NUM_INFO); + if (!drvdata->nr_link_list) + return -EINVAL; + } else { + drvdata->mem_map_ver = 1; + drvdata->nr_link_list = DCC_MAX_LINK_LIST; + } + + /* Either set the fixed loop offset or calculate + * it from the total number of words in dcc_sram. + * Max consecutive addresses dcc can loop is + * equivalent to the words in dcc_sram. + */ + if (val & DCC_LOOP_OFFSET_MASK) + drvdata->loop_shift = DCC_FIX_LOOP_OFFSET; + else + drvdata->loop_shift = get_bitmask_order((drvdata->ram_offset + + drvdata->ram_size) / DCC_SRAM_WORD_LENGTH - 1); + + mutex_init(&drvdata->mutex); + + drvdata->enable_bitmap = devm_kcalloc(dev, BITS_TO_LONGS(drvdata->nr_link_list), + sizeof(*drvdata->enable_bitmap), GFP_KERNEL); + if (!drvdata->enable_bitmap) + return -ENOMEM; + + drvdata->cfg_head = devm_kcalloc(dev, drvdata->nr_link_list, + sizeof(*drvdata->cfg_head), GFP_KERNEL); + if (!drvdata->cfg_head) + return -ENOMEM; + + for (i = 0; i < drvdata->nr_link_list; i++) + INIT_LIST_HEAD(&drvdata->cfg_head[i]); + + ret = dcc_sram_dev_init(drvdata); + if (ret) { + dev_err(drvdata->dev, "DCC: sram node not registered.\n"); + return ret; + } + + dcc_create_debug_dir(drvdata); + + return 0; +} + +static int dcc_remove(struct platform_device *pdev) +{ + struct dcc_drvdata *drvdata = platform_get_drvdata(pdev); + + dcc_delete_debug_dir(drvdata); + dcc_sram_dev_exit(drvdata); + dcc_config_reset(drvdata); + + return 0; +} + +static const struct of_device_id dcc_match_table[] = { + { .compatible = "qcom,sc7180-dcc", .data = (void *)0x6000 }, + { .compatible = "qcom,sc7280-dcc", .data = (void *)0x12000 }, + { .compatible = "qcom,sdm845-dcc", .data = (void *)0x6000 }, + { .compatible = "qcom,sm8150-dcc", .data = (void *)0x5000 }, + { } +}; +MODULE_DEVICE_TABLE(of, dcc_match_table); + +static struct platform_driver dcc_driver = { + .probe = dcc_probe, + .remove = dcc_remove, + .driver = { + .name = "qcom-dcc", + .of_match_table = dcc_match_table, + }, +}; +module_platform_driver(dcc_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Qualcomm Technologies Inc. DCC driver"); -- cgit v1.2.3 From 40ebfbec52108be22cb68ecb9dcbd4917583a87c Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 28 Dec 2022 11:32:58 -0600 Subject: soc: qcom: ramp_controller: Include linux/bitfield.h Building ramp_controller under x86_64 results in the following build error: error: implicit declaration of function 'FIELD_PREP' is invalid in C99 Include linux/bitfield.h to ensure FIELD_PREP() is declared. Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/ramp_controller.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/ramp_controller.c b/drivers/soc/qcom/ramp_controller.c index 8f8c514b7288..93652b07e812 100644 --- a/drivers/soc/qcom/ramp_controller.c +++ b/drivers/soc/qcom/ramp_controller.c @@ -5,6 +5,7 @@ * */ +#include #include #include #include -- cgit v1.2.3 From f02a537357a61e7892587c0f3455f8295cc9075c Mon Sep 17 00:00:00 2001 From: Naman Jain Date: Fri, 25 Nov 2022 16:05:33 +0530 Subject: soc: qcom: socinfo: Add support for new fields in revision 16 Add support for new fields coming with socinfo structure under v16 to get SKU information, product code and name and type of different parts present in the SoC. Also, add debugfs nodes to read feature and product codes to allow user to get SKU and other SoC details. Support for SoC parts name and type parsing will be added separately. Details of fields added: * feature_code: mapped to qcom internal and external SKU IDs * pcode: product code * npartnamemap_offset: parts name map array offset from socinfo base ptr * nnum_partname_mapping: number of part mappings Signed-off-by: Naman Jain Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221125103533.2960-1-quic_namajain@quicinc.com --- drivers/soc/qcom/socinfo.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index ebcbf9b9c18b..10efdbcfdf05 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -169,6 +169,11 @@ struct socinfo { __le32 ndefective_parts_array_offset; /* Version 15 */ __le32 nmodem_supported; + /* Version 16 */ + __le32 feature_code; + __le32 pcode; + __le32 npartnamemap_offset; + __le32 nnum_partname_mapping; }; #ifdef CONFIG_DEBUG_FS @@ -189,6 +194,8 @@ struct socinfo_params { u32 num_defective_parts; u32 ndefective_parts_array_offset; u32 nmodem_supported; + u32 feature_code; + u32 pcode; }; struct smem_image_version { @@ -512,6 +519,15 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, &qcom_socinfo->info.fmt); switch (qcom_socinfo->info.fmt) { + case SOCINFO_VERSION(0, 16): + qcom_socinfo->info.feature_code = __le32_to_cpu(info->feature_code); + qcom_socinfo->info.pcode = __le32_to_cpu(info->pcode); + + debugfs_create_u32("feature_code", 0444, qcom_socinfo->dbg_root, + &qcom_socinfo->info.feature_code); + debugfs_create_u32("pcode", 0444, qcom_socinfo->dbg_root, + &qcom_socinfo->info.pcode); + fallthrough; case SOCINFO_VERSION(0, 15): qcom_socinfo->info.nmodem_supported = __le32_to_cpu(info->nmodem_supported); -- cgit v1.2.3 From 9d3975f27e12c89327fbac84c3d8552ecdb72a35 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 16 Dec 2022 21:08:18 +0100 Subject: soc: imx: add Kconfig symbols for blk-ctrl drivers Currently the dependencies of the blk-ctrl drivers are not fully described in Kconfig, which can trip over the compile tests on platforms where those drivers are not usually enabled. Add a non user-selectable symbol to be describe those dependencies. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- drivers/soc/imx/Kconfig | 10 ++++++++++ drivers/soc/imx/Makefile | 6 +++--- 2 files changed, 13 insertions(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/Kconfig b/drivers/soc/imx/Kconfig index 4b906791d6c7..179bcc896ea2 100644 --- a/drivers/soc/imx/Kconfig +++ b/drivers/soc/imx/Kconfig @@ -28,4 +28,14 @@ config SOC_IMX9 help If you say yes here, you get support for the NXP i.MX9 family +config IMX8M_BLK_CTRL + bool + default SOC_IMX8M && IMX_GPCV2_PM_DOMAINS + depends on PM_GENERIC_DOMAINS + +config IMX9_BLK_CTRL + bool + default SOC_IMX9 && IMX_GPCV2_PM_DOMAINS + depends on PM_GENERIC_DOMAINS + endmenu diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile index 7b4099ceafd6..a28c44a1f16a 100644 --- a/drivers/soc/imx/Makefile +++ b/drivers/soc/imx/Makefile @@ -5,7 +5,7 @@ endif obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o -obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o -obj-$(CONFIG_SOC_IMX8M) += imx8mp-blk-ctrl.o +obj-$(CONFIG_IMX8M_BLK_CTRL) += imx8m-blk-ctrl.o +obj-$(CONFIG_IMX8M_BLK_CTRL) += imx8mp-blk-ctrl.o obj-$(CONFIG_SOC_IMX9) += imx93-src.o imx93-pd.o -obj-$(CONFIG_SOC_IMX9) += imx93-blk-ctrl.o +obj-$(CONFIG_IMX9_BLK_CTRL) += imx93-blk-ctrl.o -- cgit v1.2.3 From f4b3948e5a90f49b33e89b019d3c641ab9a6fc59 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 16 Dec 2022 21:08:19 +0100 Subject: soc: imx: imx8mp-blk-ctrl: add instance specific probe function Allow the specific blk-ctrl instance to define a function, which will be called during probe to provide device specific extensions. Signed-off-by: Lucas Stach Tested-by: Marcel Ziswiler Tested-by: Lukas F. Hartmann Signed-off-by: Shawn Guo --- drivers/soc/imx/imx8mp-blk-ctrl.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c index 0e3b6ba22f94..b3d9f6e083ba 100644 --- a/drivers/soc/imx/imx8mp-blk-ctrl.c +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c @@ -60,6 +60,7 @@ struct imx8mp_blk_ctrl_domain { struct imx8mp_blk_ctrl_data { int max_reg; + int (*probe) (struct imx8mp_blk_ctrl *bc); notifier_fn_t power_notifier_fn; void (*power_off) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain); void (*power_on) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain); @@ -634,6 +635,12 @@ static int imx8mp_blk_ctrl_probe(struct platform_device *pdev) goto cleanup_provider; } + if (bc_data->probe) { + ret = bc_data->probe(bc); + if (ret) + goto cleanup_provider; + } + dev_set_drvdata(dev, bc); return 0; -- cgit v1.2.3 From 2cbee26e5d592da942a995ddee78ea3eb97ad2fa Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 16 Dec 2022 21:08:20 +0100 Subject: soc: imx: imx8mp-blk-ctrl: expose high performance PLL clock Expose the high performance PLL as a regular Linux clock, so the PCIe PHY can use it when there is no external refclock provided. Signed-off-by: Lucas Stach Tested-by: Marcel Ziswiler Tested-by: Lukas F. Hartmann Signed-off-by: Shawn Guo --- drivers/soc/imx/Kconfig | 1 + drivers/soc/imx/imx8mp-blk-ctrl.c | 98 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/Kconfig b/drivers/soc/imx/Kconfig index 179bcc896ea2..a8742fc58f01 100644 --- a/drivers/soc/imx/Kconfig +++ b/drivers/soc/imx/Kconfig @@ -32,6 +32,7 @@ config IMX8M_BLK_CTRL bool default SOC_IMX8M && IMX_GPCV2_PM_DOMAINS depends on PM_GENERIC_DOMAINS + depends on COMMON_CLK config IMX9_BLK_CTRL bool diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c index b3d9f6e083ba..0629f64ef4f1 100644 --- a/drivers/soc/imx/imx8mp-blk-ctrl.c +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c @@ -4,7 +4,9 @@ * Copyright 2022 Pengutronix, Lucas Stach */ +#include #include +#include #include #include #include @@ -21,6 +23,15 @@ #define USB_CLOCK_MODULE_EN BIT(1) #define PCIE_PHY_APB_RST BIT(4) #define PCIE_PHY_INIT_RST BIT(5) +#define GPR_REG1 0x4 +#define PLL_LOCK BIT(13) +#define GPR_REG2 0x8 +#define P_PLL_MASK GENMASK(5, 0) +#define M_PLL_MASK GENMASK(15, 6) +#define S_PLL_MASK GENMASK(18, 16) +#define GPR_REG3 0xc +#define PLL_CKE BIT(17) +#define PLL_RST BIT(31) struct imx8mp_blk_ctrl_domain; @@ -74,6 +85,92 @@ to_imx8mp_blk_ctrl_domain(struct generic_pm_domain *genpd) return container_of(genpd, struct imx8mp_blk_ctrl_domain, genpd); } +struct clk_hsio_pll { + struct clk_hw hw; + struct regmap *regmap; +}; + +static inline struct clk_hsio_pll *to_clk_hsio_pll(struct clk_hw *hw) +{ + return container_of(hw, struct clk_hsio_pll, hw); +} + +static int clk_hsio_pll_prepare(struct clk_hw *hw) +{ + struct clk_hsio_pll *clk = to_clk_hsio_pll(hw); + u32 val; + + /* set the PLL configuration */ + regmap_update_bits(clk->regmap, GPR_REG2, + P_PLL_MASK | M_PLL_MASK | S_PLL_MASK, + FIELD_PREP(P_PLL_MASK, 12) | + FIELD_PREP(M_PLL_MASK, 800) | + FIELD_PREP(S_PLL_MASK, 4)); + + /* de-assert PLL reset */ + regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST, PLL_RST); + + /* enable PLL */ + regmap_update_bits(clk->regmap, GPR_REG3, PLL_CKE, PLL_CKE); + + return regmap_read_poll_timeout(clk->regmap, GPR_REG1, val, + val & PLL_LOCK, 10, 100); +} + +static void clk_hsio_pll_unprepare(struct clk_hw *hw) +{ + struct clk_hsio_pll *clk = to_clk_hsio_pll(hw); + + regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST | PLL_CKE, 0); +} + +static int clk_hsio_pll_is_prepared(struct clk_hw *hw) +{ + struct clk_hsio_pll *clk = to_clk_hsio_pll(hw); + + return regmap_test_bits(clk->regmap, GPR_REG1, PLL_LOCK); +} + +static unsigned long clk_hsio_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return 100000000; +} + +static const struct clk_ops clk_hsio_pll_ops = { + .prepare = clk_hsio_pll_prepare, + .unprepare = clk_hsio_pll_unprepare, + .is_prepared = clk_hsio_pll_is_prepared, + .recalc_rate = clk_hsio_pll_recalc_rate, +}; + +static int imx8mp_hsio_blk_ctrl_probe(struct imx8mp_blk_ctrl *bc) +{ + struct clk_hsio_pll *clk_hsio_pll; + struct clk_hw *hw; + struct clk_init_data init = {}; + int ret; + + clk_hsio_pll = devm_kzalloc(bc->dev, sizeof(*clk_hsio_pll), GFP_KERNEL); + if (!clk_hsio_pll) + return -ENOMEM; + + init.name = "hsio_pll"; + init.ops = &clk_hsio_pll_ops; + init.parent_names = (const char *[]){"osc_24m"}; + init.num_parents = 1; + + clk_hsio_pll->regmap = bc->regmap; + clk_hsio_pll->hw.init = &init; + + hw = &clk_hsio_pll->hw; + ret = devm_clk_hw_register(bc->dev, hw); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(bc->dev, of_clk_hw_simple_get, hw); +} + static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain) { @@ -188,6 +285,7 @@ static const struct imx8mp_blk_ctrl_domain_data imx8mp_hsio_domain_data[] = { static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = { .max_reg = 0x24, + .probe = imx8mp_hsio_blk_ctrl_probe, .power_on = imx8mp_hsio_blk_ctrl_power_on, .power_off = imx8mp_hsio_blk_ctrl_power_off, .power_notifier_fn = imx8mp_hsio_power_notifier, -- cgit v1.2.3 From 06a9a229b1592abeb10728c8564492f0729f4b83 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Tue, 20 Dec 2022 18:53:53 +0100 Subject: soc: imx: imx8m-blk-ctrl: set LCDIF panic read hurry level When the LCDIF block signals a panic condition due to the display FIFO falling below the threshold, the priority at the NoC level is boosted to the value set in the LCDIF_ARCACHE_CTRL register of i.MX8MP mediamix blk-ctrl. Same as all other blk-ctrl registers this register is reset when the domain is powered down. Initialize the panic hurry levels for both LCIF interfaces to the maximium priority (same as downstream TF-A and proven to work with the other priorities set in the interconnect driver) when coming back from power down. Signed-off-by: Lucas Stach Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- drivers/soc/imx/imx8m-blk-ctrl.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c index ddcf6be3d8b4..399cb85105a1 100644 --- a/drivers/soc/imx/imx8m-blk-ctrl.c +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -4,6 +4,7 @@ * Copyright 2021 Pengutronix, Lucas Stach */ +#include #include #include #include @@ -654,6 +655,10 @@ static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = { .num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data), }; +#define LCDIF_ARCACHE_CTRL 0x4c +#define LCDIF_1_RD_HURRY GENMASK(15, 13) +#define LCDIF_0_RD_HURRY GENMASK(12, 10) + static int imx8mp_media_power_notifier(struct notifier_block *nb, unsigned long action, void *data) { @@ -667,14 +672,24 @@ static int imx8mp_media_power_notifier(struct notifier_block *nb, regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8)); regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8)); - /* - * On power up we have no software backchannel to the GPC to - * wait for the ADB handshake to happen, so we just delay for a - * bit. On power down the GPC driver waits for the handshake. - */ - if (action == GENPD_NOTIFY_ON) + if (action == GENPD_NOTIFY_ON) { + /* + * On power up we have no software backchannel to the GPC to + * wait for the ADB handshake to happen, so we just delay for a + * bit. On power down the GPC driver waits for the handshake. + */ udelay(5); + /* + * Set panic read hurry level for both LCDIF interfaces to + * maximum priority to minimize chances of display FIFO + * underflow. + */ + regmap_set_bits(bc->regmap, LCDIF_ARCACHE_CTRL, + FIELD_PREP(LCDIF_1_RD_HURRY, 7) | + FIELD_PREP(LCDIF_0_RD_HURRY, 7)); + } + return NOTIFY_OK; } -- cgit v1.2.3 From 083dab5e69f3dc9a3c85b2d690ff91cfed57e926 Mon Sep 17 00:00:00 2001 From: Deepak R Varma Date: Thu, 22 Dec 2022 23:23:16 +0530 Subject: soc: imx: imx93-pd: No need to set device_driver owner There is no need to exclusively set the .owner member of the struct device_driver when defining the platform_driver struct. The Linux core takes care of setting the .owner member as part of the call to module_platform_driver() helper function. Issue identified using the platform_no_drv_owner.cocci Coccinelle semantic patch. Signed-off-by: Deepak R Varma Signed-off-by: Shawn Guo --- drivers/soc/imx/imx93-pd.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/imx93-pd.c b/drivers/soc/imx/imx93-pd.c index 4d235c8c4924..832deeed8fd6 100644 --- a/drivers/soc/imx/imx93-pd.c +++ b/drivers/soc/imx/imx93-pd.c @@ -164,7 +164,6 @@ MODULE_DEVICE_TABLE(of, imx93_pd_ids); static struct platform_driver imx93_power_domain_driver = { .driver = { .name = "imx93_power_domain", - .owner = THIS_MODULE, .of_match_table = imx93_pd_ids, }, .probe = imx93_pd_probe, -- cgit v1.2.3 From 3c047887243c72e7835a17e90361ed19e8354bf5 Mon Sep 17 00:00:00 2001 From: Deepak R Varma Date: Thu, 22 Dec 2022 23:27:03 +0530 Subject: soc: imx: imx93-src: No need to set device_driver owner There is no need to exclusively set the .owner member of the struct device_driver when defining the platform_driver struct. The Linux core takes care of setting the .owner member as part of the call to module_platform_driver() helper function. Issue identified using the platform_no_drv_owner.cocci Coccinelle semantic patch. Signed-off-by: Deepak R Varma Signed-off-by: Shawn Guo --- drivers/soc/imx/imx93-src.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/imx93-src.c b/drivers/soc/imx/imx93-src.c index 4d74921cae0f..f1c2e22d5cbd 100644 --- a/drivers/soc/imx/imx93-src.c +++ b/drivers/soc/imx/imx93-src.c @@ -21,7 +21,6 @@ MODULE_DEVICE_TABLE(of, imx93_src_ids); static struct platform_driver imx93_src_driver = { .driver = { .name = "imx93_src", - .owner = THIS_MODULE, .of_match_table = imx93_src_ids, }, .probe = imx93_src_probe, -- cgit v1.2.3 From 9a217b7e895313a4d42f7a6c48b6237a595945f4 Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Fri, 2 Dec 2022 12:52:15 +0100 Subject: soc: amlogic: meson-pwrc: Add NNA power domain for A311D Based on power initialization sequence in downstream driver. Signed-off-by: Tomeu Vizoso Reviewed-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20221202115223.39051-4-tomeu.vizoso@collabora.com Signed-off-by: Neil Armstrong --- drivers/soc/amlogic/meson-ee-pwrc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/amlogic/meson-ee-pwrc.c b/drivers/soc/amlogic/meson-ee-pwrc.c index dd5f2a13ceb5..f54acffc83f9 100644 --- a/drivers/soc/amlogic/meson-ee-pwrc.c +++ b/drivers/soc/amlogic/meson-ee-pwrc.c @@ -46,6 +46,9 @@ #define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2) #define HHI_VPU_MEM_PD_REG2 (0x4d << 2) +#define G12A_HHI_NANOQ_MEM_PD_REG0 (0x43 << 2) +#define G12A_HHI_NANOQ_MEM_PD_REG1 (0x44 << 2) + struct meson_ee_pwrc; struct meson_ee_pwrc_domain; @@ -106,6 +109,13 @@ static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17); static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18); static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19); +static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = { + .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, + .sleep_mask = BIT(16) | BIT(17), + .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, + .iso_mask = BIT(16) | BIT(17), +}; + /* Memory PD Domains */ #define VPU_MEMPD(__reg) \ @@ -217,6 +227,11 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = { { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) }, }; +static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = { + { G12A_HHI_NANOQ_MEM_PD_REG0, GENMASK(31, 0) }, + { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(23, 0) }, +}; + #define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \ { \ .name = __name, \ @@ -253,6 +268,8 @@ static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = { [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu, pwrc_ee_is_powered_off, 11, 2), [PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), + [PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna, + pwrc_ee_is_powered_off), }; static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = { -- cgit v1.2.3 From 1bea534991b9b35c41848a397666ada436456beb Mon Sep 17 00:00:00 2001 From: Gaosheng Cui Date: Tue, 29 Nov 2022 09:01:46 +0800 Subject: driver: soc: xilinx: fix memory leak in xlnx_add_cb_for_notify_event() The kfree() should be called when memory fails to be allocated for cb_data in xlnx_add_cb_for_notify_event(), otherwise there will be a memory leak, so add kfree() to fix it. Fixes: 05e5ba40ea7a ("driver: soc: xilinx: Add support of multiple callbacks for same event in event management driver") Signed-off-by: Gaosheng Cui Acked-by: Michal Simek Link: https://lore.kernel.org/r/20221129010146.1026685-1-cuigaosheng1@huawei.com Signed-off-by: Michal Simek --- drivers/soc/xilinx/xlnx_event_manager.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/xilinx/xlnx_event_manager.c b/drivers/soc/xilinx/xlnx_event_manager.c index 2de082765bef..c76381899ef4 100644 --- a/drivers/soc/xilinx/xlnx_event_manager.c +++ b/drivers/soc/xilinx/xlnx_event_manager.c @@ -116,8 +116,10 @@ static int xlnx_add_cb_for_notify_event(const u32 node_id, const u32 event, cons INIT_LIST_HEAD(&eve_data->cb_list_head); cb_data = kmalloc(sizeof(*cb_data), GFP_KERNEL); - if (!cb_data) + if (!cb_data) { + kfree(eve_data); return -ENOMEM; + } cb_data->eve_cb = cb_fun; cb_data->agent_data = data; -- cgit v1.2.3 From fcc2f972f948d8bd5f8f149617d821b0ae3ad5fd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 8 Dec 2022 13:32:11 +0100 Subject: firmware: xilinx: Remove kernel-doc marking in the code Trivial fix. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f4c61cd5e45fab345c366a15766101408fbc3bcd.1670502727.git.michal.simek@amd.com --- drivers/soc/xilinx/zynqmp_pm_domains.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/xilinx/zynqmp_pm_domains.c b/drivers/soc/xilinx/zynqmp_pm_domains.c index fcce2433bd6d..69d03ad4cf1e 100644 --- a/drivers/soc/xilinx/zynqmp_pm_domains.c +++ b/drivers/soc/xilinx/zynqmp_pm_domains.c @@ -227,7 +227,7 @@ static struct generic_pm_domain *zynqmp_gpd_xlate goto done; } - /** + /* * Add index in empty node_id of power domain list as no existing * power domain found for current index. */ -- cgit v1.2.3 From d4b2c7484a8edd79c90b9f8acc8a03e5e3235b89 Mon Sep 17 00:00:00 2001 From: Yang Li Date: Fri, 6 Jan 2023 09:17:10 +0800 Subject: soc: qcom: dcc: Fix unsigned comparison with less than zero The return value from the call to kstrtouint_from_user() is int. However, the return value is being assigned to an unsigned int variable 'ret', so making 'ret' an int. Eliminate the following warning: ./drivers/soc/qcom/dcc.c:815:5-8: WARNING: Unsigned expression compared with zero: ret < 0 Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=3638 Fixes: 4cbe60cf5ad6 ("soc: qcom: dcc: Add driver support for Data Capture and Compare unit(DCC)") Reported-by: Abaci Robot Signed-off-by: Yang Li Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230106011710.2827-1-yang.lee@linux.alibaba.com --- drivers/soc/qcom/dcc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/dcc.c b/drivers/soc/qcom/dcc.c index d4101f79cb5d..5b50d638771d 100644 --- a/drivers/soc/qcom/dcc.c +++ b/drivers/soc/qcom/dcc.c @@ -808,7 +808,8 @@ static ssize_t config_reset_write(struct file *filp, const char __user *user_buf, size_t count, loff_t *ppos) { - unsigned int val, ret; + unsigned int val; + int ret; struct dcc_drvdata *drvdata = filp->private_data; ret = kstrtouint_from_user(user_buf, count, 0, &val); -- cgit v1.2.3 From 169fa2ad8daa1cec78a8f9f2df1b57bc125509a6 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Mon, 12 Dec 2022 23:25:48 +0100 Subject: soc: mediatek: mutex: Drop empty platform remove function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A remove callback just returning 0 is equivalent to no remove callback at all. So drop the useless function. Signed-off-by: Uwe Kleine-König Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mutex.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index c1a33d52038e..85f7fd67d7c6 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -832,11 +832,6 @@ static int mtk_mutex_probe(struct platform_device *pdev) return 0; } -static int mtk_mutex_remove(struct platform_device *pdev) -{ - return 0; -} - static const struct of_device_id mutex_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-mutex", .data = &mt2701_mutex_driver_data}, @@ -866,7 +861,6 @@ MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); static struct platform_driver mtk_mutex_driver = { .probe = mtk_mutex_probe, - .remove = mtk_mutex_remove, .driver = { .name = "mediatek-mutex", .owner = THIS_MODULE, -- cgit v1.2.3 From 3b1a57c4f999629fb1d5e7a488bdda536146fb31 Mon Sep 17 00:00:00 2001 From: Nathan Lu Date: Tue, 6 Dec 2022 10:00:44 +0800 Subject: soc: mediatek: add mtk-mmsys support for mt8188 vdosys0 1. add mt8188 mmsys 2. add mt8188 vdosys0 routing table settings Signed-off-by: amy zhang Signed-off-by: Nathan Lu Link: https://lore.kernel.org/r/20221206020046.11333-5-nathan.lu@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mt8188-mmsys.h | 149 ++++++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 11 +++ 2 files changed, 160 insertions(+) create mode 100644 drivers/soc/mediatek/mt8188-mmsys.h (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h new file mode 100644 index 000000000000..448cc3761b43 --- /dev/null +++ b/drivers/soc/mediatek/mt8188-mmsys.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8188_MMSYS_H +#define __SOC_MEDIATEK_MT8188_MMSYS_H + +#define MT8188_VDO0_OVL_MOUT_EN 0xf14 +#define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) +#define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) +#define MT8188_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) +#define MT8188_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4) +#define MT8188_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5) +#define MT8188_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) + +#define MT8188_VDO0_SEL_IN 0xf34 +#define MT8188_VDO0_SEL_OUT 0xf38 + +#define MT8188_VDO0_DISP_RDMA_SEL 0xf40 +#define MT8188_SOUT_DISP_RDMA0_TO_MASK GENMASK(2, 0) +#define MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0 (0 << 0) +#define MT8188_SOUT_DISP_RDMA0_TO_DISP_DSI0 (1 << 0) +#define MT8188_SOUT_DISP_RDMA0_TO_DISP_DP_INTF0 (5 << 0) +#define MT8188_SEL_IN_DISP_RDMA0_FROM_MASK GENMASK(8, 8) +#define MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0 (0 << 8) +#define MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_RSZ0 (1 << 8) + + +#define MT8188_VDO0_DSI0_SEL_IN 0xf44 +#define MT8188_SEL_IN_DSI0_FROM_MASK BIT(0) +#define MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 0) +#define MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 0) + +#define MT8188_VDO0_DP_INTF0_SEL_IN 0xf4C +#define MT8188_SEL_IN_DP_INTF0_FROM_MASK GENMASK(2, 0) +#define MT8188_SEL_IN_DP_INTF0_FROM_DSC_WRAP0C1_OUT (0 << 0) +#define MT8188_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 0) +#define MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0 (3 << 0) + +#define MT8188_VDO0_DISP_DITHER0_SEL_OUT 0xf58 +#define MT8188_SOUT_DISP_DITHER0_TO_MASK GENMASK(2, 0) +#define MT8188_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0) +#define MT8188_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0) +#define MT8188_SOUT_DISP_DITHER0_TO_VPP_MERGE0 (6 << 0) +#define MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0 (7 << 0) + +#define MT8188_VDO0_VPP_MERGE_SEL 0xf60 +#define MT8188_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0) +#define MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) +#define MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT (3 << 0) + +#define MT8188_SOUT_VPP_MERGE_TO_MASK GENMASK(6, 4) +#define MT8188_SOUT_VPP_MERGE_TO_DSI1 (0 << 4) +#define MT8188_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 4) +#define MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 4) +#define MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 4) +#define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 4) +#define MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0 (5 << 4) +#define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11) +#define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11) + +#define MT8188_VDO0_DSC_WARP_SEL 0xf64 +#define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK GENMASK(0, 0) +#define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0 (0 << 0) +#define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_VPP_MERGE (1 << 0) +#define MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(19, 16) +#define MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0 BIT(16) +#define MT8188_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 BIT(17) +#define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18) +#define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19) + +static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = { + { + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, + MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0, + MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 + }, { + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, + MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0, + MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 + }, { + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, + MT8188_VDO0_DISP_RDMA_SEL, MT8188_SEL_IN_DISP_RDMA0_FROM_MASK, + MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0 + }, { + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, + MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK, + MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0 + }, { + DDP_COMPONENT_DITHER0, DDP_COMPONENT_MERGE0, + MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK, + MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT + }, { + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, + MT8188_VDO0_DSC_WARP_SEL, + MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK, + MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0 + }, { + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0, + MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK, + MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0 + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, + MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK, + MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, + MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK, + MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT + }, { + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, + MT8188_VDO0_DISP_RDMA_SEL, MT8188_SOUT_DISP_RDMA0_TO_MASK, + MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0 + }, { + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, + MT8188_VDO0_DISP_DITHER0_SEL_OUT, + MT8188_SOUT_DISP_DITHER0_TO_MASK, + MT8188_SOUT_DISP_DITHER0_TO_DSI0 + }, { + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0, + MT8188_VDO0_DISP_DITHER0_SEL_OUT, + MT8188_SOUT_DISP_DITHER0_TO_MASK, + MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, + MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, + MT8188_SOUT_VPP_MERGE_TO_DP_INTF0 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, + MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, + MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA0, + MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, + MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0 + }, { + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, + MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, + MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, + MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0 + }, { + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, + MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK, + MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE + }, +}; + +#endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index f3431448e843..9974b5199377 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -16,6 +16,7 @@ #include "mt8167-mmsys.h" #include "mt8183-mmsys.h" #include "mt8186-mmsys.h" +#include "mt8188-mmsys.h" #include "mt8192-mmsys.h" #include "mt8195-mmsys.h" #include "mt8365-mmsys.h" @@ -67,6 +68,12 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, }; +static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { + .clk_driver = "clk-mt8188-vdo0", + .routes = mmsys_mt8188_routing_table, + .num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table), +}; + static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .clk_driver = "clk-mt8192-mm", .routes = mmsys_mt8192_routing_table, @@ -299,6 +306,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = { .compatible = "mediatek,mt8186-mmsys", .data = &mt8186_mmsys_driver_data, }, + { + .compatible = "mediatek,mt8188-vdosys0", + .data = &mt8188_vdosys0_driver_data, + }, { .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data, -- cgit v1.2.3 From 64bc37bf398651b712fb68921b3f674f98a9f802 Mon Sep 17 00:00:00 2001 From: Nathan Lu Date: Tue, 6 Dec 2022 10:00:45 +0800 Subject: soc: mediatek: add mtk-mutex support for mt8188 vdosys0 add mtk-mutex support for mt8188 vdosys0. Signed-off-by: amy zhang Signed-off-by: Nathan Lu Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221206020046.11333-6-nathan.lu@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mutex.c | 53 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 85f7fd67d7c6..cc934729c1f3 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -116,6 +116,21 @@ #define MT8173_MUTEX_MOD_DISP_PWM1 24 #define MT8173_MUTEX_MOD_DISP_OD 25 +#define MT8188_MUTEX_MOD_DISP_OVL0 0 +#define MT8188_MUTEX_MOD_DISP_WDMA0 1 +#define MT8188_MUTEX_MOD_DISP_RDMA0 2 +#define MT8188_MUTEX_MOD_DISP_COLOR0 3 +#define MT8188_MUTEX_MOD_DISP_CCORR0 4 +#define MT8188_MUTEX_MOD_DISP_AAL0 5 +#define MT8188_MUTEX_MOD_DISP_GAMMA0 6 +#define MT8188_MUTEX_MOD_DISP_DITHER0 7 +#define MT8188_MUTEX_MOD_DISP_DSI0 8 +#define MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 +#define MT8188_MUTEX_MOD_DISP_VPP_MERGE 20 +#define MT8188_MUTEX_MOD_DISP_DP_INTF0 21 +#define MT8188_MUTEX_MOD_DISP_POSTMASK0 24 +#define MT8188_MUTEX_MOD2_DISP_PWM0 33 + #define MT8195_MUTEX_MOD_DISP_OVL0 0 #define MT8195_MUTEX_MOD_DISP_WDMA0 1 #define MT8195_MUTEX_MOD_DISP_RDMA0 2 @@ -180,6 +195,8 @@ #define MT8167_MUTEX_SOF_DPI1 3 #define MT8183_MUTEX_SOF_DSI0 1 #define MT8183_MUTEX_SOF_DPI0 2 +#define MT8188_MUTEX_SOF_DSI0 1 +#define MT8188_MUTEX_SOF_DP_INTF0 3 #define MT8195_MUTEX_SOF_DSI0 1 #define MT8195_MUTEX_SOF_DSI1 2 #define MT8195_MUTEX_SOF_DP_INTF0 3 @@ -189,6 +206,8 @@ #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) +#define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7) +#define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7) #define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7) #define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7) #define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7) @@ -344,6 +363,23 @@ static const unsigned int mt8186_mdp_mutex_table_mod[MUTEX_MOD_IDX_MAX] = { [MUTEX_MOD_IDX_MDP_COLOR0] = MT8186_MUTEX_MOD_MDP_COLOR0, }; +static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_OVL0] = MT8188_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_WDMA0] = MT8188_MUTEX_MOD_DISP_WDMA0, + [DDP_COMPONENT_RDMA0] = MT8188_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_COLOR0] = MT8188_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_CCORR] = MT8188_MUTEX_MOD_DISP_CCORR0, + [DDP_COMPONENT_AAL0] = MT8188_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_GAMMA] = MT8188_MUTEX_MOD_DISP_GAMMA0, + [DDP_COMPONENT_POSTMASK0] = MT8188_MUTEX_MOD_DISP_POSTMASK0, + [DDP_COMPONENT_DITHER0] = MT8188_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_MERGE0] = MT8188_MUTEX_MOD_DISP_VPP_MERGE, + [DDP_COMPONENT_DSC0] = MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0, + [DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0, + [DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0, + [DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0, +}; + static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0, @@ -435,6 +471,14 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = { * but also detect the error at end of frame(EAEOF) when EOF signal * arrives. */ +static const unsigned int mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = { + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, + [MUTEX_SOF_DSI0] = + MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0, + [MUTEX_SOF_DP_INTF0] = + MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0, +}; + static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0, @@ -505,6 +549,13 @@ static const struct mtk_mutex_data mt8186_mutex_driver_data = { .mutex_sof_reg = MT8183_MUTEX0_SOF0, }; +static const struct mtk_mutex_data mt8188_mutex_driver_data = { + .mutex_mod = mt8188_mutex_mod, + .mutex_sof = mt8188_mutex_sof, + .mutex_mod_reg = MT8183_MUTEX0_MOD0, + .mutex_sof_reg = MT8183_MUTEX0_SOF0, +}; + static const struct mtk_mutex_data mt8192_mutex_driver_data = { .mutex_mod = mt8192_mutex_mod, .mutex_sof = mt8183_mutex_sof, @@ -849,6 +900,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8186_mutex_driver_data}, { .compatible = "mediatek,mt8186-mdp3-mutex", .data = &mt8186_mdp_mutex_driver_data}, + { .compatible = "mediatek,mt8188-disp-mutex", + .data = &mt8188_mutex_driver_data}, { .compatible = "mediatek,mt8192-disp-mutex", .data = &mt8192_mutex_driver_data}, { .compatible = "mediatek,mt8195-disp-mutex", -- cgit v1.2.3 From 0d08c56d97a614f56d74f490d693faf8038db125 Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Wed, 12 Oct 2022 15:54:34 +0800 Subject: soc: mediatek: mtk-pm-domains: Allow mt8186 ADSP default power on In the use case of configuring the access permissions of the ADSP core, the mt8186 SoC ADSP power will be switched on in the bootloader because the permission control registers are located in the ADSP subsys. Signed-off-by: Tinghan Shen Fixes: 88590cbc1703 ("soc: mediatek: pm-domains: Add support for mt8186") Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221012075434.30009-1-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mt8186-pm-domains.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mt8186-pm-domains.h b/drivers/soc/mediatek/mt8186-pm-domains.h index 108af61854a3..fce86f79c505 100644 --- a/drivers/soc/mediatek/mt8186-pm-domains.h +++ b/drivers/soc/mediatek/mt8186-pm-domains.h @@ -304,7 +304,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { .ctl_offs = 0x9FC, .pwr_sta_offs = 0x16C, .pwr_sta2nd_offs = 0x170, - .caps = MTK_SCPD_KEEP_DEFAULT_OFF, }, [MT8186_POWER_DOMAIN_ADSP_INFRA] = { .name = "adsp_infra", @@ -312,7 +311,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { .ctl_offs = 0x9F8, .pwr_sta_offs = 0x16C, .pwr_sta2nd_offs = 0x170, - .caps = MTK_SCPD_KEEP_DEFAULT_OFF, }, [MT8186_POWER_DOMAIN_ADSP_TOP] = { .name = "adsp_top", @@ -332,7 +330,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { MT8186_TOP_AXI_PROT_EN_3_CLR, MT8186_TOP_AXI_PROT_EN_3_STA), }, - .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, + .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP, }, }; -- cgit v1.2.3 From a7596e62dac7318456c1aa9af5bfccf0f8e6ad7e Mon Sep 17 00:00:00 2001 From: Yongqiang Niu Date: Fri, 18 Nov 2022 14:30:18 +0800 Subject: mtk-mmsys: Change mtk-mmsys & mtk-mutex to modules Change mtk-mmsys & mtk-mutex to modules for gki Signed-off-by: Yongqiang Niu Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221118063018.13520-1-yongqiang.niu@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/Kconfig | 2 +- drivers/soc/mediatek/mtk-mmsys.c | 18 +++++++++++++++++- drivers/soc/mediatek/mtk-mutex.c | 17 ++++++++++++++++- 3 files changed, 34 insertions(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index 40d0cc600cae..20c77152c282 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -68,7 +68,7 @@ config MTK_SCPSYS_PM_DOMAINS tasks in the system. config MTK_MMSYS - bool "MediaTek MMSYS Support" + tristate "MediaTek MMSYS Support" default ARCH_MEDIATEK depends on HAS_IOMEM help diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 9974b5199377..38f1dd92e7c6 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -337,4 +338,19 @@ static struct platform_driver mtk_mmsys_drv = { .probe = mtk_mmsys_probe, }; -builtin_platform_driver(mtk_mmsys_drv); +static int __init mtk_mmsys_init(void) +{ + return platform_driver_register(&mtk_mmsys_drv); +} + +static void __exit mtk_mmsys_exit(void) +{ + platform_driver_unregister(&mtk_mmsys_drv); +} + +module_init(mtk_mmsys_init); +module_exit(mtk_mmsys_exit); + +MODULE_AUTHOR("Yongqiang Niu "); +MODULE_DESCRIPTION("MediaTek SoC MMSYS driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index cc934729c1f3..582d4b04e353 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -921,4 +921,19 @@ static struct platform_driver mtk_mutex_driver = { }, }; -builtin_platform_driver(mtk_mutex_driver); +static int __init mtk_mutex_init(void) +{ + return platform_driver_register(&mtk_mutex_driver); +} + +static void __exit mtk_mutex_exit(void) +{ + platform_driver_unregister(&mtk_mutex_driver); +} + +module_init(mtk_mutex_init); +module_exit(mtk_mutex_exit); + +MODULE_AUTHOR("Yongqiang Niu "); +MODULE_DESCRIPTION("MediaTek SoC MUTEX driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 91e910adc59a6954e475dd2d6a4534ac56dd8eed Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 9 Jan 2023 18:45:07 +0100 Subject: soc: qcom: rmphpd: add power domains for sa8775p Add power domain description for sa8775p and a new compatible to match it. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230109174511.1740856-15-brgl@bgdev.pl --- drivers/soc/qcom/rpmhpd.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index 4c2d2c296790..f20e2a49a669 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -187,6 +187,16 @@ static struct rpmhpd nsp = { .res_name = "nsp.lvl", }; +static struct rpmhpd nsp0 = { + .pd = { .name = "nsp0", }, + .res_name = "nsp0.lvl", +}; + +static struct rpmhpd nsp1 = { + .pd = { .name = "nsp1", }, + .res_name = "nsp1.lvl", +}; + static struct rpmhpd qphy = { .pd = { .name = "qphy", }, .res_name = "qphy.lvl", @@ -212,6 +222,29 @@ static const struct rpmhpd_desc sa8540p_desc = { .num_pds = ARRAY_SIZE(sa8540p_rpmhpds), }; +/* SA8775P RPMH power domains */ +static struct rpmhpd *sa8775p_rpmhpds[] = { + [SA8775P_CX] = &cx, + [SA8775P_CX_AO] = &cx_ao, + [SA8775P_EBI] = &ebi, + [SA8775P_GFX] = &gfx, + [SA8775P_LCX] = &lcx, + [SA8775P_LMX] = &lmx, + [SA8775P_MMCX] = &mmcx, + [SA8775P_MMCX_AO] = &mmcx_ao, + [SA8775P_MXC] = &mxc, + [SA8775P_MXC_AO] = &mxc_ao, + [SA8775P_MX] = &mx, + [SA8775P_MX_AO] = &mx_ao, + [SA8775P_NSP0] = &nsp0, + [SA8775P_NSP1] = &nsp1, +}; + +static const struct rpmhpd_desc sa8775p_desc = { + .rpmhpds = sa8775p_rpmhpds, + .num_pds = ARRAY_SIZE(sa8775p_rpmhpds), +}; + /* SDM670 RPMH powerdomains */ static struct rpmhpd *sdm670_rpmhpds[] = { [SDM670_CX] = &cx_w_mx_parent, @@ -487,6 +520,7 @@ static const struct rpmhpd_desc sc8280xp_desc = { static const struct of_device_id rpmhpd_match_table[] = { { .compatible = "qcom,qdu1000-rpmhpd", .data = &qdu1000_desc }, { .compatible = "qcom,sa8540p-rpmhpd", .data = &sa8540p_desc }, + { .compatible = "qcom,sa8775p-rpmhpd", .data = &sa8775p_desc }, { .compatible = "qcom,sc7180-rpmhpd", .data = &sc7180_desc }, { .compatible = "qcom,sc7280-rpmhpd", .data = &sc7280_desc }, { .compatible = "qcom,sc8180x-rpmhpd", .data = &sc8180x_desc }, -- cgit v1.2.3 From 94214f145bdf91bd5a60657c71ca6df6ec0fd0b6 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Mon, 12 Dec 2022 23:25:47 +0100 Subject: soc: bcm: bcm2835-power: Drop empty platform remove function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A remove callback just returning 0 is equivalent to no remove callback at all. So drop the useless function. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20221212222549.3779846-2-u.kleine-koenig@pengutronix.de Signed-off-by: Florian Fainelli --- drivers/soc/bcm/bcm2835-power.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/bcm/bcm2835-power.c b/drivers/soc/bcm/bcm2835-power.c index 5bcd047768b6..bf51f03f77d6 100644 --- a/drivers/soc/bcm/bcm2835-power.c +++ b/drivers/soc/bcm/bcm2835-power.c @@ -701,14 +701,8 @@ fail: return ret; } -static int bcm2835_power_remove(struct platform_device *pdev) -{ - return 0; -} - static struct platform_driver bcm2835_power_driver = { .probe = bcm2835_power_probe, - .remove = bcm2835_power_remove, .driver = { .name = "bcm2835-power", }, -- cgit v1.2.3 From d45fb976f46600554e2db02ce5d16d1dff84d106 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 9 Jan 2023 20:20:04 -0800 Subject: soc: qcom: ramp_controller: Make things static The five msm8976_cfg_* objects ought to be static, as reported by LKP and sparse, fix this. drivers/soc/qcom/ramp_controller.c:235:27: sparse: sparse: symbol 'msm8976_cfg_dfs_sid' was not declared. Should it be static? drivers/soc/qcom/ramp_controller.c:246:27: sparse: sparse: symbol 'msm8976_cfg_link_sid' was not declared. Should it be static? drivers/soc/qcom/ramp_controller.c:250:27: sparse: sparse: symbol 'msm8976_cfg_lmh_sid' was not declared. Should it be static? drivers/soc/qcom/ramp_controller.c:256:27: sparse: sparse: symbol 'msm8976_cfg_ramp_en' was not declared. Should it be static? drivers/soc/qcom/ramp_controller.c:262:27: sparse: sparse: symbol 'msm8976_cfg_ramp_dis' was not declared. Should it be static? Fixes: a723c95fa137 ("soc: qcom: Add Qualcomm Ramp Controller driver") Reported-by: kernel test robot Signed-off-by: Bjorn Andersson Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230110042004.2378444-1-quic_bjorande@quicinc.com --- drivers/soc/qcom/ramp_controller.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/ramp_controller.c b/drivers/soc/qcom/ramp_controller.c index 93652b07e812..dc74d2a19de2 100644 --- a/drivers/soc/qcom/ramp_controller.c +++ b/drivers/soc/qcom/ramp_controller.c @@ -232,7 +232,7 @@ static const struct regmap_config qrc_regmap_config = { .fast_io = true, }; -const struct reg_sequence msm8976_cfg_dfs_sid[] = { +static const struct reg_sequence msm8976_cfg_dfs_sid[] = { { 0x10, 0xfefebff7 }, { 0x14, 0xfdff7fef }, { 0x18, 0xfbffdefb }, @@ -243,23 +243,23 @@ const struct reg_sequence msm8976_cfg_dfs_sid[] = { { 0x2c, 0x8102 } }; -const struct reg_sequence msm8976_cfg_link_sid[] = { +static const struct reg_sequence msm8976_cfg_link_sid[] = { { 0x40, 0xfc987 } }; -const struct reg_sequence msm8976_cfg_lmh_sid[] = { +static const struct reg_sequence msm8976_cfg_lmh_sid[] = { { 0x30, 0x77706db }, { 0x34, 0x5550249 }, { 0x38, 0x111 } }; -const struct reg_sequence msm8976_cfg_ramp_en[] = { +static const struct reg_sequence msm8976_cfg_ramp_en[] = { { 0x50, 0x800 }, /* pre_en */ { 0x50, 0xc00 }, /* en */ { 0x50, 0x400 } /* post_en */ }; -const struct reg_sequence msm8976_cfg_ramp_dis[] = { +static const struct reg_sequence msm8976_cfg_ramp_dis[] = { { 0x50, 0x0 } }; -- cgit v1.2.3 From e656cd0bcf3d2ba2eceac82b44714bf355428ec4 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Mon, 9 Jan 2023 14:05:22 +0100 Subject: soc: qcom: rmtfs: Optionally map RMTFS to more VMs Some SoCs require that RMTFS is also mapped to the NAV VM. Trying to power on the modem without that results in the whole platform crashing and forces a hard reboot within about 2 seconds. Add support for mapping the region to additional VMs, such as NAV to open a path towards enabling modem on such platforms. Signed-off-by: Loic Poulain [Konrad: reword, make conditional and flexible, add a define for NAV VMID] Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230109130523.298971-2-konrad.dybcio@linaro.org --- drivers/soc/qcom/rmtfs_mem.c | 29 ++++++++++++++++++++++------- include/linux/qcom_scm.h | 1 + 2 files changed, 23 insertions(+), 7 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/rmtfs_mem.c b/drivers/soc/qcom/rmtfs_mem.c index 0feaae357821..9d59ad509a5c 100644 --- a/drivers/soc/qcom/rmtfs_mem.c +++ b/drivers/soc/qcom/rmtfs_mem.c @@ -17,6 +17,7 @@ #include #define QCOM_RMTFS_MEM_DEV_MAX (MINORMASK + 1) +#define NUM_MAX_VMIDS 2 static dev_t qcom_rmtfs_mem_major; @@ -171,12 +172,12 @@ static void qcom_rmtfs_mem_release_device(struct device *dev) static int qcom_rmtfs_mem_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; - struct qcom_scm_vmperm perms[2]; + struct qcom_scm_vmperm perms[NUM_MAX_VMIDS + 1]; struct reserved_mem *rmem; struct qcom_rmtfs_mem *rmtfs_mem; u32 client_id; - u32 vmid; - int ret; + u32 num_vmids, vmid[NUM_MAX_VMIDS]; + int ret, i; rmem = of_reserved_mem_lookup(node); if (!rmem) { @@ -226,7 +227,18 @@ static int qcom_rmtfs_mem_probe(struct platform_device *pdev) goto put_device; } - ret = of_property_read_u32(node, "qcom,vmid", &vmid); + num_vmids = of_property_count_u32_elems(node, "qcom,vmid"); + if (num_vmids < 0) { + dev_err(&pdev->dev, "failed to count qcom,vmid elements: %d\n", ret); + goto remove_cdev; + } else if (num_vmids > NUM_MAX_VMIDS) { + dev_warn(&pdev->dev, + "too many VMIDs (%d) specified! Only mapping first %d entries\n", + num_vmids, NUM_MAX_VMIDS); + num_vmids = NUM_MAX_VMIDS; + } + + ret = of_property_read_u32_array(node, "qcom,vmid", vmid, num_vmids); if (ret < 0 && ret != -EINVAL) { dev_err(&pdev->dev, "failed to parse qcom,vmid\n"); goto remove_cdev; @@ -238,12 +250,15 @@ static int qcom_rmtfs_mem_probe(struct platform_device *pdev) perms[0].vmid = QCOM_SCM_VMID_HLOS; perms[0].perm = QCOM_SCM_PERM_RW; - perms[1].vmid = vmid; - perms[1].perm = QCOM_SCM_PERM_RW; + + for (i = 0; i < num_vmids; i++) { + perms[i + 1].vmid = vmid[i]; + perms[i + 1].perm = QCOM_SCM_PERM_RW; + } rmtfs_mem->perms = BIT(QCOM_SCM_VMID_HLOS); ret = qcom_scm_assign_mem(rmtfs_mem->addr, rmtfs_mem->size, - &rmtfs_mem->perms, perms, 2); + &rmtfs_mem->perms, perms, num_vmids + 1); if (ret < 0) { dev_err(&pdev->dev, "assign memory failed\n"); goto remove_cdev; diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index f8335644a01a..150b72edb879 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -55,6 +55,7 @@ enum qcom_scm_ice_cipher { #define QCOM_SCM_VMID_MSS_MSA 0xF #define QCOM_SCM_VMID_WLAN 0x18 #define QCOM_SCM_VMID_WLAN_CE 0x19 +#define QCOM_SCM_VMID_NAV 0x2B #define QCOM_SCM_PERM_READ 0x4 #define QCOM_SCM_PERM_WRITE 0x2 #define QCOM_SCM_PERM_EXEC 0x1 -- cgit v1.2.3 From 73b7d7f2dcf4f729028deec3f5e434af19270fda Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 8 Dec 2022 02:41:27 -0600 Subject: soc: sunxi: sram: Only iterate over SRAM children Now that a regulators child is accepted by the controller binding, the debugfs show routine must be explicitly limited to mmio-sram children. Acked-by: Jernej Skrabec Signed-off-by: Samuel Holland Link: https://lore.kernel.org/r/20221208084127.17443-5-samuel@sholland.org Signed-off-by: Jernej Skrabec --- drivers/soc/sunxi/sunxi_sram.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c index 92f9186c1c42..f09918c59042 100644 --- a/drivers/soc/sunxi/sunxi_sram.c +++ b/drivers/soc/sunxi/sunxi_sram.c @@ -120,6 +120,9 @@ static int sunxi_sram_show(struct seq_file *s, void *data) seq_puts(s, "--------------------\n\n"); for_each_child_of_node(sram_dev->of_node, sram_node) { + if (!of_device_is_compatible(sram_node, "mmio-sram")) + continue; + sram_addr_p = of_get_address(sram_node, 0, NULL, NULL); seq_printf(s, "sram@%08x\n", -- cgit v1.2.3 From 017a7c11a8a29e266aa40c6d1bf2ba83f880f719 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 4 Jan 2023 12:53:45 +0100 Subject: soc: qcom: socinfo: Fix soc_id order The soc_id array is mostly ordered by the numeric "msm-id" defined in qcom,ids.h but some recent entries were added at the wrong place. While it does not make a functional difference it does make it harder to regenerate the entire array after adding a bunch of new IDs. Fixes: de320c07da3d ("soc: qcom: socinfo: Add MSM8956/76 SoC IDs to the soc_id table") Fixes: 147f6534b8ff ("soc: qcom: socinfo: Add SM8550 ID") Signed-off-by: Stephan Gerhold Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230104115348.25046-2-stephan@gerhold.net --- drivers/soc/qcom/socinfo.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 10efdbcfdf05..7258527816b0 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -257,8 +257,6 @@ static const struct soc_id soc_id[] = { { qcom_board_id(MSM8926) }, { qcom_board_id(MSM8326) }, { qcom_board_id(MSM8916) }, - { qcom_board_id(MSM8956) }, - { qcom_board_id(MSM8976) }, { qcom_board_id(MSM8994) }, { qcom_board_id_named(APQ8074PRO_AA, "APQ8074PRO-AA") }, { qcom_board_id_named(APQ8074PRO_AB, "APQ8074PRO-AB") }, @@ -290,6 +288,8 @@ static const struct soc_id soc_id[] = { { qcom_board_id(MSM8616) }, { qcom_board_id(MSM8992) }, { qcom_board_id(APQ8094) }, + { qcom_board_id(MSM8956) }, + { qcom_board_id(MSM8976) }, { qcom_board_id(MDM9607) }, { qcom_board_id(APQ8096) }, { qcom_board_id(MSM8998) }, @@ -348,7 +348,6 @@ static const struct soc_id soc_id[] = { { qcom_board_id(IPQ6005) }, { qcom_board_id(QRB5165) }, { qcom_board_id(SM8450) }, - { qcom_board_id(SM8550) }, { qcom_board_id(SM7225) }, { qcom_board_id(SA8295P) }, { qcom_board_id(SA8540P) }, @@ -359,6 +358,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(SC7280) }, { qcom_board_id(SC7180P) }, { qcom_board_id(SM6375) }, + { qcom_board_id(SM8550) }, { qcom_board_id(QRU1000) }, { qcom_board_id(QDU1000) }, { qcom_board_id(QDU1010) }, -- cgit v1.2.3 From 40017cebb111eed65bddfa993df7b0636be98de8 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 4 Jan 2023 12:53:48 +0100 Subject: soc: qcom: socinfo: Add a bunch of older SoCs Add the new SoCs added in qcom,ids.h to the soc_id array so they show up correctly in the socinfo sysfs. Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230104115348.25046-5-stephan@gerhold.net --- drivers/soc/qcom/socinfo.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 7258527816b0..3b970a80f3aa 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -221,36 +221,62 @@ struct soc_id { }; static const struct soc_id soc_id[] = { + { qcom_board_id(MSM8260) }, + { qcom_board_id(MSM8660) }, + { qcom_board_id(APQ8060) }, { qcom_board_id(MSM8960) }, { qcom_board_id(APQ8064) }, + { qcom_board_id(MSM8930) }, + { qcom_board_id(MSM8630) }, + { qcom_board_id(MSM8230) }, + { qcom_board_id(APQ8030) }, + { qcom_board_id(MSM8627) }, + { qcom_board_id(MSM8227) }, { qcom_board_id(MSM8660A) }, { qcom_board_id(MSM8260A) }, { qcom_board_id(APQ8060A) }, { qcom_board_id(MSM8974) }, + { qcom_board_id(MSM8225) }, + { qcom_board_id(MSM8625) }, { qcom_board_id(MPQ8064) }, { qcom_board_id(MSM8960AB) }, { qcom_board_id(APQ8060AB) }, { qcom_board_id(MSM8260AB) }, { qcom_board_id(MSM8660AB) }, + { qcom_board_id(MSM8930AA) }, + { qcom_board_id(MSM8630AA) }, + { qcom_board_id(MSM8230AA) }, { qcom_board_id(MSM8626) }, { qcom_board_id(MSM8610) }, { qcom_board_id(APQ8064AB) }, + { qcom_board_id(MSM8930AB) }, + { qcom_board_id(MSM8630AB) }, + { qcom_board_id(MSM8230AB) }, + { qcom_board_id(APQ8030AB) }, { qcom_board_id(MSM8226) }, { qcom_board_id(MSM8526) }, + { qcom_board_id(APQ8030AA) }, { qcom_board_id(MSM8110) }, { qcom_board_id(MSM8210) }, { qcom_board_id(MSM8810) }, { qcom_board_id(MSM8212) }, { qcom_board_id(MSM8612) }, { qcom_board_id(MSM8112) }, + { qcom_board_id(MSM8125) }, { qcom_board_id(MSM8225Q) }, { qcom_board_id(MSM8625Q) }, { qcom_board_id(MSM8125Q) }, { qcom_board_id(APQ8064AA) }, { qcom_board_id(APQ8084) }, + { qcom_board_id(MSM8130) }, + { qcom_board_id(MSM8130AA) }, + { qcom_board_id(MSM8130AB) }, + { qcom_board_id(MSM8627AA) }, + { qcom_board_id(MSM8227AA) }, { qcom_board_id(APQ8074) }, { qcom_board_id(MSM8274) }, { qcom_board_id(MSM8674) }, + { qcom_board_id(MDM9635) }, { qcom_board_id_named(MSM8974PRO_AC, "MSM8974PRO-AC") }, { qcom_board_id(MSM8126) }, { qcom_board_id(APQ8026) }, @@ -278,34 +304,72 @@ static const struct soc_id soc_id[] = { { qcom_board_id(MSM8510) }, { qcom_board_id(MSM8512) }, { qcom_board_id(MSM8936) }, + { qcom_board_id(MDM9640) }, { qcom_board_id(MSM8939) }, { qcom_board_id(APQ8036) }, { qcom_board_id(APQ8039) }, + { qcom_board_id(MSM8236) }, + { qcom_board_id(MSM8636) }, + { qcom_board_id(MSM8909) }, { qcom_board_id(MSM8996) }, { qcom_board_id(APQ8016) }, { qcom_board_id(MSM8216) }, { qcom_board_id(MSM8116) }, { qcom_board_id(MSM8616) }, { qcom_board_id(MSM8992) }, + { qcom_board_id(APQ8092) }, { qcom_board_id(APQ8094) }, + { qcom_board_id(MSM8209) }, + { qcom_board_id(MSM8208) }, + { qcom_board_id(MDM9209) }, + { qcom_board_id(MDM9309) }, + { qcom_board_id(MDM9609) }, + { qcom_board_id(MSM8239) }, + { qcom_board_id(MSM8952) }, + { qcom_board_id(APQ8009) }, { qcom_board_id(MSM8956) }, + { qcom_board_id(MSM8929) }, + { qcom_board_id(MSM8629) }, + { qcom_board_id(MSM8229) }, + { qcom_board_id(APQ8029) }, + { qcom_board_id(APQ8056) }, + { qcom_board_id(MSM8609) }, + { qcom_board_id(APQ8076) }, { qcom_board_id(MSM8976) }, + { qcom_board_id(MDM9650) }, + { qcom_board_id(MDM9655) }, + { qcom_board_id(MDM9250) }, + { qcom_board_id(MDM9255) }, + { qcom_board_id(MDM9350) }, + { qcom_board_id(APQ8052) }, { qcom_board_id(MDM9607) }, { qcom_board_id(APQ8096) }, { qcom_board_id(MSM8998) }, { qcom_board_id(MSM8953) }, + { qcom_board_id(MSM8937) }, + { qcom_board_id(APQ8037) }, { qcom_board_id(MDM8207) }, { qcom_board_id(MDM9207) }, { qcom_board_id(MDM9307) }, { qcom_board_id(MDM9628) }, + { qcom_board_id(MSM8909W) }, + { qcom_board_id(APQ8009W) }, + { qcom_board_id(MSM8996L) }, + { qcom_board_id(MSM8917) }, { qcom_board_id(APQ8053) }, { qcom_board_id(MSM8996SG) }, + { qcom_board_id(APQ8017) }, + { qcom_board_id(MSM8217) }, + { qcom_board_id(MSM8617) }, { qcom_board_id(MSM8996AU) }, { qcom_board_id(APQ8096AU) }, { qcom_board_id(APQ8096SG) }, + { qcom_board_id(MSM8940) }, + { qcom_board_id(SDX201) }, { qcom_board_id(SDM660) }, { qcom_board_id(SDM630) }, { qcom_board_id(APQ8098) }, + { qcom_board_id(MSM8920) }, { qcom_board_id(SDM845) }, { qcom_board_id(MDM9206) }, { qcom_board_id(IPQ8074) }, @@ -313,6 +377,8 @@ static const struct soc_id soc_id[] = { { qcom_board_id(SDM658) }, { qcom_board_id(SDA658) }, { qcom_board_id(SDA630) }, + { qcom_board_id(MSM8905) }, + { qcom_board_id(SDX202) }, { qcom_board_id(SDM450) }, { qcom_board_id(SM8150) }, { qcom_board_id(SDA845) }, @@ -324,10 +390,15 @@ static const struct soc_id soc_id[] = { { qcom_board_id(SDM632) }, { qcom_board_id(SDA632) }, { qcom_board_id(SDA450) }, + { qcom_board_id(SDM439) }, + { qcom_board_id(SDM429) }, { qcom_board_id(SM8250) }, { qcom_board_id(SA8155) }, + { qcom_board_id(SDA439) }, + { qcom_board_id(SDA429) }, { qcom_board_id(IPQ8070) }, { qcom_board_id(IPQ8071) }, + { qcom_board_id(QM215) }, { qcom_board_id(IPQ8072A) }, { qcom_board_id(IPQ8074A) }, { qcom_board_id(IPQ8076A) }, @@ -337,11 +408,14 @@ static const struct soc_id soc_id[] = { { qcom_board_id(IPQ8071A) }, { qcom_board_id(IPQ6018) }, { qcom_board_id(IPQ6028) }, + { qcom_board_id(SDM429W) }, { qcom_board_id(SM4250) }, { qcom_board_id(IPQ6000) }, { qcom_board_id(IPQ6010) }, { qcom_board_id(SC7180) }, { qcom_board_id(SM6350) }, + { qcom_board_id(QCM2150) }, + { qcom_board_id(SDA429W) }, { qcom_board_id(SM8350) }, { qcom_board_id(SM6115) }, { qcom_board_id(SC8280XP) }, -- cgit v1.2.3 From a36489778ba8f7eb98c3e9fca2d300090bf1ffcd Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 13 Jan 2023 16:22:31 +0100 Subject: Revert "soc: qcom: rpmpd: Add SM4250 support" SM4250 and SM6115 use a shared device tree and the RPMPDs are identical. There's no need for a separate entry, so remove it. This reverts commit 5b617b1b10c1c6a4365d8f956032e95c53b8e388. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230113152232.2624545-1-konrad.dybcio@linaro.org --- drivers/soc/qcom/rpmpd.c | 18 ------------------ 1 file changed, 18 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index f0db6a10cf4e..337b1ad1cd3b 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -471,23 +471,6 @@ static const struct rpmpd_desc qcm2290_desc = { .max_state = RPM_SMD_LEVEL_TURBO_NO_CPR, }; -static struct rpmpd *sm4250_rpmpds[] = { - [SM4250_VDDCX] = &sm6115_vddcx, - [SM4250_VDDCX_AO] = &sm6115_vddcx_ao, - [SM4250_VDDCX_VFL] = &sm6115_vddcx_vfl, - [SM4250_VDDMX] = &sm6115_vddmx, - [SM4250_VDDMX_AO] = &sm6115_vddmx_ao, - [SM4250_VDDMX_VFL] = &sm6115_vddmx_vfl, - [SM4250_VDD_LPI_CX] = &sm6115_vdd_lpi_cx, - [SM4250_VDD_LPI_MX] = &sm6115_vdd_lpi_mx, -}; - -static const struct rpmpd_desc sm4250_desc = { - .rpmpds = sm4250_rpmpds, - .num_pds = ARRAY_SIZE(sm4250_rpmpds), - .max_state = RPM_SMD_LEVEL_TURBO_NO_CPR, -}; - static const struct of_device_id rpmpd_match_table[] = { { .compatible = "qcom,mdm9607-rpmpd", .data = &mdm9607_desc }, { .compatible = "qcom,msm8226-rpmpd", .data = &msm8226_desc }, @@ -502,7 +485,6 @@ static const struct of_device_id rpmpd_match_table[] = { { .compatible = "qcom,qcm2290-rpmpd", .data = &qcm2290_desc }, { .compatible = "qcom,qcs404-rpmpd", .data = &qcs404_desc }, { .compatible = "qcom,sdm660-rpmpd", .data = &sdm660_desc }, - { .compatible = "qcom,sm4250-rpmpd", .data = &sm4250_desc }, { .compatible = "qcom,sm6115-rpmpd", .data = &sm6115_desc }, { .compatible = "qcom,sm6125-rpmpd", .data = &sm6125_desc }, { .compatible = "qcom,sm6375-rpmpd", .data = &sm6375_desc }, -- cgit v1.2.3 From e610e81464e4e52645a0f5d259b8a9e3632db6ff Mon Sep 17 00:00:00 2001 From: "Garmin.Chang" Date: Fri, 23 Dec 2022 16:05:53 +0800 Subject: soc: mediatek: pm-domains: Add support for mt8188 Add domain control data including bus protection data size change due to more protection steps in mt8188. Signed-off-by: Garmin.Chang Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221223080553.9397-3-Garmin.Chang@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mt8188-pm-domains.h | 623 +++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-pm-domains.c | 5 + include/linux/soc/mediatek/infracfg.h | 121 ++++++ 3 files changed, 749 insertions(+) create mode 100644 drivers/soc/mediatek/mt8188-pm-domains.h (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mt8188-pm-domains.h b/drivers/soc/mediatek/mt8188-pm-domains.h new file mode 100644 index 000000000000..0692cb444ed0 --- /dev/null +++ b/drivers/soc/mediatek/mt8188-pm-domains.h @@ -0,0 +1,623 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang + */ + +#ifndef __SOC_MEDIATEK_MT8188_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT8188_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT8188 power domain support + */ + +static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { + [MT8188_POWER_DOMAIN_MFG0] = { + .name = "mfg0", + .sta_mask = BIT(1), + .ctl_offs = 0x300, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, + }, + [MT8188_POWER_DOMAIN_MFG1] = { + .name = "mfg1", + .sta_mask = BIT(2), + .ctl_offs = 0x304, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP1, + MT8188_TOP_AXI_PROT_EN_SET, + MT8188_TOP_AXI_PROT_EN_CLR, + MT8188_TOP_AXI_PROT_EN_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3, + MT8188_TOP_AXI_PROT_EN_1_SET, + MT8188_TOP_AXI_PROT_EN_1_CLR, + MT8188_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP5, + MT8188_TOP_AXI_PROT_EN_SET, + MT8188_TOP_AXI_PROT_EN_CLR, + MT8188_TOP_AXI_PROT_EN_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, + }, + [MT8188_POWER_DOMAIN_MFG2] = { + .name = "mfg2", + .sta_mask = BIT(3), + .ctl_offs = 0x308, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8188_POWER_DOMAIN_MFG3] = { + .name = "mfg3", + .sta_mask = BIT(4), + .ctl_offs = 0x30C, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8188_POWER_DOMAIN_MFG4] = { + .name = "mfg4", + .sta_mask = BIT(5), + .ctl_offs = 0x310, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8188_POWER_DOMAIN_PEXTP_MAC_P0] = { + .name = "pextp_mac_p0", + .sta_mask = BIT(10), + .ctl_offs = 0x324, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1, + MT8188_TOP_AXI_PROT_EN_SET, + MT8188_TOP_AXI_PROT_EN_CLR, + MT8188_TOP_AXI_PROT_EN_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8188_POWER_DOMAIN_PEXTP_PHY_TOP] = { + .name = "pextp_phy_top", + .sta_mask = BIT(12), + .ctl_offs = 0x328, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8188_POWER_DOMAIN_CSIRX_TOP] = { + .name = "pextp_csirx_top", + .sta_mask = BIT(17), + .ctl_offs = 0x3C4, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8188_POWER_DOMAIN_ETHER] = { + .name = "ether", + .sta_mask = BIT(1), + .ctl_offs = 0x338, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8188_POWER_DOMAIN_HDMI_TX] = { + .name = "hdmi_tx", + .sta_mask = BIT(18), + .ctl_offs = 0x37C, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8188_POWER_DOMAIN_ADSP_AO] = { + .name = "adsp_ao", + .sta_mask = BIT(10), + .ctl_offs = 0x35C, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + }, + .caps = MTK_SCPD_ALWAYS_ON, + }, + [MT8188_POWER_DOMAIN_ADSP_INFRA] = { + .name = "adsp_infra", + .sta_mask = BIT(9), + .ctl_offs = 0x358, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + }, + .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ALWAYS_ON, + }, + [MT8188_POWER_DOMAIN_ADSP] = { + .name = "adsp", + .sta_mask = BIT(8), + .ctl_offs = 0x354, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8188_POWER_DOMAIN_AUDIO] = { + .name = "audio", + .sta_mask = BIT(6), + .ctl_offs = 0x34C, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8188_POWER_DOMAIN_AUDIO_ASRC] = { + .name = "audio_asrc", + .sta_mask = BIT(7), + .ctl_offs = 0x350, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8188_POWER_DOMAIN_VPPSYS0] = { + .name = "vppsys0", + .sta_mask = BIT(11), + .ctl_offs = 0x360, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1, + MT8188_TOP_AXI_PROT_EN_SET, + MT8188_TOP_AXI_PROT_EN_CLR, + MT8188_TOP_AXI_PROT_EN_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3, + MT8188_TOP_AXI_PROT_EN_SET, + MT8188_TOP_AXI_PROT_EN_CLR, + MT8188_TOP_AXI_PROT_EN_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), + }, + }, + [MT8188_POWER_DOMAIN_VDOSYS0] = { + .name = "vdosys0", + .sta_mask = BIT(13), + .ctl_offs = 0x368, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2, + MT8188_TOP_AXI_PROT_EN_SET, + MT8188_TOP_AXI_PROT_EN_CLR, + MT8188_TOP_AXI_PROT_EN_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), + }, + }, + [MT8188_POWER_DOMAIN_VDOSYS1] = { + .name = "vdosys1", + .sta_mask = BIT(14), + .ctl_offs = 0x36C, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + }, + }, + [MT8188_POWER_DOMAIN_DP_TX] = { + .name = "dp_tx", + .sta_mask = BIT(16), + .ctl_offs = 0x374, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8188_POWER_DOMAIN_EDP_TX] = { + .name = "edp_tx", + .sta_mask = BIT(17), + .ctl_offs = 0x378, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8188_POWER_DOMAIN_VPPSYS1] = { + .name = "vppsys1", + .sta_mask = BIT(12), + .ctl_offs = 0x364, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + }, + }, + [MT8188_POWER_DOMAIN_WPE] = { + .name = "wpe", + .sta_mask = BIT(15), + .ctl_offs = 0x370, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8188_POWER_DOMAIN_VDEC0] = { + .name = "vdec0", + .sta_mask = BIT(19), + .ctl_offs = 0x380, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8188_POWER_DOMAIN_VDEC1] = { + .name = "vdec1", + .sta_mask = BIT(20), + .ctl_offs = 0x384, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8188_POWER_DOMAIN_VENC] = { + .name = "venc", + .sta_mask = BIT(22), + .ctl_offs = 0x38C, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8188_POWER_DOMAIN_IMG_VCORE] = { + .name = "vcore", + .sta_mask = BIT(28), + .ctl_offs = 0x3A4, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, + }, + [MT8188_POWER_DOMAIN_IMG_MAIN] = { + .name = "img_main", + .sta_mask = BIT(29), + .ctl_offs = 0x3A8, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8188_POWER_DOMAIN_DIP] = { + .name = "dip", + .sta_mask = BIT(30), + .ctl_offs = 0x3AC, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8188_POWER_DOMAIN_IPE] = { + .name = "ipe", + .sta_mask = BIT(31), + .ctl_offs = 0x3B0, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8188_POWER_DOMAIN_CAM_VCORE] = { + .name = "cam_vcore", + .sta_mask = BIT(27), + .ctl_offs = 0x3A0, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3, + MT8188_TOP_AXI_PROT_EN_1_SET, + MT8188_TOP_AXI_PROT_EN_1_CLR, + MT8188_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4, + MT8188_TOP_AXI_PROT_EN_MM_SET, + MT8188_TOP_AXI_PROT_EN_MM_CLR, + MT8188_TOP_AXI_PROT_EN_MM_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, + }, + [MT8188_POWER_DOMAIN_CAM_MAIN] = { + .name = "cam_main", + .sta_mask = BIT(24), + .ctl_offs = 0x394, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3, + MT8188_TOP_AXI_PROT_EN_MM_2_SET, + MT8188_TOP_AXI_PROT_EN_MM_2_CLR, + MT8188_TOP_AXI_PROT_EN_MM_2_STA), + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4, + MT8188_TOP_AXI_PROT_EN_2_SET, + MT8188_TOP_AXI_PROT_EN_2_CLR, + MT8188_TOP_AXI_PROT_EN_2_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8188_POWER_DOMAIN_CAM_SUBA] = { + .name = "cam_suba", + .sta_mask = BIT(25), + .ctl_offs = 0x398, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8188_POWER_DOMAIN_CAM_SUBB] = { + .name = "cam_subb", + .sta_mask = BIT(26), + .ctl_offs = 0x39C, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, +}; + +static const struct scpsys_soc_data mt8188_scpsys_data = { + .domains_data = scpsys_domain_data_mt8188, + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8188), +}; + +#endif /* __SOC_MEDIATEK_MT8188_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 474b272f9b02..ea3878bf4387 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -21,6 +21,7 @@ #include "mt8173-pm-domains.h" #include "mt8183-pm-domains.h" #include "mt8186-pm-domains.h" +#include "mt8188-pm-domains.h" #include "mt8192-pm-domains.h" #include "mt8195-pm-domains.h" @@ -579,6 +580,10 @@ static const struct of_device_id scpsys_of_match[] = { .compatible = "mediatek,mt8186-power-controller", .data = &mt8186_scpsys_data, }, + { + .compatible = "mediatek,mt8188-power-controller", + .data = &mt8188_scpsys_data, + }, { .compatible = "mediatek,mt8192-power-controller", .data = &mt8192_scpsys_data, diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h index 50804ac748bd..07f67b3d8e97 100644 --- a/include/linux/soc/mediatek/infracfg.h +++ b/include/linux/soc/mediatek/infracfg.h @@ -140,6 +140,127 @@ #define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13) #define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21) +#define MT8188_TOP_AXI_PROT_EN_SET 0x2A0 +#define MT8188_TOP_AXI_PROT_EN_CLR 0x2A4 +#define MT8188_TOP_AXI_PROT_EN_STA 0x228 +#define MT8188_TOP_AXI_PROT_EN_1_SET 0x2A8 +#define MT8188_TOP_AXI_PROT_EN_1_CLR 0x2AC +#define MT8188_TOP_AXI_PROT_EN_1_STA 0x258 +#define MT8188_TOP_AXI_PROT_EN_2_SET 0x714 +#define MT8188_TOP_AXI_PROT_EN_2_CLR 0x718 +#define MT8188_TOP_AXI_PROT_EN_2_STA 0x724 + +#define MT8188_TOP_AXI_PROT_EN_MM_SET 0x2D4 +#define MT8188_TOP_AXI_PROT_EN_MM_CLR 0x2D8 +#define MT8188_TOP_AXI_PROT_EN_MM_STA 0x2EC +#define MT8188_TOP_AXI_PROT_EN_MM_2_SET 0xDCC +#define MT8188_TOP_AXI_PROT_EN_MM_2_CLR 0xDD0 +#define MT8188_TOP_AXI_PROT_EN_MM_2_STA 0xDD8 + +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET 0xB84 +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR 0xB88 +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA 0xB90 +#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xBCC +#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xBD0 +#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA 0xBD8 + +#define MT8188_TOP_AXI_PROT_EN_MFG1_STEP1 BIT(11) +#define MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2 BIT(7) +#define MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3 BIT(19) +#define MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4 BIT(5) +#define MT8188_TOP_AXI_PROT_EN_MFG1_STEP5 GENMASK(22, 21) +#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6 BIT(17) + +#define MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1 BIT(2) +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2 (BIT(8) | BIT(18) | BIT(30)) +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1 BIT(24) +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1 BIT(20) +#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1 GENMASK(31, 29) +#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2 (GENMASK(4, 3) | BIT(28)) +#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1 (GENMASK(16, 14) | BIT(23) | \ + BIT(27)) +#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2 (GENMASK(19, 17) | GENMASK(26, 25)) +#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1 GENMASK(11, 8) +#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2 GENMASK(22, 21) +#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1 BIT(20) +#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2 BIT(12) +#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1 BIT(24) +#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2 BIT(13) + +#define MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1 BIT(10) +#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2 GENMASK(9, 8) +#define MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3 BIT(23) +#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4 (BIT(1) | BIT(4) | BIT(11)) +#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5 (BIT(20)) +#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1 (GENMASK(18, 17) | GENMASK(21, 20)) +#define MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2 BIT(6) +#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3 BIT(21) +#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1 GENMASK(31, 30) +#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2 BIT(22) +#define MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3 BIT(10) +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1 BIT(23) +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1 BIT(22) + +#define MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1 GENMASK(6, 5) +#define MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2 BIT(23) +#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3 BIT(18) +#define MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1 BIT(23) +#define MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2 BIT(21) +#define MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1 BIT(13) +#define MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2 BIT(13) +#define MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1 BIT(14) +#define MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2 BIT(29) +#define MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1 (BIT(9) | BIT(11)) +#define MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2 BIT(26) +#define MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3 BIT(2) +#define MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1 (BIT(1) | BIT(3)) +#define MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2 BIT(25) +#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3 BIT(16) +#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1 GENMASK(27, 26) +#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2 GENMASK(25, 24) +#define MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1 (BIT(2) | BIT(4)) +#define MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2 BIT(0) +#define MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3 BIT(22) +#define MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4 BIT(24) +#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5 BIT(17) +#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1 GENMASK(31, 30) +#define MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2 BIT(2) +#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3 GENMASK(29, 28) +#define MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4 BIT(1) + +#define MT8188_SMI_COMMON_CLAMP_EN_STA 0x3C0 +#define MT8188_SMI_COMMON_CLAMP_EN_SET 0x3C4 +#define MT8188_SMI_COMMON_CLAMP_EN_CLR 0x3C8 + +#define MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VDO0 GENMASK(3, 1) +#define MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VPP1 GENMASK(2, 1) +#define MT8188_SMI_COMMON_SMI_CLAMP_IPE_TO_VPP1 BIT(0) + +#define MT8188_SMI_COMMON_SMI_CLAMP_CAM_SUBA_TO_VPP0 GENMASK(3, 2) +#define MT8188_SMI_COMMON_SMI_CLAMP_CAM_SUBB_TO_VDO0 GENMASK(3, 2) + +#define MT8188_SMI_LARB10_RESET_ADDR 0xC +#define MT8188_SMI_LARB11A_RESET_ADDR 0xC +#define MT8188_SMI_LARB11C_RESET_ADDR 0xC +#define MT8188_SMI_LARB12_RESET_ADDR 0xC +#define MT8188_SMI_LARB11B_RESET_ADDR 0xC +#define MT8188_SMI_LARB15_RESET_ADDR 0xC +#define MT8188_SMI_LARB16B_RESET_ADDR 0xA0 +#define MT8188_SMI_LARB17B_RESET_ADDR 0xA0 +#define MT8188_SMI_LARB16A_RESET_ADDR 0xA0 +#define MT8188_SMI_LARB17A_RESET_ADDR 0xA0 + +#define MT8188_SMI_LARB10_RESET BIT(0) +#define MT8188_SMI_LARB11A_RESET BIT(0) +#define MT8188_SMI_LARB11C_RESET BIT(0) +#define MT8188_SMI_LARB12_RESET BIT(8) +#define MT8188_SMI_LARB11B_RESET BIT(0) +#define MT8188_SMI_LARB15_RESET BIT(0) +#define MT8188_SMI_LARB16B_RESET BIT(4) +#define MT8188_SMI_LARB17B_RESET BIT(4) +#define MT8188_SMI_LARB16A_RESET BIT(4) +#define MT8188_SMI_LARB17A_RESET BIT(4) + #define MT8186_TOP_AXI_PROT_EN_SET (0x2A0) #define MT8186_TOP_AXI_PROT_EN_CLR (0x2A4) #define MT8186_TOP_AXI_PROT_EN_STA (0x228) -- cgit v1.2.3 From 1e28f6a35f7adec653dd04240ce971f9de598e16 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Tue, 17 Jan 2023 11:26:39 +0800 Subject: soc: mediatek: pm-domains: Add buck isolation offset and mask to power domain data Add buck isolation offset and mask to power domain data. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230117032640.13504-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-pm-domains.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index 7d3c0c36316c..a5f24c58e35a 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -81,6 +81,8 @@ struct scpsys_bus_prot_data { * @ctl_offs: The offset for main power control register. * @sram_pdn_bits: The mask for sram power control bits. * @sram_pdn_ack_bits: The mask for sram power control acked bits. + * @ext_buck_iso_offs: The offset for external buck isolation + * @ext_buck_iso_mask: The mask for external buck isolation * @caps: The flag for active wake-up action. * @bp_infracfg: bus protection for infracfg subsystem * @bp_smi: bus protection for smi subsystem @@ -91,6 +93,8 @@ struct scpsys_domain_data { int ctl_offs; u32 sram_pdn_bits; u32 sram_pdn_ack_bits; + int ext_buck_iso_offs; + u32 ext_buck_iso_mask; u8 caps; const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA]; const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA]; -- cgit v1.2.3 From 7d1ae5926d3216f823be56b79202711dd0b83cdb Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Tue, 17 Jan 2023 11:26:40 +0800 Subject: soc: mediatek: pm-domains: Add buck isolation setting in power domain In some chipsets, we need to disable EXT_BUCK_ISO before turning on the specific power pm-domains (mtcmos), such as ADSP in MT8192 and CAM_VCORE in MT8188. Add the MTK_SCPD_EXT_BUCK_ISO flag to control the buck isolation setting in the mediatek power domain driver. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230117032640.13504-3-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-pm-domains.c | 8 ++++++++ drivers/soc/mediatek/mtk-pm-domains.h | 1 + 2 files changed, 9 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index ea3878bf4387..354249cc1b12 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -219,6 +219,10 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) if (ret) goto err_reg; + if (pd->data->ext_buck_iso_offs && MTK_SCPD_CAPS(pd, MTK_SCPD_EXT_BUCK_ISO)) + regmap_clear_bits(scpsys->base, pd->data->ext_buck_iso_offs, + pd->data->ext_buck_iso_mask); + /* subsys power on */ regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); @@ -273,6 +277,10 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) if (ret < 0) return ret; + if (pd->data->ext_buck_iso_offs && MTK_SCPD_CAPS(pd, MTK_SCPD_EXT_BUCK_ISO)) + regmap_set_bits(scpsys->base, pd->data->ext_buck_iso_offs, + pd->data->ext_buck_iso_mask); + clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); /* subsys power off */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index a5f24c58e35a..5ec53ee073c4 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -10,6 +10,7 @@ #define MTK_SCPD_DOMAIN_SUPPLY BIT(4) /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */ #define MTK_SCPD_ALWAYS_ON BIT(5) +#define MTK_SCPD_EXT_BUCK_ISO BIT(6) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) #define SPM_VDE_PWR_CON 0x0210 -- cgit v1.2.3 From 08b9a94e8654d402bfd1f5496b077503d69aa2cf Mon Sep 17 00:00:00 2001 From: Walker Chen Date: Thu, 19 Jan 2023 17:44:47 +0800 Subject: soc: starfive: Add StarFive JH71XX pmu driver Add pmu driver for the StarFive JH71XX SoC. As the power domains provider, the Power Management Unit (PMU) is designed for including multiple PM domains that can be used for power gating of selected IP blocks for power saving by reduced leakage current. It accepts software encourage command to switch the power mode of SoC. Signed-off-by: Walker Chen Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Signed-off-by: Conor Dooley --- MAINTAINERS | 13 ++ drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/starfive/Kconfig | 12 ++ drivers/soc/starfive/Makefile | 3 + drivers/soc/starfive/jh71xx_pmu.c | 383 ++++++++++++++++++++++++++++++++++++++ 6 files changed, 413 insertions(+) create mode 100644 drivers/soc/starfive/Kconfig create mode 100644 drivers/soc/starfive/Makefile create mode 100644 drivers/soc/starfive/jh71xx_pmu.c (limited to 'drivers/soc') diff --git a/MAINTAINERS b/MAINTAINERS index f61eb221415b..305246e5d574 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19905,6 +19905,19 @@ F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml F: drivers/reset/reset-starfive-jh7100.c F: include/dt-bindings/reset/starfive-jh7100.h +STARFIVE SOC DRIVERS +M: Conor Dooley +S: Maintained +T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ +F: drivers/soc/starfive/ + +STARFIVE JH71XX PMU CONTROLLER DRIVER +M: Walker Chen +S: Supported +F: Documentation/devicetree/bindings/power/starfive* +F: drivers/soc/starfive/jh71xx_pmu.c +F: include/dt-bindings/power/starfive,jh7110-pmu.h + STATIC BRANCH/CALL M: Peter Zijlstra M: Josh Poimboeuf diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 5dbb09f843f7..81ae4f77974b 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -22,6 +22,7 @@ source "drivers/soc/renesas/Kconfig" source "drivers/soc/rockchip/Kconfig" source "drivers/soc/samsung/Kconfig" source "drivers/soc/sifive/Kconfig" +source "drivers/soc/starfive/Kconfig" source "drivers/soc/sunxi/Kconfig" source "drivers/soc/tegra/Kconfig" source "drivers/soc/ti/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index fff513bd522d..bc7491d9e1ed 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -28,6 +28,7 @@ obj-y += renesas/ obj-y += rockchip/ obj-$(CONFIG_SOC_SAMSUNG) += samsung/ obj-$(CONFIG_SOC_SIFIVE) += sifive/ +obj-$(CONFIG_SOC_STARFIVE) += starfive/ obj-y += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig new file mode 100644 index 000000000000..bdb96dc4c989 --- /dev/null +++ b/drivers/soc/starfive/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0 + +config JH71XX_PMU + bool "Support PMU for StarFive JH71XX Soc" + depends on PM + depends on SOC_STARFIVE || COMPILE_TEST + default SOC_STARFIVE + select PM_GENERIC_DOMAINS + help + Say 'y' here to enable support power domain support. + In order to meet low power requirements, a Power Management Unit (PMU) + is designed for controlling power resources in StarFive JH71XX SoCs. diff --git a/drivers/soc/starfive/Makefile b/drivers/soc/starfive/Makefile new file mode 100644 index 000000000000..13b589d6b5f3 --- /dev/null +++ b/drivers/soc/starfive/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_JH71XX_PMU) += jh71xx_pmu.o diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c new file mode 100644 index 000000000000..7d5f50d71c0d --- /dev/null +++ b/drivers/soc/starfive/jh71xx_pmu.c @@ -0,0 +1,383 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * StarFive JH71XX PMU (Power Management Unit) Controller Driver + * + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* register offset */ +#define JH71XX_PMU_SW_TURN_ON_POWER 0x0C +#define JH71XX_PMU_SW_TURN_OFF_POWER 0x10 +#define JH71XX_PMU_SW_ENCOURAGE 0x44 +#define JH71XX_PMU_TIMER_INT_MASK 0x48 +#define JH71XX_PMU_CURR_POWER_MODE 0x80 +#define JH71XX_PMU_EVENT_STATUS 0x88 +#define JH71XX_PMU_INT_STATUS 0x8C + +/* sw encourage cfg */ +#define JH71XX_PMU_SW_ENCOURAGE_EN_LO 0x05 +#define JH71XX_PMU_SW_ENCOURAGE_EN_HI 0x50 +#define JH71XX_PMU_SW_ENCOURAGE_DIS_LO 0x0A +#define JH71XX_PMU_SW_ENCOURAGE_DIS_HI 0xA0 +#define JH71XX_PMU_SW_ENCOURAGE_ON 0xFF + +/* pmu int status */ +#define JH71XX_PMU_INT_SEQ_DONE BIT(0) +#define JH71XX_PMU_INT_HW_REQ BIT(1) +#define JH71XX_PMU_INT_SW_FAIL GENMASK(3, 2) +#define JH71XX_PMU_INT_HW_FAIL GENMASK(5, 4) +#define JH71XX_PMU_INT_PCH_FAIL GENMASK(8, 6) +#define JH71XX_PMU_INT_ALL_MASK GENMASK(8, 0) + +/* + * The time required for switching power status is based on the time + * to turn on the largest domain's power, which is at microsecond level + */ +#define JH71XX_PMU_TIMEOUT_US 100 + +struct jh71xx_domain_info { + const char * const name; + unsigned int flags; + u8 bit; +}; + +struct jh71xx_pmu_match_data { + const struct jh71xx_domain_info *domain_info; + int num_domains; +}; + +struct jh71xx_pmu { + struct device *dev; + const struct jh71xx_pmu_match_data *match_data; + void __iomem *base; + struct generic_pm_domain **genpd; + struct genpd_onecell_data genpd_data; + int irq; + spinlock_t lock; /* protects pmu reg */ +}; + +struct jh71xx_pmu_dev { + const struct jh71xx_domain_info *domain_info; + struct jh71xx_pmu *pmu; + struct generic_pm_domain genpd; +}; + +static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_on) +{ + struct jh71xx_pmu *pmu = pmd->pmu; + + if (!mask) + return -EINVAL; + + *is_on = readl(pmu->base + JH71XX_PMU_CURR_POWER_MODE) & mask; + + return 0; +} + +static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) +{ + struct jh71xx_pmu *pmu = pmd->pmu; + unsigned long flags; + u32 val; + u32 mode; + u32 encourage_lo; + u32 encourage_hi; + bool is_on; + int ret; + + ret = jh71xx_pmu_get_state(pmd, mask, &is_on); + if (ret) { + dev_dbg(pmu->dev, "unable to get current state for %s\n", + pmd->genpd.name); + return ret; + } + + if (is_on == on) { + dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n", + pmd->genpd.name, on ? "en" : "dis"); + return 0; + } + + spin_lock_irqsave(&pmu->lock, flags); + + /* + * The PMU accepts software encourage to switch power mode in the following 2 steps: + * + * 1.Configure the register SW_TURN_ON_POWER (offset 0x0c) by writing 1 to + * the bit corresponding to the power domain that will be turned on + * and writing 0 to the others. + * Likewise, configure the register SW_TURN_OFF_POWER (offset 0x10) by + * writing 1 to the bit corresponding to the power domain that will be + * turned off and writing 0 to the others. + */ + if (on) { + mode = JH71XX_PMU_SW_TURN_ON_POWER; + encourage_lo = JH71XX_PMU_SW_ENCOURAGE_EN_LO; + encourage_hi = JH71XX_PMU_SW_ENCOURAGE_EN_HI; + } else { + mode = JH71XX_PMU_SW_TURN_OFF_POWER; + encourage_lo = JH71XX_PMU_SW_ENCOURAGE_DIS_LO; + encourage_hi = JH71XX_PMU_SW_ENCOURAGE_DIS_HI; + } + + writel(mask, pmu->base + mode); + + /* + * 2.Write SW encourage command sequence to the Software Encourage Reg (offset 0x44) + * First write SW_MODE_ENCOURAGE_ON to JH71XX_PMU_SW_ENCOURAGE. This will reset + * the state machine which parses the command sequence. This register must be + * written every time software wants to power on/off a domain. + * Then write the lower bits of the command sequence, followed by the upper + * bits. The sequence differs between powering on & off a domain. + */ + writel(JH71XX_PMU_SW_ENCOURAGE_ON, pmu->base + JH71XX_PMU_SW_ENCOURAGE); + writel(encourage_lo, pmu->base + JH71XX_PMU_SW_ENCOURAGE); + writel(encourage_hi, pmu->base + JH71XX_PMU_SW_ENCOURAGE); + + spin_unlock_irqrestore(&pmu->lock, flags); + + /* Wait for the power domain bit to be enabled / disabled */ + if (on) { + ret = readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE, + val, val & mask, + 1, JH71XX_PMU_TIMEOUT_US); + } else { + ret = readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE, + val, !(val & mask), + 1, JH71XX_PMU_TIMEOUT_US); + } + + if (ret) { + dev_err(pmu->dev, "%s: failed to power %s\n", + pmd->genpd.name, on ? "on" : "off"); + return -ETIMEDOUT; + } + + return 0; +} + +static int jh71xx_pmu_on(struct generic_pm_domain *genpd) +{ + struct jh71xx_pmu_dev *pmd = container_of(genpd, + struct jh71xx_pmu_dev, genpd); + u32 pwr_mask = BIT(pmd->domain_info->bit); + + return jh71xx_pmu_set_state(pmd, pwr_mask, true); +} + +static int jh71xx_pmu_off(struct generic_pm_domain *genpd) +{ + struct jh71xx_pmu_dev *pmd = container_of(genpd, + struct jh71xx_pmu_dev, genpd); + u32 pwr_mask = BIT(pmd->domain_info->bit); + + return jh71xx_pmu_set_state(pmd, pwr_mask, false); +} + +static void jh71xx_pmu_int_enable(struct jh71xx_pmu *pmu, u32 mask, bool enable) +{ + u32 val; + unsigned long flags; + + spin_lock_irqsave(&pmu->lock, flags); + val = readl(pmu->base + JH71XX_PMU_TIMER_INT_MASK); + + if (enable) + val &= ~mask; + else + val |= mask; + + writel(val, pmu->base + JH71XX_PMU_TIMER_INT_MASK); + spin_unlock_irqrestore(&pmu->lock, flags); +} + +static irqreturn_t jh71xx_pmu_interrupt(int irq, void *data) +{ + struct jh71xx_pmu *pmu = data; + u32 val; + + val = readl(pmu->base + JH71XX_PMU_INT_STATUS); + + if (val & JH71XX_PMU_INT_SEQ_DONE) + dev_dbg(pmu->dev, "sequence done.\n"); + if (val & JH71XX_PMU_INT_HW_REQ) + dev_dbg(pmu->dev, "hardware encourage requestion.\n"); + if (val & JH71XX_PMU_INT_SW_FAIL) + dev_err(pmu->dev, "software encourage fail.\n"); + if (val & JH71XX_PMU_INT_HW_FAIL) + dev_err(pmu->dev, "hardware encourage fail.\n"); + if (val & JH71XX_PMU_INT_PCH_FAIL) + dev_err(pmu->dev, "p-channel fail event.\n"); + + /* clear interrupts */ + writel(val, pmu->base + JH71XX_PMU_INT_STATUS); + writel(val, pmu->base + JH71XX_PMU_EVENT_STATUS); + + return IRQ_HANDLED; +} + +static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index) +{ + struct jh71xx_pmu_dev *pmd; + u32 pwr_mask; + int ret; + bool is_on = false; + + pmd = devm_kzalloc(pmu->dev, sizeof(*pmd), GFP_KERNEL); + if (!pmd) + return -ENOMEM; + + pmd->domain_info = &pmu->match_data->domain_info[index]; + pmd->pmu = pmu; + pwr_mask = BIT(pmd->domain_info->bit); + + pmd->genpd.name = pmd->domain_info->name; + pmd->genpd.flags = pmd->domain_info->flags; + + ret = jh71xx_pmu_get_state(pmd, pwr_mask, &is_on); + if (ret) + dev_warn(pmu->dev, "unable to get current state for %s\n", + pmd->genpd.name); + + pmd->genpd.power_on = jh71xx_pmu_on; + pmd->genpd.power_off = jh71xx_pmu_off; + pm_genpd_init(&pmd->genpd, NULL, !is_on); + + pmu->genpd_data.domains[index] = &pmd->genpd; + + return 0; +} + +static int jh71xx_pmu_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + const struct jh71xx_pmu_match_data *match_data; + struct jh71xx_pmu *pmu; + unsigned int i; + int ret; + + pmu = devm_kzalloc(dev, sizeof(*pmu), GFP_KERNEL); + if (!pmu) + return -ENOMEM; + + pmu->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pmu->base)) + return PTR_ERR(pmu->base); + + pmu->irq = platform_get_irq(pdev, 0); + if (pmu->irq < 0) + return pmu->irq; + + ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt, + 0, pdev->name, pmu); + if (ret) + dev_err(dev, "failed to request irq\n"); + + match_data = of_device_get_match_data(dev); + if (!match_data) + return -EINVAL; + + pmu->genpd = devm_kcalloc(dev, match_data->num_domains, + sizeof(struct generic_pm_domain *), + GFP_KERNEL); + if (!pmu->genpd) + return -ENOMEM; + + pmu->dev = dev; + pmu->match_data = match_data; + pmu->genpd_data.domains = pmu->genpd; + pmu->genpd_data.num_domains = match_data->num_domains; + + for (i = 0; i < match_data->num_domains; i++) { + ret = jh71xx_pmu_init_domain(pmu, i); + if (ret) { + dev_err(dev, "failed to initialize power domain\n"); + return ret; + } + } + + spin_lock_init(&pmu->lock); + jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true); + + ret = of_genpd_add_provider_onecell(np, &pmu->genpd_data); + if (ret) { + dev_err(dev, "failed to register genpd driver: %d\n", ret); + return ret; + } + + dev_dbg(dev, "registered %u power domains\n", i); + + return 0; +} + +static const struct jh71xx_domain_info jh7110_power_domains[] = { + [JH7110_PD_SYSTOP] = { + .name = "SYSTOP", + .bit = 0, + .flags = GENPD_FLAG_ALWAYS_ON, + }, + [JH7110_PD_CPU] = { + .name = "CPU", + .bit = 1, + .flags = GENPD_FLAG_ALWAYS_ON, + }, + [JH7110_PD_GPUA] = { + .name = "GPUA", + .bit = 2, + }, + [JH7110_PD_VDEC] = { + .name = "VDEC", + .bit = 3, + }, + [JH7110_PD_VOUT] = { + .name = "VOUT", + .bit = 4, + }, + [JH7110_PD_ISP] = { + .name = "ISP", + .bit = 5, + }, + [JH7110_PD_VENC] = { + .name = "VENC", + .bit = 6, + }, +}; + +static const struct jh71xx_pmu_match_data jh7110_pmu = { + .num_domains = ARRAY_SIZE(jh7110_power_domains), + .domain_info = jh7110_power_domains, +}; + +static const struct of_device_id jh71xx_pmu_of_match[] = { + { + .compatible = "starfive,jh7110-pmu", + .data = (void *)&jh7110_pmu, + }, { + /* sentinel */ + } +}; + +static struct platform_driver jh71xx_pmu_driver = { + .probe = jh71xx_pmu_probe, + .driver = { + .name = "jh71xx-pmu", + .of_match_table = jh71xx_pmu_of_match, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(jh71xx_pmu_driver); + +MODULE_AUTHOR("Walker Chen "); +MODULE_DESCRIPTION("StarFive JH71XX PMU Driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 0c56f949f626e59ef7c5b18e2706fed2a6afc4a2 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 6 Jan 2023 12:58:16 +0000 Subject: soc: renesas: Add PWC support for RZ/V2M The Renesas RZ/V2M External Power Sequence Controller (PWC) IP is capable of: * external power supply on/off sequence generation * on/off signal generation for the LPDDR4 core power supply (LPVDD) * key input signals processing * general-purpose output pins Add the corresponding device driver. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230106125816.10600-3-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/soc/renesas/Kconfig | 4 ++ drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/pwc-rzv2m.c | 141 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 146 insertions(+) create mode 100644 drivers/soc/renesas/pwc-rzv2m.c (limited to 'drivers/soc') diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 660498252ec5..4e8b51ba2266 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -330,6 +330,7 @@ config ARCH_R9A09G011 bool "ARM64 Platform support for RZ/V2M" select PM select PM_GENERIC_DOMAINS + select PWC_RZV2M help This enables support for the Renesas RZ/V2M SoC. @@ -345,6 +346,9 @@ config ARCH_R9A07G043 endif # RISCV +config PWC_RZV2M + bool "Renesas RZ/V2M PWC support" if COMPILE_TEST + config RST_RCAR bool "Reset Controller support for R-Car" if COMPILE_TEST diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 535868c9c7e4..6e4e77b0afff 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o endif # Family +obj-$(CONFIG_PWC_RZV2M) += pwc-rzv2m.o obj-$(CONFIG_RST_RCAR) += rcar-rst.o obj-$(CONFIG_SYSC_RCAR) += rcar-sysc.o obj-$(CONFIG_SYSC_RCAR_GEN4) += rcar-gen4-sysc.o diff --git a/drivers/soc/renesas/pwc-rzv2m.c b/drivers/soc/renesas/pwc-rzv2m.c new file mode 100644 index 000000000000..c83bdbdabb64 --- /dev/null +++ b/drivers/soc/renesas/pwc-rzv2m.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Renesas Electronics Corporation + */ + +#include +#include +#include +#include + +#define PWC_PWCRST 0x00 +#define PWC_PWCCKEN 0x04 +#define PWC_PWCCTL 0x50 +#define PWC_GPIO 0x80 + +#define PWC_PWCRST_RSTSOFTAX 0x1 +#define PWC_PWCCKEN_ENGCKMAIN 0x1 +#define PWC_PWCCTL_PWOFF 0x1 + +struct rzv2m_pwc_priv { + void __iomem *base; + struct device *dev; + struct gpio_chip gp; + DECLARE_BITMAP(ch_en_bits, 2); +}; + +static void rzv2m_pwc_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct rzv2m_pwc_priv *priv = gpiochip_get_data(chip); + u32 reg; + + /* BIT 16 enables write to BIT 0, and BIT 17 enables write to BIT 1 */ + reg = BIT(offset + 16); + if (value) + reg |= BIT(offset); + + writel(reg, priv->base + PWC_GPIO); + + assign_bit(offset, priv->ch_en_bits, value); +} + +static int rzv2m_pwc_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct rzv2m_pwc_priv *priv = gpiochip_get_data(chip); + + return test_bit(offset, priv->ch_en_bits); +} + +static int rzv2m_pwc_gpio_direction_output(struct gpio_chip *gc, + unsigned int nr, int value) +{ + if (nr > 1) + return -EINVAL; + + rzv2m_pwc_gpio_set(gc, nr, value); + + return 0; +} + +static const struct gpio_chip rzv2m_pwc_gc = { + .label = "gpio_rzv2m_pwc", + .owner = THIS_MODULE, + .get = rzv2m_pwc_gpio_get, + .set = rzv2m_pwc_gpio_set, + .direction_output = rzv2m_pwc_gpio_direction_output, + .can_sleep = false, + .ngpio = 2, + .base = -1, +}; + +static int rzv2m_pwc_poweroff(struct sys_off_data *data) +{ + struct rzv2m_pwc_priv *priv = data->cb_data; + + writel(PWC_PWCRST_RSTSOFTAX, priv->base + PWC_PWCRST); + writel(PWC_PWCCKEN_ENGCKMAIN, priv->base + PWC_PWCCKEN); + writel(PWC_PWCCTL_PWOFF, priv->base + PWC_PWCCTL); + + mdelay(150); + + dev_err(priv->dev, "Failed to power off the system"); + + return NOTIFY_DONE; +} + +static int rzv2m_pwc_probe(struct platform_device *pdev) +{ + struct rzv2m_pwc_priv *priv; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + /* + * The register used by this driver cannot be read, therefore set the + * outputs to their default values and initialize priv->ch_en_bits + * accordingly. BIT 16 enables write to BIT 0, BIT 17 enables write to + * BIT 1, and the default value of both BIT 0 and BIT 1 is 0. + */ + writel(BIT(17) | BIT(16), priv->base + PWC_GPIO); + bitmap_zero(priv->ch_en_bits, 2); + + priv->gp = rzv2m_pwc_gc; + priv->gp.parent = pdev->dev.parent; + priv->gp.fwnode = dev_fwnode(&pdev->dev); + + ret = devm_gpiochip_add_data(&pdev->dev, &priv->gp, priv); + if (ret) + return ret; + + if (device_property_read_bool(&pdev->dev, "renesas,rzv2m-pwc-power")) + ret = devm_register_power_off_handler(&pdev->dev, + rzv2m_pwc_poweroff, priv); + + return ret; +} + +static const struct of_device_id rzv2m_pwc_of_match[] = { + { .compatible = "renesas,rzv2m-pwc" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rzv2m_pwc_of_match); + +static struct platform_driver rzv2m_pwc_driver = { + .probe = rzv2m_pwc_probe, + .driver = { + .name = "rzv2m_pwc", + .of_match_table = of_match_ptr(rzv2m_pwc_of_match), + }, +}; +module_platform_driver(rzv2m_pwc_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Fabrizio Castro "); +MODULE_DESCRIPTION("Renesas RZ/V2M PWC driver"); -- cgit v1.2.3 From 39170127c1ed12e178c31f02527cca45c2f24416 Mon Sep 17 00:00:00 2001 From: "Nancy.Lin" Date: Fri, 13 Jan 2023 18:44:27 +0800 Subject: soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Add mt8195 vdosys1 routing table to the driver data of mtk-mmsys. Signed-off-by: Nancy.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen Reviewed-by: CK Hu Tested-by: AngeloGioacchino Del Regno Tested-by: Bo-Chen Chen Link: https://lore.kernel.org/r/20230113104434.28023-5-nancy.lin@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mt8195-mmsys.h | 139 ++++++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 10 +++ 2 files changed, 149 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h index abfe94a30248..fd7b455bd675 100644 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -75,6 +75,70 @@ #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16) #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16) +#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04 +#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1 + +#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08 +#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1 + +#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10 +#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0 + +#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14 +#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0 + +#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18 +#define MT8195_MERGE4_SOUT_TO_DPI1_SEL 2 +#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL 3 + +#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24 +#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1 + +#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28 +#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1 + +#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c +#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1 + +#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30 +#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1 + +#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34 +#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1 + +#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c +#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1 + +#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40 +#define MT8195_SOUT_TO_MIXER_IN1_SEL 1 + +#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44 +#define MT8195_SOUT_TO_MIXER_IN2_SEL 1 + +#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48 +#define MT8195_SOUT_TO_MIXER_IN3_SEL 1 + +#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c +#define MT8195_SOUT_TO_MIXER_IN4_SEL 1 + +#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50 +#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1 + +#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58 +#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER 0 + +#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c +#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER 0 + +#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60 +#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER 0 + +#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64 +#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER 0 + +#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68 +#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 + static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { { DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, @@ -367,4 +431,79 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { } }; +static const struct mtk_mmsys_routes mmsys_mt8195_vdo1_routing_table[] = { + { + DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1, + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), + MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 + }, { + DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1, + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), + MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 + }, { + DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2, + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), + MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 + }, { + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8195_SOUT_TO_MIXER_IN1_SEL + }, { + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8195_SOUT_TO_MIXER_IN2_SEL + }, { + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8195_SOUT_TO_MIXER_IN3_SEL + }, { + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8195_SOUT_TO_MIXER_IN4_SEL + }, { + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, + MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), + MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL + }, { + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, + MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), + MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT + }, { + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, + MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), + MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT + }, { + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, + MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), + MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT + }, { + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, + MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), + MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT + }, { + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, + MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), + MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER + }, { + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, + MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), + MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, + MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), + MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, + MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), + MT8195_MERGE4_SOUT_TO_DPI1_SEL + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, + MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), + MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, + MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), + MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL + } +}; #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 38f1dd92e7c6..e75ac7f5aa3c 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -88,6 +88,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), }; +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { + .clk_driver = "clk-mt8195-vdo1", + .routes = mmsys_mt8195_vdo1_routing_table, + .num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table), +}; + static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { .clk_driver = "clk-mt8365-mm", .routes = mt8365_mmsys_routing_table, @@ -323,6 +329,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = { .compatible = "mediatek,mt8195-vdosys0", .data = &mt8195_vdosys0_driver_data, }, + { + .compatible = "mediatek,mt8195-vdosys1", + .data = &mt8195_vdosys1_driver_data, + }, { .compatible = "mediatek,mt8365-mmsys", .data = &mt8365_mmsys_driver_data, -- cgit v1.2.3 From 0a815034a52ab315befb191ef6381fbd19019793 Mon Sep 17 00:00:00 2001 From: "Nancy.Lin" Date: Fri, 13 Jan 2023 18:44:28 +0800 Subject: soc: mediatek: refine code to use mtk_mmsys_update_bits API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Simplify code for update mmsys reg. Signed-off-by: Nancy.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Tested-by: AngeloGioacchino Del Regno Tested-by: Bo-Chen Chen Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20230113104434.28023-6-nancy.lin@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mmsys.c | 45 ++++++++++++++-------------------------- 1 file changed, 16 insertions(+), 29 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index e75ac7f5aa3c..602197e95f67 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -107,22 +107,27 @@ struct mtk_mmsys { struct reset_controller_dev rcdev; }; +static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val) +{ + u32 tmp; + + tmp = readl_relaxed(mmsys->regs + offset); + tmp = (tmp & ~mask) | (val & mask); + writel_relaxed(tmp, mmsys->regs + offset); +} + void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) { struct mtk_mmsys *mmsys = dev_get_drvdata(dev); const struct mtk_mmsys_routes *routes = mmsys->data->routes; - u32 reg; int i; for (i = 0; i < mmsys->data->num_routes; i++) - if (cur == routes[i].from_comp && next == routes[i].to_comp) { - reg = readl_relaxed(mmsys->regs + routes[i].addr); - reg &= ~routes[i].mask; - reg |= routes[i].val; - writel_relaxed(reg, mmsys->regs + routes[i].addr); - } + if (cur == routes[i].from_comp && next == routes[i].to_comp) + mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, + routes[i].val); } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); @@ -132,27 +137,14 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, { struct mtk_mmsys *mmsys = dev_get_drvdata(dev); const struct mtk_mmsys_routes *routes = mmsys->data->routes; - u32 reg; int i; for (i = 0; i < mmsys->data->num_routes; i++) - if (cur == routes[i].from_comp && next == routes[i].to_comp) { - reg = readl_relaxed(mmsys->regs + routes[i].addr); - reg &= ~routes[i].mask; - writel_relaxed(reg, mmsys->regs + routes[i].addr); - } + if (cur == routes[i].from_comp && next == routes[i].to_comp) + mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 0); } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); -static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val) -{ - u32 tmp; - - tmp = readl_relaxed(mmsys->regs + offset); - tmp = (tmp & ~mask) | val; - writel_relaxed(tmp, mmsys->regs + offset); -} - void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val) { struct mtk_mmsys *mmsys = dev_get_drvdata(dev); @@ -184,18 +176,13 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l { struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev); unsigned long flags; - u32 reg; spin_lock_irqsave(&mmsys->lock, flags); - reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset); - if (assert) - reg &= ~BIT(id); + mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), 0); else - reg |= BIT(id); - - writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset); + mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), BIT(id)); spin_unlock_irqrestore(&mmsys->lock, flags); -- cgit v1.2.3 From 3dd20b715c4483ae5d8ddb22cbc8e116944094e4 Mon Sep 17 00:00:00 2001 From: "Nancy.Lin" Date: Fri, 13 Jan 2023 18:44:29 +0800 Subject: soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1 Add four mmsys config APIs. The config APIs are used for config mmsys reg. Some mmsys regs need to be set according to the HW engine binding to the mmsys simultaneously. 1. mtk_mmsys_merge_async_config: config merge async width/height. async is used for cross-clock domain synchronization. 2. mtk_mmsys_hdr_confing: config hdr backend async width/height. 3. mtk_mmsys_mixer_in_config and mtk_mmsys_mixer_in_config: config mixer related settings. Signed-off-by: Nancy.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Tested-by: AngeloGioacchino Del Regno Tested-by: Bo-Chen Chen Link: https://lore.kernel.org/r/20230113104434.28023-7-nancy.lin@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mt8195-mmsys.h | 6 ++++++ drivers/soc/mediatek/mtk-mmsys.c | 35 ++++++++++++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-mmsys.h | 9 +++++++++ 3 files changed, 50 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h index fd7b455bd675..454944a9409c 100644 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -75,6 +75,12 @@ #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16) #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16) +#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 +#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70 +#define MT8195_VDO1_HDR_TOP_CFG 0xd00 +#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30 +#define MT8195_VDO1_MIXER_IN1_PAD 0xd40 + #define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04 #define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1 diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 602197e95f67..2aeb739b8503 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -145,6 +145,41 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); +void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height) +{ + mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx, + ~0, height << 16 | width); +} +EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config); + +void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height) +{ + mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0, + be_height << 16 | be_width); +} +EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_config); + +void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha, + u8 mode, u32 biwidth) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + + mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, ~0, + alpha << 16 | alpha); + mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx), + alpha_sel << (19 + idx)); + mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4, + GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode); +} +EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config); + +void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap) +{ + mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4, + BIT(4), channel_swap << 4); +} +EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap); + void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val) { struct mtk_mmsys *mmsys = dev_get_drvdata(dev); diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 3e4b080627c3..5a6753aed482 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -83,4 +83,13 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val); +void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height); + +void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height); + +void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha, + u8 mode, u32 biwidth); + +void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap); + #endif /* __MTK_MMSYS_H */ -- cgit v1.2.3 From 8af1f6b5bccb61edc40c3c00cefa7be07c1e5a91 Mon Sep 17 00:00:00 2001 From: "Nancy.Lin" Date: Fri, 13 Jan 2023 18:44:30 +0800 Subject: soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1 Add cmdq support for mtk-mmsys config API. The mmsys config register settings need to take effect with the other HW settings(like OVL_ADAPTOR...) at the same vblanking time. If we use CPU to write the mmsys reg, we can't guarantee all the settings can be written in the same vblanking time. Cmdq is used for this purpose. We prepare all the related HW settings in one cmdq packet. The first command in the packet is "wait stream done", and then following with all the HW settings. After the cmdq packet is flush to GCE HW. The GCE waits for the "stream done event" to coming and then starts flushing all the HW settings. This can guarantee all the settings flush in the same vblanking. Signed-off-by: Nancy.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Tested-by: AngeloGioacchino Del Regno Tested-by: Bo-Chen Chen Link: https://lore.kernel.org/r/20230113104434.28023-8-nancy.lin@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mmsys.c | 63 ++++++++++++++++++++++++---------- include/linux/soc/mediatek/mtk-mmsys.h | 15 +++++--- 2 files changed, 55 insertions(+), 23 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 2aeb739b8503..a0a584f16405 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -105,12 +105,27 @@ struct mtk_mmsys { const struct mtk_mmsys_driver_data *data; spinlock_t lock; /* protects mmsys_sw_rst_b reg */ struct reset_controller_dev rcdev; + struct cmdq_client_reg cmdq_base; }; -static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val) +static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val, + struct cmdq_pkt *cmdq_pkt) { u32 tmp; +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + if (cmdq_pkt) { + if (mmsys->cmdq_base.size == 0) { + pr_err("mmsys lose gce property, failed to update mmsys bits with cmdq"); + return; + } + cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys, + mmsys->cmdq_base.offset + offset, val, + mask); + return; + } +#endif + tmp = readl_relaxed(mmsys->regs + offset); tmp = (tmp & ~mask) | (val & mask); writel_relaxed(tmp, mmsys->regs + offset); @@ -127,7 +142,7 @@ void mtk_mmsys_ddp_connect(struct device *dev, for (i = 0; i < mmsys->data->num_routes; i++) if (cur == routes[i].from_comp && next == routes[i].to_comp) mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, - routes[i].val); + routes[i].val, NULL); } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); @@ -141,42 +156,45 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, for (i = 0; i < mmsys->data->num_routes; i++) if (cur == routes[i].from_comp && next == routes[i].to_comp) - mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 0); + mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 0, NULL); } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); -void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height) +void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height, + struct cmdq_pkt *cmdq_pkt) { mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx, - ~0, height << 16 | width); + ~0, height << 16 | width, cmdq_pkt); } EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config); -void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height) +void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height, + struct cmdq_pkt *cmdq_pkt) { mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0, - be_height << 16 | be_width); + be_height << 16 | be_width, cmdq_pkt); } EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_config); void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha, - u8 mode, u32 biwidth) + u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt) { struct mtk_mmsys *mmsys = dev_get_drvdata(dev); mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, ~0, - alpha << 16 | alpha); + alpha << 16 | alpha, cmdq_pkt); mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx), - alpha_sel << (19 + idx)); + alpha_sel << (19 + idx), cmdq_pkt); mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4, - GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode); + GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode, cmdq_pkt); } EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config); -void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap) +void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap, + struct cmdq_pkt *cmdq_pkt) { mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4, - BIT(4), channel_swap << 4); + BIT(4), channel_swap << 4, cmdq_pkt); } EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap); @@ -187,20 +205,20 @@ void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val) switch (val) { case MTK_DPI_RGB888_SDR_CON: mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, - MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_SDR_CON); + MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_SDR_CON, NULL); break; case MTK_DPI_RGB565_SDR_CON: mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, - MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_SDR_CON); + MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_SDR_CON, NULL); break; case MTK_DPI_RGB565_DDR_CON: mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, - MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_DDR_CON); + MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB565_DDR_CON, NULL); break; case MTK_DPI_RGB888_DDR_CON: default: mtk_mmsys_update_bits(mmsys, MT8186_MMSYS_DPI_OUTPUT_FORMAT, - MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_DDR_CON); + MT8186_DPI_FORMAT_MASK, MT8186_DPI_RGB888_DDR_CON, NULL); break; } } @@ -215,9 +233,9 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l spin_lock_irqsave(&mmsys->lock, flags); if (assert) - mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), 0); + mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), 0, NULL); else - mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), BIT(id)); + mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), BIT(id), NULL); spin_unlock_irqrestore(&mmsys->lock, flags); @@ -285,6 +303,13 @@ static int mtk_mmsys_probe(struct platform_device *pdev) } mmsys->data = of_device_get_match_data(&pdev->dev); + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0); + if (ret) + dev_dbg(dev, "No mediatek,gce-client-reg!\n"); +#endif + platform_set_drvdata(pdev, mmsys); clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 5a6753aed482..dc2963a0a0f7 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -6,6 +6,10 @@ #ifndef __MTK_MMSYS_H #define __MTK_MMSYS_H +#include +#include +#include + enum mtk_ddp_comp_id; struct device; @@ -83,13 +87,16 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val); -void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height); +void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, + int height, struct cmdq_pkt *cmdq_pkt); -void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height); +void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height, + struct cmdq_pkt *cmdq_pkt); void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha, - u8 mode, u32 biwidth); + u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt); -void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap); +void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap, + struct cmdq_pkt *cmdq_pkt); #endif /* __MTK_MMSYS_H */ -- cgit v1.2.3 From 2004f8be8483ad0e5c73bcf9f5985dd4386e2061 Mon Sep 17 00:00:00 2001 From: "Nancy.Lin" Date: Fri, 13 Jan 2023 18:44:31 +0800 Subject: soc: mediatek: mmsys: add mmsys for support 64 reset bits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add mmsys for support 64 reset bits. It is a preparation for MT8195 vdosys1 HW reset. MT8195 vdosys1 has more than 32 reset bits. 1. Add the number of reset bits in mmsys private data 2. move the whole "reset register code section" behind the "get mmsys->data" code section for getting the num_resets in mmsys->data. Signed-off-by: Nancy.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Tested-by: Bo-Chen Chen Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20230113104434.28023-9-nancy.lin@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mmsys.c | 40 +++++++++++++++++++++++++++------------- drivers/soc/mediatek/mtk-mmsys.h | 1 + 2 files changed, 28 insertions(+), 13 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index a0a584f16405..32b17c56c44a 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -22,6 +22,8 @@ #include "mt8195-mmsys.h" #include "mt8365-mmsys.h" +#define MMSYS_SW_RESET_PER_REG 32 + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", .routes = mmsys_default_routing_table, @@ -53,6 +55,7 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .routes = mmsys_default_routing_table, .num_routes = ARRAY_SIZE(mmsys_default_routing_table), .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, + .num_resets = 32, }; static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { @@ -60,6 +63,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .routes = mmsys_mt8183_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, + .num_resets = 32, }; static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { @@ -67,6 +71,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { .routes = mmsys_mt8186_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table), .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, + .num_resets = 32, }; static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { @@ -80,6 +85,7 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .routes = mmsys_mt8192_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, + .num_resets = 32, }; static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { @@ -229,13 +235,19 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l { struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev); unsigned long flags; + u32 offset; + u32 reg; + + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); + id = id % MMSYS_SW_RESET_PER_REG; + reg = mmsys->data->sw0_rst_offset + offset; spin_lock_irqsave(&mmsys->lock, flags); if (assert) - mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), 0, NULL); + mtk_mmsys_update_bits(mmsys, reg, BIT(id), 0, NULL); else - mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), BIT(id), NULL); + mtk_mmsys_update_bits(mmsys, reg, BIT(id), BIT(id), NULL); spin_unlock_irqrestore(&mmsys->lock, flags); @@ -290,20 +302,22 @@ static int mtk_mmsys_probe(struct platform_device *pdev) return ret; } - spin_lock_init(&mmsys->lock); + mmsys->data = of_device_get_match_data(&pdev->dev); - mmsys->rcdev.owner = THIS_MODULE; - mmsys->rcdev.nr_resets = 32; - mmsys->rcdev.ops = &mtk_mmsys_reset_ops; - mmsys->rcdev.of_node = pdev->dev.of_node; - ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev); - if (ret) { - dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret); - return ret; + if (mmsys->data->num_resets > 0) { + spin_lock_init(&mmsys->lock); + + mmsys->rcdev.owner = THIS_MODULE; + mmsys->rcdev.nr_resets = mmsys->data->num_resets; + mmsys->rcdev.ops = &mtk_mmsys_reset_ops; + mmsys->rcdev.of_node = pdev->dev.of_node; + ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev); + if (ret) { + dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret); + return ret; + } } - mmsys->data = of_device_get_match_data(&pdev->dev); - #if IS_REACHABLE(CONFIG_MTK_CMDQ) ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0); if (ret) diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 77f37f8c715b..e19994749adb 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -91,6 +91,7 @@ struct mtk_mmsys_driver_data { const struct mtk_mmsys_routes *routes; const unsigned int num_routes; const u16 sw0_rst_offset; + const u32 num_resets; }; /* -- cgit v1.2.3 From 7f0a38f46b67ba15c0fb5fc6c075a74ae9bb385d Mon Sep 17 00:00:00 2001 From: "Nancy.Lin" Date: Fri, 13 Jan 2023 18:44:32 +0800 Subject: soc: mediatek: mmsys: add reset control for MT8195 vdosys1 MT8195 vdosys1 has more than 32 reset bits and a different reset base than other chips. Add the number of reset bits and reset base in mmsys private data. Signed-off-by: Nancy.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Tested-by: AngeloGioacchino Del Regno Tested-by: Bo-Chen Chen Link: https://lore.kernel.org/r/20230113104434.28023-10-nancy.lin@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mt8195-mmsys.h | 1 + drivers/soc/mediatek/mtk-mmsys.c | 2 ++ 2 files changed, 3 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h index 454944a9409c..a6652ae63431 100644 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -75,6 +75,7 @@ #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16) #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16) +#define MT8195_VDO1_SW0_RST_B 0x1d0 #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 #define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70 #define MT8195_VDO1_HDR_TOP_CFG 0xd00 diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 32b17c56c44a..297c810440f4 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -98,6 +98,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { .clk_driver = "clk-mt8195-vdo1", .routes = mmsys_mt8195_vdo1_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table), + .sw0_rst_offset = MT8195_VDO1_SW0_RST_B, + .num_resets = 64, }; static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { -- cgit v1.2.3 From 8150a0e3a9d49a99cbfafc950f2ed8fe448b4117 Mon Sep 17 00:00:00 2001 From: "Nancy.Lin" Date: Fri, 13 Jan 2023 18:44:33 +0800 Subject: soc: mediatek: add mtk-mutex component - dp_intf1 Add mtk-mutex DDP_COMPONENT_DP_INTF1 component. The MT8195 vdosys1 path component contains ovl_adaptor, merge5, and dp_intf1. It is a preparation for adding support for MT8195 vdosys1 path component. Signed-off-by: Nancy.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Tested-by: AngeloGioacchino Del Regno Tested-by: Bo-Chen Chen Link: https://lore.kernel.org/r/20230113104434.28023-11-nancy.lin@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mutex.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 582d4b04e353..e2d04f1a231e 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -653,6 +653,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex, case DDP_COMPONENT_DP_INTF0: sof_id = MUTEX_SOF_DP_INTF0; break; + case DDP_COMPONENT_DP_INTF1: + sof_id = MUTEX_SOF_DP_INTF1; + break; default: if (mtx->data->mutex_mod[id] < 32) { offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, @@ -693,6 +696,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex, case DDP_COMPONENT_DPI0: case DDP_COMPONENT_DPI1: case DDP_COMPONENT_DP_INTF0: + case DDP_COMPONENT_DP_INTF1: writel_relaxed(MUTEX_SOF_SINGLE_MODE, mtx->regs + DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, -- cgit v1.2.3 From 4ea6aa8902fc62bd3576eaef248067cc106f8a41 Mon Sep 17 00:00:00 2001 From: "Nancy.Lin" Date: Fri, 13 Jan 2023 18:44:34 +0800 Subject: soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Add mtk-mutex support for mt8195 vdosys1. The vdosys1 path component contains ovl_adaptor, merge5, and dp_intf1. Ovl_adaptor is composed of several sub-elements which include MDP_RDMA0~7, MERGE0~3, and ETHDR. Signed-off-by: Nancy.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Tested-by: AngeloGioacchino Del Regno Tested-by: Bo-Chen Chen Link: https://lore.kernel.org/r/20230113104434.28023-12-nancy.lin@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mutex.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index e2d04f1a231e..c5b1b42303ac 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -145,6 +145,24 @@ #define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 #define MT8195_MUTEX_MOD_DISP_PWM0 27 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 0 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 1 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 2 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 3 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 4 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 5 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 6 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 7 +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 8 +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 9 +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 10 +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 11 +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 12 +#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER 18 +#define MT8195_MUTEX_MOD_DISP1_DPI0 25 +#define MT8195_MUTEX_MOD_DISP1_DPI1 26 +#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 27 + #define MT8365_MUTEX_MOD_DISP_OVL0 7 #define MT8365_MUTEX_MOD_DISP_OVL0_2L 8 #define MT8365_MUTEX_MOD_DISP_RDMA0 9 @@ -408,6 +426,21 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0, + [DDP_COMPONENT_MDP_RDMA0] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0, + [DDP_COMPONENT_MDP_RDMA1] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA1, + [DDP_COMPONENT_MDP_RDMA2] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA2, + [DDP_COMPONENT_MDP_RDMA3] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA3, + [DDP_COMPONENT_MDP_RDMA4] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA4, + [DDP_COMPONENT_MDP_RDMA5] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA5, + [DDP_COMPONENT_MDP_RDMA6] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA6, + [DDP_COMPONENT_MDP_RDMA7] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA7, + [DDP_COMPONENT_MERGE1] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE0, + [DDP_COMPONENT_MERGE2] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE1, + [DDP_COMPONENT_MERGE3] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE2, + [DDP_COMPONENT_MERGE4] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE3, + [DDP_COMPONENT_ETHDR_MIXER] = MT8195_MUTEX_MOD_DISP1_DISP_MIXER, + [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4, + [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0, }; static const unsigned int mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = { -- cgit v1.2.3 From b74952aba6c3f47e7f2c5165abaeefa44c377140 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Date: Tue, 20 Dec 2022 22:35:59 +0100 Subject: soc: mediatek: mtk-svs: Enable the IRQ later If the system does not come from reset (like when is booted via kexec()), the peripheral might triger an IRQ before the data structures are initialised. Fixes: [ 0.227710] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000f08 [ 0.227913] Call trace: [ 0.227918] svs_isr+0x8c/0x538 Signed-off-by: Ricardo Ribalda Link: https://lore.kernel.org/r/20221127-mtk-svs-v2-0-145b07663ea8@chromium.org Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-svs.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 0469c9dfeb04..75b2f534aa9d 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -2385,14 +2385,6 @@ static int svs_probe(struct platform_device *pdev) goto svs_probe_free_resource; } - ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr, - IRQF_ONESHOT, svsp->name, svsp); - if (ret) { - dev_err(svsp->dev, "register irq(%d) failed: %d\n", - svsp_irq, ret); - goto svs_probe_free_resource; - } - svsp->main_clk = devm_clk_get(svsp->dev, "main"); if (IS_ERR(svsp->main_clk)) { dev_err(svsp->dev, "failed to get clock: %ld\n", @@ -2414,6 +2406,14 @@ static int svs_probe(struct platform_device *pdev) goto svs_probe_clk_disable; } + ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr, + IRQF_ONESHOT, svsp->name, svsp); + if (ret) { + dev_err(svsp->dev, "register irq(%d) failed: %d\n", + svsp_irq, ret); + goto svs_probe_iounmap; + } + ret = svs_start(svsp); if (ret) { dev_err(svsp->dev, "svs start fail: %d\n", ret); -- cgit v1.2.3 From 0e30ca5ab0a80fdc7f1055f63c1436dfdc4d317d Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 26 Jan 2023 00:34:18 -0600 Subject: soc: sunxi: Add Allwinner D1 PPU driver The PPU contains a series of identical MMIO register ranges, one for each power domain. Each range contains control/status bits for a clock gate, reset line, output gates, and a power switch. (The clock and reset are separate from, and in addition to, the bits in the CCU.) It also contains a hardware power sequence engine to control the other bits. Acked-by: Jernej Skrabec Signed-off-by: Samuel Holland Link: https://lore.kernel.org/r/20230126063419.15971-3-samuel@sholland.org Signed-off-by: Jernej Skrabec --- drivers/soc/sunxi/Kconfig | 8 ++ drivers/soc/sunxi/Makefile | 1 + drivers/soc/sunxi/sun20i-ppu.c | 207 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 216 insertions(+) create mode 100644 drivers/soc/sunxi/sun20i-ppu.c (limited to 'drivers/soc') diff --git a/drivers/soc/sunxi/Kconfig b/drivers/soc/sunxi/Kconfig index 8aecbc9b1976..29e9ba2d520d 100644 --- a/drivers/soc/sunxi/Kconfig +++ b/drivers/soc/sunxi/Kconfig @@ -19,3 +19,11 @@ config SUNXI_SRAM Say y here to enable the SRAM controller support. This device is responsible on mapping the SRAM in the sunXi SoCs whether to the CPU/DMA, or to the devices. + +config SUN20I_PPU + bool "Allwinner D1 PPU power domain driver" + depends on ARCH_SUNXI || COMPILE_TEST + select PM_GENERIC_DOMAINS + help + Say y to enable the PPU power domain driver. This saves power + when certain peripherals, such as the video engine, are idle. diff --git a/drivers/soc/sunxi/Makefile b/drivers/soc/sunxi/Makefile index 549159571d4f..90ff2ebe7655 100644 --- a/drivers/soc/sunxi/Makefile +++ b/drivers/soc/sunxi/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_SUNXI_MBUS) += sunxi_mbus.o obj-$(CONFIG_SUNXI_SRAM) += sunxi_sram.o +obj-$(CONFIG_SUN20I_PPU) += sun20i-ppu.o diff --git a/drivers/soc/sunxi/sun20i-ppu.c b/drivers/soc/sunxi/sun20i-ppu.c new file mode 100644 index 000000000000..98cb41d36560 --- /dev/null +++ b/drivers/soc/sunxi/sun20i-ppu.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PD_STATE_ON 1 +#define PD_STATE_OFF 2 + +#define PD_RSTN_REG 0x00 +#define PD_CLK_GATE_REG 0x04 +#define PD_PWROFF_GATE_REG 0x08 +#define PD_PSW_ON_REG 0x0c +#define PD_PSW_OFF_REG 0x10 +#define PD_PSW_DELAY_REG 0x14 +#define PD_OFF_DELAY_REG 0x18 +#define PD_ON_DELAY_REG 0x1c +#define PD_COMMAND_REG 0x20 +#define PD_STATUS_REG 0x24 +#define PD_STATUS_COMPLETE BIT(1) +#define PD_STATUS_BUSY BIT(3) +#define PD_STATUS_STATE GENMASK(17, 16) +#define PD_ACTIVE_CTRL_REG 0x2c +#define PD_GATE_STATUS_REG 0x30 +#define PD_RSTN_STATUS BIT(0) +#define PD_CLK_GATE_STATUS BIT(1) +#define PD_PWROFF_GATE_STATUS BIT(2) +#define PD_PSW_STATUS_REG 0x34 + +#define PD_REGS_SIZE 0x80 + +struct sun20i_ppu_desc { + const char *const *names; + unsigned int num_domains; +}; + +struct sun20i_ppu_pd { + struct generic_pm_domain genpd; + void __iomem *base; +}; + +#define to_sun20i_ppu_pd(_genpd) \ + container_of(_genpd, struct sun20i_ppu_pd, genpd) + +static bool sun20i_ppu_pd_is_on(const struct sun20i_ppu_pd *pd) +{ + u32 status = readl(pd->base + PD_STATUS_REG); + + return FIELD_GET(PD_STATUS_STATE, status) == PD_STATE_ON; +} + +static int sun20i_ppu_pd_set_power(const struct sun20i_ppu_pd *pd, bool power_on) +{ + u32 state, status; + int ret; + + if (sun20i_ppu_pd_is_on(pd) == power_on) + return 0; + + /* Wait for the power controller to be idle. */ + ret = readl_poll_timeout(pd->base + PD_STATUS_REG, status, + !(status & PD_STATUS_BUSY), 100, 1000); + if (ret) + return ret; + + state = power_on ? PD_STATE_ON : PD_STATE_OFF; + writel(state, pd->base + PD_COMMAND_REG); + + /* Wait for the state transition to complete. */ + ret = readl_poll_timeout(pd->base + PD_STATUS_REG, status, + FIELD_GET(PD_STATUS_STATE, status) == state && + (status & PD_STATUS_COMPLETE), 100, 1000); + if (ret) + return ret; + + /* Clear the completion flag. */ + writel(status, pd->base + PD_STATUS_REG); + + return 0; +} + +static int sun20i_ppu_pd_power_on(struct generic_pm_domain *genpd) +{ + const struct sun20i_ppu_pd *pd = to_sun20i_ppu_pd(genpd); + + return sun20i_ppu_pd_set_power(pd, true); +} + +static int sun20i_ppu_pd_power_off(struct generic_pm_domain *genpd) +{ + const struct sun20i_ppu_pd *pd = to_sun20i_ppu_pd(genpd); + + return sun20i_ppu_pd_set_power(pd, false); +} + +static int sun20i_ppu_probe(struct platform_device *pdev) +{ + const struct sun20i_ppu_desc *desc; + struct device *dev = &pdev->dev; + struct genpd_onecell_data *ppu; + struct sun20i_ppu_pd *pds; + struct reset_control *rst; + void __iomem *base; + struct clk *clk; + int ret; + + desc = of_device_get_match_data(dev); + if (!desc) + return -EINVAL; + + pds = devm_kcalloc(dev, desc->num_domains, sizeof(*pds), GFP_KERNEL); + if (!pds) + return -ENOMEM; + + ppu = devm_kzalloc(dev, sizeof(*ppu), GFP_KERNEL); + if (!ppu) + return -ENOMEM; + + ppu->domains = devm_kcalloc(dev, desc->num_domains, + sizeof(*ppu->domains), GFP_KERNEL); + if (!ppu->domains) + return -ENOMEM; + + ppu->num_domains = desc->num_domains; + platform_set_drvdata(pdev, ppu); + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + rst = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(rst)) + return PTR_ERR(rst); + + ret = reset_control_deassert(rst); + if (ret) + return ret; + + for (unsigned int i = 0; i < ppu->num_domains; ++i) { + struct sun20i_ppu_pd *pd = &pds[i]; + + pd->genpd.name = desc->names[i]; + pd->genpd.power_off = sun20i_ppu_pd_power_off; + pd->genpd.power_on = sun20i_ppu_pd_power_on; + pd->base = base + PD_REGS_SIZE * i; + + ret = pm_genpd_init(&pd->genpd, NULL, sun20i_ppu_pd_is_on(pd)); + if (ret) { + dev_warn(dev, "Failed to add '%s' domain: %d\n", + pd->genpd.name, ret); + continue; + } + + ppu->domains[i] = &pd->genpd; + } + + ret = of_genpd_add_provider_onecell(dev->of_node, ppu); + if (ret) + dev_warn(dev, "Failed to add provider: %d\n", ret); + + return 0; +} + +static const char *const sun20i_d1_ppu_pd_names[] = { + "CPU", + "VE", + "DSP", +}; + +static const struct sun20i_ppu_desc sun20i_d1_ppu_desc = { + .names = sun20i_d1_ppu_pd_names, + .num_domains = ARRAY_SIZE(sun20i_d1_ppu_pd_names), +}; + +static const struct of_device_id sun20i_ppu_of_match[] = { + { + .compatible = "allwinner,sun20i-d1-ppu", + .data = &sun20i_d1_ppu_desc, + }, + { } +}; +MODULE_DEVICE_TABLE(of, sun20i_ppu_of_match); + +static struct platform_driver sun20i_ppu_driver = { + .probe = sun20i_ppu_probe, + .driver = { + .name = "sun20i-ppu", + .of_match_table = sun20i_ppu_of_match, + /* Power domains cannot be removed while they are in use. */ + .suppress_bind_attrs = true, + }, +}; +module_platform_driver(sun20i_ppu_driver); + +MODULE_AUTHOR("Samuel Holland "); +MODULE_DESCRIPTION("Allwinner D1 PPU power domain driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 9ec590a8a1bbf6610f72124ad79231f2c5875fc9 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 9 Jan 2023 17:12:42 +0100 Subject: soc: imx: imx8mp-blk-ctrl: set HDMI LCDIF panic read hurry level Same as done for both LCDIF interfaces in the MEDIA domain, set the panic priority of the LCDIF instance in the HDMI domain to the maximium NoC priority of 7 to minimize chances of display underflows. Signed-off-by: Lucas Stach Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/soc/imx/imx8mp-blk-ctrl.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c index 0629f64ef4f1..28458ed1793b 100644 --- a/drivers/soc/imx/imx8mp-blk-ctrl.c +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c @@ -300,6 +300,7 @@ static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = { #define HDMI_RTX_CLK_CTL3 0x70 #define HDMI_RTX_CLK_CTL4 0x80 #define HDMI_TX_CONTROL0 0x200 +#define HDMI_LCDIF_NOC_HURRY_MASK GENMASK(14, 12) static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain) @@ -316,6 +317,8 @@ static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc, regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11)); regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(4) | BIT(5) | BIT(6)); + regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, + FIELD_PREP(HDMI_LCDIF_NOC_HURRY_MASK, 7)); break; case IMX8MP_HDMIBLK_PD_PAI: regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17)); -- cgit v1.2.3 From c200774a6df47cfc1053334c98ab777563de5bd8 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 6 Oct 2022 13:58:16 +0200 Subject: soc: mediatek: Introduce mediatek-regulator-coupler driver This driver currently deals with GPU-SRAM regulator coupling, ensuring that the SRAM voltage is always between a specific range of distance to the GPU voltage, depending on the SoC, necessary in order to achieve system stability across the full range of supported GPU frequencies. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Dmitry Osipenko Reviewed-by: Alyssa Rosenzweig Link: https://lore.kernel.org/r/20221006115816.66853-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/Kconfig | 5 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-regulator-coupler.c | 159 +++++++++++++++++++++++++++ 3 files changed, 165 insertions(+) create mode 100644 drivers/soc/mediatek/mtk-regulator-coupler.c (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index 20c77152c282..d6b83a5508ca 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -44,6 +44,11 @@ config MTK_PMIC_WRAP on different MediaTek SoCs. The PMIC wrapper is a proprietary hardware to connect the PMIC. +config MTK_REGULATOR_COUPLER + bool "MediaTek SoC Regulator Coupler" if COMPILE_TEST + default ARCH_MEDIATEK + depends on REGULATOR + config MTK_SCPSYS bool "MediaTek SCPSYS Support" default ARCH_MEDIATEK diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 0e9e703c931a..8c0ddacbcde8 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o obj-$(CONFIG_MTK_DEVAPC) += mtk-devapc.o obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o +obj-$(CONFIG_MTK_REGULATOR_COUPLER) += mtk-regulator-coupler.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mtk-regulator-coupler.c b/drivers/soc/mediatek/mtk-regulator-coupler.c new file mode 100644 index 000000000000..ad2ed42aa697 --- /dev/null +++ b/drivers/soc/mediatek/mtk-regulator-coupler.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Voltage regulators coupler for MediaTek SoCs + * + * Copyright (C) 2022 Collabora, Ltd. + * Author: AngeloGioacchino Del Regno + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include + +#define to_mediatek_coupler(x) container_of(x, struct mediatek_regulator_coupler, coupler) + +struct mediatek_regulator_coupler { + struct regulator_coupler coupler; + struct regulator_dev *vsram_rdev; +}; + +/* + * We currently support only couples of not more than two vregs and + * modify the vsram voltage only when changing voltage of vgpu. + * + * This function is limited to the GPU<->SRAM voltages relationships. + */ +static int mediatek_regulator_balance_voltage(struct regulator_coupler *coupler, + struct regulator_dev *rdev, + suspend_state_t state) +{ + struct mediatek_regulator_coupler *mrc = to_mediatek_coupler(coupler); + int max_spread = rdev->constraints->max_spread[0]; + int vsram_min_uV = mrc->vsram_rdev->constraints->min_uV; + int vsram_max_uV = mrc->vsram_rdev->constraints->max_uV; + int vsram_target_min_uV, vsram_target_max_uV; + int min_uV = 0; + int max_uV = INT_MAX; + int ret; + + /* + * If the target device is on, setting the SRAM voltage directly + * is not supported as it scales through its coupled supply voltage. + * + * An exception is made in case the use_count is zero: this means + * that this is the first time we power up the SRAM regulator, which + * implies that the target device has yet to perform initialization + * and setting a voltage at that time is harmless. + */ + if (rdev == mrc->vsram_rdev) { + if (rdev->use_count == 0) + return regulator_do_balance_voltage(rdev, state, true); + + return -EPERM; + } + + ret = regulator_check_consumers(rdev, &min_uV, &max_uV, state); + if (ret < 0) + return ret; + + if (min_uV == 0) { + ret = regulator_get_voltage_rdev(rdev); + if (ret < 0) + return ret; + min_uV = ret; + } + + ret = regulator_check_voltage(rdev, &min_uV, &max_uV); + if (ret < 0) + return ret; + + /* + * If we're asked to set a voltage less than VSRAM min_uV, set + * the minimum allowed voltage on VSRAM, as in this case it is + * safe to ignore the max_spread parameter. + */ + vsram_target_min_uV = max(vsram_min_uV, min_uV + max_spread); + vsram_target_max_uV = min(vsram_max_uV, vsram_target_min_uV + max_spread); + + /* Make sure we're not out of range */ + vsram_target_min_uV = min(vsram_target_min_uV, vsram_max_uV); + + pr_debug("Setting voltage %d-%duV on %s (minuV %d)\n", + vsram_target_min_uV, vsram_target_max_uV, + rdev_get_name(mrc->vsram_rdev), min_uV); + + ret = regulator_set_voltage_rdev(mrc->vsram_rdev, vsram_target_min_uV, + vsram_target_max_uV, state); + if (ret) + return ret; + + /* The sram voltage is now balanced: update the target vreg voltage */ + return regulator_do_balance_voltage(rdev, state, true); +} + +static int mediatek_regulator_attach(struct regulator_coupler *coupler, + struct regulator_dev *rdev) +{ + struct mediatek_regulator_coupler *mrc = to_mediatek_coupler(coupler); + const char *rdev_name = rdev_get_name(rdev); + + /* + * If we're getting a coupling of more than two regulators here and + * this means that this is surely not a GPU<->SRAM couple: in that + * case, we may want to use another coupler implementation, if any, + * or the generic one: the regulator core will keep walking through + * the list of couplers when any .attach_regulator() cb returns 1. + */ + if (rdev->coupling_desc.n_coupled > 2) + return 1; + + if (strstr(rdev_name, "sram")) { + if (mrc->vsram_rdev) + return -EINVAL; + mrc->vsram_rdev = rdev; + } else if (!strstr(rdev_name, "vgpu") && !strstr(rdev_name, "Vgpu")) { + return 1; + } + + return 0; +} + +static int mediatek_regulator_detach(struct regulator_coupler *coupler, + struct regulator_dev *rdev) +{ + struct mediatek_regulator_coupler *mrc = to_mediatek_coupler(coupler); + + if (rdev == mrc->vsram_rdev) + mrc->vsram_rdev = NULL; + + return 0; +} + +static struct mediatek_regulator_coupler mediatek_coupler = { + .coupler = { + .attach_regulator = mediatek_regulator_attach, + .detach_regulator = mediatek_regulator_detach, + .balance_voltage = mediatek_regulator_balance_voltage, + }, +}; + +static int mediatek_regulator_coupler_init(void) +{ + if (!of_machine_is_compatible("mediatek,mt8183") && + !of_machine_is_compatible("mediatek,mt8186") && + !of_machine_is_compatible("mediatek,mt8192")) + return 0; + + return regulator_coupler_register(&mediatek_coupler.coupler); +} +arch_initcall(mediatek_regulator_coupler_init); + +MODULE_AUTHOR("AngeloGioacchino Del Regno "); +MODULE_DESCRIPTION("MediaTek Regulator Coupler driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 78ce3093f055a695bf1dbe1f30adf48b8b19772b Mon Sep 17 00:00:00 2001 From: "Roy-CW.Yeh" Date: Wed, 18 Jan 2023 11:15:09 +0800 Subject: soc: mediatek: mmsys: add support for MT8195 VPPSYS Add MT8195 VPPSYS0 and VPPSYS1 driver data. Signed-off-by: Roy-CW.Yeh Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230118031509.29834-5-moudy.ho@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mmsys.c | 22 ++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.h | 1 + 2 files changed, 23 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 297c810440f4..eb4c7e57896c 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -102,6 +102,16 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { .num_resets = 64, }; +static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data = { + .clk_driver = "clk-mt8195-vpp0", + .is_vppsys = true, +}; + +static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = { + .clk_driver = "clk-mt8195-vpp1", + .is_vppsys = true, +}; + static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { .clk_driver = "clk-mt8365-mm", .routes = mt8365_mmsys_routing_table, @@ -333,6 +343,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev) if (IS_ERR(clks)) return PTR_ERR(clks); + if (mmsys->data->is_vppsys) + goto out_probe_done; + drm = platform_device_register_data(&pdev->dev, "mediatek-drm", PLATFORM_DEVID_AUTO, NULL, 0); if (IS_ERR(drm)) { @@ -340,6 +353,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev) return PTR_ERR(drm); } +out_probe_done: return 0; } @@ -396,6 +410,14 @@ static const struct of_device_id of_match_mtk_mmsys[] = { .compatible = "mediatek,mt8195-vdosys1", .data = &mt8195_vdosys1_driver_data, }, + { + .compatible = "mediatek,mt8195-vppsys0", + .data = &mt8195_vppsys0_driver_data, + }, + { + .compatible = "mediatek,mt8195-vppsys1", + .data = &mt8195_vppsys1_driver_data, + }, { .compatible = "mediatek,mt8365-mmsys", .data = &mt8365_mmsys_driver_data, diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index e19994749adb..56f8cc3a97b7 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data { const unsigned int num_routes; const u16 sw0_rst_offset; const u32 num_resets; + const bool is_vppsys; }; /* -- cgit v1.2.3 From 0ad2185dcb5ed3f3c26be8262e4180d5d97f244f Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 30 Jan 2023 10:49:01 +0100 Subject: soc: sunxi: select CONFIG_PM Selecting CONFIG_PM_GENERIC_DOMAINS without CONFIG_PM leads to a build failure: WARNING: unmet direct dependencies detected for PM_GENERIC_DOMAINS Depends on [n]: PM [=n] Selected by [y]: - SUN20I_PPU [=y] && (ARCH_SUNXI [=n] || COMPILE_TEST [=y]) drivers/base/power/domain_governor.c: In function 'default_suspend_ok': drivers/base/power/domain_governor.c:85:24: error: 'struct dev_pm_info' has no member named 'ignore_children' 85 | if (!dev->power.ignore_children) | ^ drivers/base/power/domain.c: In function 'genpd_queue_power_off_work': drivers/base/power/domain.c:657:20: error: 'pm_wq' undeclared (first use in this function) 657 | queue_work(pm_wq, &genpd->power_off_work); | ^~~~~ Unfortunately platforms are inconsistent between using 'select PM' and 'depends on PM' here. CONFIG_PM is a user-visible symbol, so in principle we should be using 'depends on', but on the other hand using 'select' here is more common among drivers/soc. Go with the majority for now, as this has a smaller risk of introducing circular dependencies. We may need to clean this up for consistency later. Fixes: 0e30ca5ab0a8 ("soc: sunxi: Add Allwinner D1 PPU driver") Acked-by: Jernej Skrabec Signed-off-by: Arnd Bergmann --- drivers/soc/sunxi/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/sunxi/Kconfig b/drivers/soc/sunxi/Kconfig index 29e9ba2d520d..02d0b338feb3 100644 --- a/drivers/soc/sunxi/Kconfig +++ b/drivers/soc/sunxi/Kconfig @@ -23,6 +23,7 @@ config SUNXI_SRAM config SUN20I_PPU bool "Allwinner D1 PPU power domain driver" depends on ARCH_SUNXI || COMPILE_TEST + select PM select PM_GENERIC_DOMAINS help Say y to enable the PPU power domain driver. This saves power -- cgit v1.2.3 From c5d52d7bf241a4d06b651362446644948621c426 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 30 Jan 2023 20:30:54 -0600 Subject: soc: qcom: dcc: Drop driver for now Arnd asks for the DCC driver to be dropped for now, in order to allow for more thorough review, by a wider audience, of the ABI introduced. The Devicetree binding is adequately describing the hardware block, so this is kept. Requested-by: Arnd Bergmann Signed-off-by: Bjorn Andersson --- MAINTAINERS | 8 - drivers/soc/qcom/Kconfig | 8 - drivers/soc/qcom/Makefile | 1 - drivers/soc/qcom/dcc.c | 1300 --------------------------------------------- 4 files changed, 1317 deletions(-) delete mode 100644 drivers/soc/qcom/dcc.c (limited to 'drivers/soc') diff --git a/MAINTAINERS b/MAINTAINERS index f2c3d471fe8f..f61eb221415b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5821,14 +5821,6 @@ W: http://lists.twibble.org/mailman/listinfo/dc395x/ F: Documentation/scsi/dc395x.rst F: drivers/scsi/dc395x.* -DCC QTI DRIVER -M: Souradeep Chowdhury -L: linux-arm-msm@vger.kernel.org -S: Maintained -F: Documentation/ABI/testing/debugfs-driver-dcc -F: Documentation/devicetree/bindings/soc/qcom/qcom,dcc.yaml -F: drivers/soc/qcom/dcc.c - DCCP PROTOCOL L: dccp@vger.kernel.org S: Orphan diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 21c4ce2315ba..df46108e58ce 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -70,14 +70,6 @@ config QCOM_LLCC SDM845. This provides interfaces to clients that use the LLCC. Say yes here to enable LLCC slice driver. -config QCOM_DCC - tristate "Qualcomm Technologies, Inc. Data Capture and Compare(DCC) engine driver" - depends on ARCH_QCOM || COMPILE_TEST - help - This option enables driver for Data Capture and Compare engine. DCC - driver provides interface to configure DCC block and read back - captured data from DCC's internal SRAM. - config QCOM_KRYO_L2_ACCESSORS bool depends on ARCH_QCOM && ARM64 || COMPILE_TEST diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 3b92c6c8e0ec..6e02333c4080 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -4,7 +4,6 @@ obj-$(CONFIG_QCOM_AOSS_QMP) += qcom_aoss.o obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o obj-$(CONFIG_QCOM_CPR) += cpr.o -obj-$(CONFIG_QCOM_DCC) += dcc.o obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o obj-$(CONFIG_QCOM_OCMEM) += ocmem.o diff --git a/drivers/soc/qcom/dcc.c b/drivers/soc/qcom/dcc.c deleted file mode 100644 index 5b50d638771d..000000000000 --- a/drivers/soc/qcom/dcc.c +++ /dev/null @@ -1,1300 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define STATUS_READY_TIMEOUT 5000 /* microseconds */ - -#define DCC_SRAM_NODE "dcc_sram" - -/* DCC registers */ -#define DCC_HW_INFO 0x04 -#define DCC_LL_NUM_INFO 0x10 -#define DCC_STATUS(vers) ((vers) == 1 ? 0x0c : 0x1c) -#define DCC_LL_LOCK 0x00 -#define DCC_LL_CFG 0x04 -#define DCC_LL_BASE 0x08 -#define DCC_FD_BASE 0x0c -#define DCC_LL_TIMEOUT 0x10 -#define DCC_LL_INT_ENABLE 0x18 -#define DCC_LL_INT_STATUS 0x1c -#define DCC_LL_SW_TRIGGER 0x2c -#define DCC_LL_BUS_ACCESS_STATUS 0x30 - -/* Default value used if a bit 6 in the HW_INFO register is set. */ -#define DCC_FIX_LOOP_OFFSET 16 - -/* Mask to find version info from HW_Info register */ -#define DCC_VER_INFO_MASK BIT(9) - -#define MAX_DCC_OFFSET GENMASK(9, 2) -#define MAX_DCC_LEN GENMASK(6, 0) -#define MAX_LOOP_CNT GENMASK(7, 0) -#define MAX_LOOP_ADDR 10 - -#define DCC_ADDR_DESCRIPTOR 0x00 -#define DCC_ADDR_LIMIT 27 -#define DCC_WORD_SIZE sizeof(u32) -#define DCC_ADDR_RANGE_MASK GENMASK(31, 4) -#define DCC_LOOP_DESCRIPTOR BIT(30) -#define DCC_RD_MOD_WR_DESCRIPTOR BIT(31) -#define DCC_LINK_DESCRIPTOR GENMASK(31, 30) -#define DCC_STATUS_MASK GENMASK(1, 0) -#define DCC_LOCK_MASK BIT(0) -#define DCC_LOOP_OFFSET_MASK BIT(6) -#define DCC_TRIGGER_MASK BIT(9) - -#define DCC_WRITE_MASK BIT(15) -#define DCC_WRITE_OFF_MASK GENMASK(7, 0) -#define DCC_WRITE_LEN_MASK GENMASK(14, 8) - -#define DCC_READ_IND 0x00 -#define DCC_WRITE_IND (BIT(28)) - -#define DCC_AHB_IND 0x00 -#define DCC_APB_IND BIT(29) - -#define DCC_MAX_LINK_LIST 8 - -#define DCC_VER_MASK2 GENMASK(5, 0) - -#define DCC_SRAM_WORD_LENGTH 4 - -#define DCC_RD_MOD_WR_ADDR 0xc105e - -enum dcc_descriptor_type { - DCC_READ_TYPE, - DCC_LOOP_TYPE, - DCC_READ_WRITE_TYPE, - DCC_WRITE_TYPE -}; - -struct dcc_config_entry { - u32 base; - u32 offset; - u32 len; - u32 loop_cnt; - u32 write_val; - u32 mask; - bool apb_bus; - enum dcc_descriptor_type desc_type; - struct list_head list; -}; - -/** - * struct dcc_drvdata - configuration information related to a dcc device - * @base: Base Address of the dcc device - * @dev: The device attached to the driver data - * @mutex: Lock to protect access and manipulation of dcc_drvdata - * @ram_base: Base address for the SRAM dedicated for the dcc device - * @ram_size: Total size of the SRAM dedicated for the dcc device - * @ram_offset: Offset to the SRAM dedicated for dcc device - * @mem_map_ver: Memory map version of DCC hardware - * @ram_cfg: Used for address limit calculation for dcc - * @ram_start: Starting address of DCC SRAM - * @sram_dev: Miscellaneous device equivalent of dcc SRAM - * @cfg_head: Points to the head of the linked list of addresses - * @dbg_dir: The dcc debugfs directory under which all the debugfs files are placed - * @nr_link_list: Total number of linkedlists supported by the DCC configuration - * @loop_shift: Loop offset bits range for the addresses - * @enable_bitmap: Bitmap to capture the enabled status of each linked list of addresses - */ -struct dcc_drvdata { - void __iomem *base; - void __iomem *ram_base; - struct device *dev; - struct mutex mutex; - size_t ram_size; - size_t ram_offset; - int mem_map_ver; - unsigned int ram_cfg; - unsigned int ram_start; - struct miscdevice sram_dev; - struct list_head *cfg_head; - struct dentry *dbg_dir; - size_t nr_link_list; - u8 loop_shift; - unsigned long *enable_bitmap; -}; - -struct dcc_cfg_attr { - u32 addr; - u32 prev_addr; - u32 prev_off; - u32 link; - u32 sram_offset; -}; - -struct dcc_cfg_loop_attr { - u32 loop_cnt; - u32 loop_len; - u32 loop_off; - bool loop_start; -}; - -static inline u32 dcc_list_offset(int version) -{ - return version == 1 ? 0x1c : version == 2 ? 0x2c : 0x34; -} - -static inline void dcc_list_writel(struct dcc_drvdata *drvdata, - u32 ll, u32 val, u32 off) -{ - u32 offset = dcc_list_offset(drvdata->mem_map_ver) + off; - - writel(val, drvdata->base + ll * 0x80 + offset); -} - -static inline u32 dcc_list_readl(struct dcc_drvdata *drvdata, u32 ll, u32 off) -{ - u32 offset = dcc_list_offset(drvdata->mem_map_ver) + off; - - return readl(drvdata->base + ll * 0x80 + offset); -} - -static void dcc_sram_write_auto(struct dcc_drvdata *drvdata, - u32 val, u32 *off) -{ - /* If the overflow condition is met increment the offset - * and return to indicate that overflow has occurred - */ - if (unlikely(*off > drvdata->ram_size - 4)) { - *off += 4; - return; - } - - writel(val, drvdata->ram_base + *off); - - *off += 4; -} - -static int dcc_sw_trigger(struct dcc_drvdata *drvdata) -{ - void __iomem *addr; - int ret = 0; - int i; - u32 status; - u32 ll_cfg; - u32 tmp_ll_cfg; - u32 val; - - mutex_lock(&drvdata->mutex); - - for (i = 0; i < drvdata->nr_link_list; i++) { - if (!test_bit(i, drvdata->enable_bitmap)) - continue; - ll_cfg = dcc_list_readl(drvdata, i, DCC_LL_CFG); - tmp_ll_cfg = ll_cfg & ~DCC_TRIGGER_MASK; - dcc_list_writel(drvdata, tmp_ll_cfg, i, DCC_LL_CFG); - dcc_list_writel(drvdata, 1, i, DCC_LL_SW_TRIGGER); - dcc_list_writel(drvdata, ll_cfg, i, DCC_LL_CFG); - } - - addr = drvdata->base + DCC_STATUS(drvdata->mem_map_ver); - if (readl_poll_timeout(addr, val, !FIELD_GET(DCC_STATUS_MASK, val), - 1, STATUS_READY_TIMEOUT)) { - dev_err(drvdata->dev, "DCC is busy after receiving sw trigger\n"); - ret = -EBUSY; - goto out_unlock; - } - - for (i = 0; i < drvdata->nr_link_list; i++) { - if (!test_bit(i, drvdata->enable_bitmap)) - continue; - - status = dcc_list_readl(drvdata, i, DCC_LL_BUS_ACCESS_STATUS); - if (!status) - continue; - - dev_err(drvdata->dev, "Read access error for list %d err: 0x%x\n", - i, status); - ll_cfg = dcc_list_readl(drvdata, i, DCC_LL_CFG); - tmp_ll_cfg = ll_cfg & ~DCC_TRIGGER_MASK; - dcc_list_writel(drvdata, tmp_ll_cfg, i, DCC_LL_CFG); - dcc_list_writel(drvdata, DCC_STATUS_MASK, i, DCC_LL_BUS_ACCESS_STATUS); - dcc_list_writel(drvdata, ll_cfg, i, DCC_LL_CFG); - ret = -ENODATA; - break; - } - -out_unlock: - mutex_unlock(&drvdata->mutex); - return ret; -} - -static void dcc_ll_cfg_reset_link(struct dcc_cfg_attr *cfg) -{ - cfg->addr = 0x00; - cfg->link = 0; - cfg->prev_off = 0; - cfg->prev_addr = cfg->addr; -} - -static void dcc_emit_read_write(struct dcc_drvdata *drvdata, - struct dcc_config_entry *entry, - struct dcc_cfg_attr *cfg) -{ - if (cfg->link) { - /* - * write new offset = 1 to continue - * processing the list - */ - - dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); - - /* Reset link and prev_off */ - dcc_ll_cfg_reset_link(cfg); - } - - cfg->addr = DCC_RD_MOD_WR_DESCRIPTOR; - dcc_sram_write_auto(drvdata, cfg->addr, &cfg->sram_offset); - - dcc_sram_write_auto(drvdata, entry->mask, &cfg->sram_offset); - - dcc_sram_write_auto(drvdata, entry->write_val, &cfg->sram_offset); - - cfg->addr = 0; -} - -static void dcc_emit_loop(struct dcc_drvdata *drvdata, struct dcc_config_entry *entry, - struct dcc_cfg_attr *cfg, - struct dcc_cfg_loop_attr *cfg_loop, - u32 *total_len) -{ - int loop; - - /* Check if we need to write link of prev entry */ - if (cfg->link) - dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); - - if (cfg_loop->loop_start) { - loop = (cfg->sram_offset - cfg_loop->loop_off) / 4; - loop |= (cfg_loop->loop_cnt << drvdata->loop_shift) & - GENMASK(DCC_ADDR_LIMIT, drvdata->loop_shift); - loop |= DCC_LOOP_DESCRIPTOR; - *total_len += (*total_len - cfg_loop->loop_len) * cfg_loop->loop_cnt; - - dcc_sram_write_auto(drvdata, loop, &cfg->sram_offset); - - cfg_loop->loop_start = false; - cfg_loop->loop_len = 0; - cfg_loop->loop_off = 0; - } else { - cfg_loop->loop_start = true; - cfg_loop->loop_cnt = entry->loop_cnt - 1; - cfg_loop->loop_len = *total_len; - cfg_loop->loop_off = cfg->sram_offset; - } - - /* Reset link and prev_off */ - dcc_ll_cfg_reset_link(cfg); -} - -static void dcc_emit_write(struct dcc_drvdata *drvdata, - struct dcc_config_entry *entry, - struct dcc_cfg_attr *cfg) -{ - u32 off; - - if (cfg->link) { - /* - * write new offset = 1 to continue - * processing the list - */ - dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); - - /* Reset link and prev_off */ - cfg->addr = 0x00; - cfg->prev_off = 0; - cfg->prev_addr = cfg->addr; - } - - off = entry->offset / 4; - /* write new offset-length pair to correct position */ - cfg->link |= ((off & DCC_WRITE_OFF_MASK) | DCC_WRITE_MASK | - FIELD_PREP(DCC_WRITE_LEN_MASK, entry->len)); - cfg->link |= DCC_LINK_DESCRIPTOR; - - /* Address type */ - cfg->addr = (entry->base >> 4) & GENMASK(DCC_ADDR_LIMIT, 0); - if (entry->apb_bus) - cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_APB_IND; - else - cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_AHB_IND; - dcc_sram_write_auto(drvdata, cfg->addr, &cfg->sram_offset); - - dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); - - dcc_sram_write_auto(drvdata, entry->write_val, &cfg->sram_offset); - - cfg->addr = 0x00; - cfg->link = 0; -} - -static int dcc_emit_read(struct dcc_drvdata *drvdata, - struct dcc_config_entry *entry, - struct dcc_cfg_attr *cfg, - u32 *pos, u32 *total_len) -{ - u32 off; - u32 temp_off; - - cfg->addr = (entry->base >> 4) & GENMASK(27, 0); - - if (entry->apb_bus) - cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_APB_IND; - else - cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_AHB_IND; - - off = entry->offset / 4; - - *total_len += entry->len * 4; - - if (!cfg->prev_addr || cfg->prev_addr != cfg->addr || cfg->prev_off > off) { - /* Check if we need to write prev link entry */ - if (cfg->link) - dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); - dev_dbg(drvdata->dev, "DCC: sram address 0x%x\n", cfg->sram_offset); - - /* Write address */ - dcc_sram_write_auto(drvdata, cfg->addr, &cfg->sram_offset); - - /* Reset link and prev_off */ - cfg->link = 0; - cfg->prev_off = 0; - } - - if ((off - cfg->prev_off) > 0xff || entry->len > MAX_DCC_LEN) { - dev_err(drvdata->dev, "DCC: Programming error Base: 0x%x, offset 0x%x\n", - entry->base, entry->offset); - return -EINVAL; - } - - if (cfg->link) { - /* - * link already has one offset-length so new - * offset-length needs to be placed at - * bits [29:15] - */ - *pos = 15; - - /* Clear bits [31:16] */ - cfg->link &= GENMASK(14, 0); - } else { - /* - * link is empty, so new offset-length needs - * to be placed at bits [15:0] - */ - *pos = 0; - cfg->link = 1 << 15; - } - - /* write new offset-length pair to correct position */ - temp_off = (off - cfg->prev_off) & GENMASK(7, 0); - cfg->link |= temp_off | ((entry->len << 8) & GENMASK(14, 8)) << *pos; - - cfg->link |= DCC_LINK_DESCRIPTOR; - - if (*pos) { - dcc_sram_write_auto(drvdata, cfg->link, &cfg->sram_offset); - cfg->link = 0; - } - - cfg->prev_off = off + entry->len - 1; - cfg->prev_addr = cfg->addr; - return 0; -} - -static int dcc_emit_config(struct dcc_drvdata *drvdata, unsigned int curr_list) -{ - int ret; - u32 total_len, pos; - struct dcc_config_entry *entry; - struct dcc_cfg_attr cfg; - struct dcc_cfg_loop_attr cfg_loop; - - memset(&cfg, 0, sizeof(cfg)); - memset(&cfg_loop, 0, sizeof(cfg_loop)); - cfg.sram_offset = drvdata->ram_cfg * 4; - total_len = 0; - - list_for_each_entry(entry, &drvdata->cfg_head[curr_list], list) { - switch (entry->desc_type) { - case DCC_READ_WRITE_TYPE: - dcc_emit_read_write(drvdata, entry, &cfg); - break; - - case DCC_LOOP_TYPE: - dcc_emit_loop(drvdata, entry, &cfg, &cfg_loop, &total_len); - break; - - case DCC_WRITE_TYPE: - dcc_emit_write(drvdata, entry, &cfg); - break; - - case DCC_READ_TYPE: - ret = dcc_emit_read(drvdata, entry, &cfg, &pos, &total_len); - if (ret) - goto err; - break; - } - } - - if (cfg.link) - dcc_sram_write_auto(drvdata, cfg.link, &cfg.sram_offset); - - if (cfg_loop.loop_start) { - dev_err(drvdata->dev, "DCC: Programming error: Loop unterminated\n"); - ret = -EINVAL; - goto err; - } - - /* Handling special case of list ending with a rd_mod_wr */ - if (cfg.addr == DCC_RD_MOD_WR_DESCRIPTOR) { - cfg.addr = (DCC_RD_MOD_WR_ADDR) & GENMASK(27, 0); - cfg.addr |= DCC_ADDR_DESCRIPTOR; - dcc_sram_write_auto(drvdata, cfg.addr, &cfg.sram_offset); - } - - /* Setting zero to indicate end of the list */ - cfg.link = DCC_LINK_DESCRIPTOR; - dcc_sram_write_auto(drvdata, cfg.link, &cfg.sram_offset); - - /* Check if sram offset exceeds the ram size */ - if (cfg.sram_offset > drvdata->ram_size) - goto overstep; - - /* Update ram_cfg and check if the data will overstep */ - drvdata->ram_cfg = (cfg.sram_offset + total_len) / 4; - - if (cfg.sram_offset + total_len > drvdata->ram_size) { - cfg.sram_offset += total_len; - goto overstep; - } - - drvdata->ram_start = cfg.sram_offset / 4; - return 0; -overstep: - ret = -EINVAL; - memset_io(drvdata->ram_base, 0, drvdata->ram_size); - -err: - return ret; -} - -static bool dcc_valid_list(struct dcc_drvdata *drvdata, unsigned int curr_list) -{ - u32 lock_reg; - - if (list_empty(&drvdata->cfg_head[curr_list])) - return false; - - if (test_bit(curr_list, drvdata->enable_bitmap)) { - dev_err(drvdata->dev, "List %d is already enabled\n", curr_list); - return false; - } - - lock_reg = dcc_list_readl(drvdata, curr_list, DCC_LL_LOCK); - if (lock_reg & DCC_LOCK_MASK) { - dev_err(drvdata->dev, "List %d is already locked\n", curr_list); - return false; - } - - return true; -} - -static bool is_dcc_enabled(struct dcc_drvdata *drvdata) -{ - int list; - - for (list = 0; list < drvdata->nr_link_list; list++) - if (test_bit(list, drvdata->enable_bitmap)) - return true; - - return false; -} - -static int dcc_enable(struct dcc_drvdata *drvdata, unsigned int curr_list) -{ - int ret; - u32 ram_cfg_base; - - mutex_lock(&drvdata->mutex); - - if (!dcc_valid_list(drvdata, curr_list)) { - ret = -EINVAL; - goto out_unlock; - } - - /* Fill dcc sram with the poison value. - * This helps in understanding bus - * hang from registers returning a zero - */ - if (!is_dcc_enabled(drvdata)) - memset_io(drvdata->ram_base, 0xde, drvdata->ram_size); - - /* 1. Take ownership of the list */ - dcc_list_writel(drvdata, DCC_LOCK_MASK, curr_list, DCC_LL_LOCK); - - /* 2. Program linked-list in the SRAM */ - ram_cfg_base = drvdata->ram_cfg; - ret = dcc_emit_config(drvdata, curr_list); - if (ret) { - dcc_list_writel(drvdata, 0, curr_list, DCC_LL_LOCK); - goto out_unlock; - } - - /* 3. Program DCC_RAM_CFG reg */ - dcc_list_writel(drvdata, ram_cfg_base + - drvdata->ram_offset / 4, curr_list, DCC_LL_BASE); - dcc_list_writel(drvdata, drvdata->ram_start + - drvdata->ram_offset / 4, curr_list, DCC_FD_BASE); - dcc_list_writel(drvdata, 0xFFF, curr_list, DCC_LL_TIMEOUT); - - /* 4. Clears interrupt status register */ - dcc_list_writel(drvdata, 0, curr_list, DCC_LL_INT_ENABLE); - dcc_list_writel(drvdata, (BIT(0) | BIT(1) | BIT(2)), - curr_list, DCC_LL_INT_STATUS); - - set_bit(curr_list, drvdata->enable_bitmap); - - /* 5. Configure trigger */ - dcc_list_writel(drvdata, DCC_TRIGGER_MASK, - curr_list, DCC_LL_CFG); - -out_unlock: - mutex_unlock(&drvdata->mutex); - return ret; -} - -static void dcc_disable(struct dcc_drvdata *drvdata, int curr_list) -{ - mutex_lock(&drvdata->mutex); - - if (!test_bit(curr_list, drvdata->enable_bitmap)) - goto out_unlock; - dcc_list_writel(drvdata, 0, curr_list, DCC_LL_CFG); - dcc_list_writel(drvdata, 0, curr_list, DCC_LL_BASE); - dcc_list_writel(drvdata, 0, curr_list, DCC_FD_BASE); - dcc_list_writel(drvdata, 0, curr_list, DCC_LL_LOCK); - clear_bit(curr_list, drvdata->enable_bitmap); -out_unlock: - mutex_unlock(&drvdata->mutex); -} - -static u32 dcc_filp_curr_list(const struct file *filp) -{ - struct dentry *dentry = file_dentry(filp); - int curr_list, ret; - - ret = kstrtoint(dentry->d_parent->d_name.name, 0, &curr_list); - if (ret) - return ret; - - return curr_list; -} - -static ssize_t enable_read(struct file *filp, char __user *userbuf, - size_t count, loff_t *ppos) -{ - char *buf; - struct dcc_drvdata *drvdata = filp->private_data; - - mutex_lock(&drvdata->mutex); - - if (is_dcc_enabled(drvdata)) - buf = "Y\n"; - else - buf = "N\n"; - - mutex_unlock(&drvdata->mutex); - - return simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf)); -} - -static ssize_t enable_write(struct file *filp, const char __user *userbuf, - size_t count, loff_t *ppos) -{ - int ret = 0, curr_list; - bool val; - struct dcc_drvdata *drvdata = filp->private_data; - - curr_list = dcc_filp_curr_list(filp); - if (curr_list < 0) - return curr_list; - - ret = kstrtobool_from_user(userbuf, count, &val); - if (ret < 0) - return ret; - - if (val) { - ret = dcc_enable(drvdata, curr_list); - if (ret) - return ret; - } else { - dcc_disable(drvdata, curr_list); - } - - return count; -} - -static const struct file_operations enable_fops = { - .read = enable_read, - .write = enable_write, - .open = simple_open, - .llseek = generic_file_llseek, -}; - -static ssize_t trigger_write(struct file *filp, - const char __user *user_buf, size_t count, - loff_t *ppos) -{ - int ret; - unsigned int val; - struct dcc_drvdata *drvdata = filp->private_data; - - ret = kstrtouint_from_user(user_buf, count, 0, &val); - if (ret < 0) - return ret; - - if (val != 1) - return -EINVAL; - - ret = dcc_sw_trigger(drvdata); - if (ret < 0) - return ret; - - return count; -} - -static const struct file_operations trigger_fops = { - .write = trigger_write, - .open = simple_open, - .llseek = generic_file_llseek, -}; - -static int dcc_config_add(struct dcc_drvdata *drvdata, unsigned int addr, - unsigned int len, bool apb_bus, int curr_list) -{ - int ret = 0; - struct dcc_config_entry *entry, *pentry; - unsigned int base, offset; - - mutex_lock(&drvdata->mutex); - - if (!len || len > drvdata->ram_size / DCC_WORD_SIZE) { - dev_err(drvdata->dev, "DCC: Invalid length\n"); - ret = -EINVAL; - goto out_unlock; - } - - base = addr & DCC_ADDR_RANGE_MASK; - - if (!list_empty(&drvdata->cfg_head[curr_list])) { - pentry = list_last_entry(&drvdata->cfg_head[curr_list], - struct dcc_config_entry, list); - - if (pentry->desc_type == DCC_READ_TYPE && - addr >= (pentry->base + pentry->offset) && - addr <= (pentry->base + pentry->offset + MAX_DCC_OFFSET)) { - /* Re-use base address from last entry */ - base = pentry->base; - - if ((pentry->len * 4 + pentry->base + pentry->offset) - == addr) { - len += pentry->len; - - if (len > MAX_DCC_LEN) - pentry->len = MAX_DCC_LEN; - else - pentry->len = len; - - addr = pentry->base + pentry->offset + - pentry->len * 4; - len -= pentry->len; - } - } - } - - offset = addr - base; - - while (len) { - entry = kzalloc(sizeof(*entry), GFP_KERNEL); - if (!entry) { - ret = -ENOMEM; - goto out_unlock; - } - - entry->base = base; - entry->offset = offset; - entry->len = min_t(u32, len, MAX_DCC_LEN); - entry->desc_type = DCC_READ_TYPE; - entry->apb_bus = apb_bus; - INIT_LIST_HEAD(&entry->list); - list_add_tail(&entry->list, &drvdata->cfg_head[curr_list]); - - len -= entry->len; - offset += MAX_DCC_LEN * 4; - } - -out_unlock: - mutex_unlock(&drvdata->mutex); - return ret; -} - -static ssize_t dcc_config_add_read(struct dcc_drvdata *drvdata, char *buf, int curr_list) -{ - bool bus; - int len, nval; - unsigned int base; - char apb_bus[4]; - - nval = sscanf(buf, "%x %i %3s", &base, &len, apb_bus); - if (nval <= 0 || nval > 3) - return -EINVAL; - - if (nval == 1) { - len = 1; - bus = false; - } else if (nval == 2) { - bus = false; - } else if (!strcmp("apb", apb_bus)) { - bus = true; - } else if (!strcmp("ahb", apb_bus)) { - bus = false; - } else { - return -EINVAL; - } - - return dcc_config_add(drvdata, base, len, bus, curr_list); -} - -static void dcc_config_reset(struct dcc_drvdata *drvdata) -{ - struct dcc_config_entry *entry, *temp; - int curr_list; - - mutex_lock(&drvdata->mutex); - - for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) { - list_for_each_entry_safe(entry, temp, - &drvdata->cfg_head[curr_list], list) { - list_del(&entry->list); - kfree(entry); - } - } - drvdata->ram_start = 0; - drvdata->ram_cfg = 0; - mutex_unlock(&drvdata->mutex); -} - -static ssize_t config_reset_write(struct file *filp, - const char __user *user_buf, size_t count, - loff_t *ppos) -{ - unsigned int val; - int ret; - struct dcc_drvdata *drvdata = filp->private_data; - - ret = kstrtouint_from_user(user_buf, count, 0, &val); - if (ret < 0) - return ret; - - if (val) - dcc_config_reset(drvdata); - - return count; -} - -static const struct file_operations config_reset_fops = { - .write = config_reset_write, - .open = simple_open, - .llseek = generic_file_llseek, -}; - -static ssize_t ready_read(struct file *filp, char __user *userbuf, - size_t count, loff_t *ppos) -{ - int ret = 0; - char *buf; - struct dcc_drvdata *drvdata = filp->private_data; - - mutex_lock(&drvdata->mutex); - - if (!is_dcc_enabled(drvdata)) { - ret = -EINVAL; - goto out_unlock; - } - - if (!FIELD_GET(BIT(1), readl(drvdata->base + DCC_STATUS(drvdata->mem_map_ver)))) - buf = "Y\n"; - else - buf = "N\n"; -out_unlock: - mutex_unlock(&drvdata->mutex); - - if (ret < 0) - return -EINVAL; - else - return simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf) + 1); -} - -static const struct file_operations ready_fops = { - .read = ready_read, - .open = simple_open, - .llseek = generic_file_llseek, -}; - -static int dcc_add_loop(struct dcc_drvdata *drvdata, unsigned long loop_cnt, int curr_list) -{ - struct dcc_config_entry *entry; - - entry = kzalloc(sizeof(*entry), GFP_KERNEL); - if (!entry) - return -ENOMEM; - - entry->loop_cnt = min_t(u32, loop_cnt, MAX_LOOP_CNT); - entry->desc_type = DCC_LOOP_TYPE; - INIT_LIST_HEAD(&entry->list); - list_add_tail(&entry->list, &drvdata->cfg_head[curr_list]); - - return 0; -} - -static ssize_t dcc_config_add_loop(struct dcc_drvdata *drvdata, char *buf, int curr_list) -{ - int ret, i = 0; - char *token, *input; - char delim[2] = " "; - unsigned int val[MAX_LOOP_ADDR]; - - input = buf; - - while ((token = strsep(&input, delim)) && i < MAX_LOOP_ADDR) { - ret = kstrtoint(token, 0, &val[i++]); - if (ret) - return ret; - } - - if (token) { - dev_err(drvdata->dev, "Max limit %u of loop address exceeded", - MAX_LOOP_ADDR); - return -EINVAL; - } - - if (val[1] < 1 || val[1] > 8) - return -EINVAL; - - ret = dcc_add_loop(drvdata, val[0], curr_list); - if (ret) - return ret; - - for (i = 0; i < val[1]; i++) - dcc_config_add(drvdata, val[i + 2], 1, false, curr_list); - - return dcc_add_loop(drvdata, 1, curr_list); -} - -static int dcc_rd_mod_wr_add(struct dcc_drvdata *drvdata, unsigned int mask, - unsigned int val, int curr_list) -{ - int ret = 0; - struct dcc_config_entry *entry; - - mutex_lock(&drvdata->mutex); - - if (list_empty(&drvdata->cfg_head[curr_list])) { - dev_err(drvdata->dev, "DCC: No read address programmed\n"); - ret = -EPERM; - goto out_unlock; - } - - entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL); - if (!entry) { - ret = -ENOMEM; - goto out_unlock; - } - - entry->desc_type = DCC_READ_WRITE_TYPE; - entry->mask = mask; - entry->write_val = val; - list_add_tail(&entry->list, &drvdata->cfg_head[curr_list]); -out_unlock: - mutex_unlock(&drvdata->mutex); - return ret; -} - -static ssize_t dcc_config_add_read_write(struct dcc_drvdata *drvdata, char *buf, int curr_list) -{ - int ret; - int nval; - unsigned int addr, mask, val; - - nval = sscanf(buf, "%x %x %x", &addr, &mask, &val); - - if (nval <= 1 || nval > 3) - return -EINVAL; - - ret = dcc_config_add(drvdata, addr, 1, false, curr_list); - if (ret) - return ret; - - return dcc_rd_mod_wr_add(drvdata, mask, val, curr_list); -} - -static int dcc_add_write(struct dcc_drvdata *drvdata, unsigned int addr, - unsigned int write_val, int apb_bus, int curr_list) -{ - struct dcc_config_entry *entry; - - entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL); - if (!entry) - return -ENOMEM; - - entry->desc_type = DCC_WRITE_TYPE; - entry->base = addr & GENMASK(31, 4); - entry->offset = addr - entry->base; - entry->write_val = write_val; - entry->len = 1; - entry->apb_bus = apb_bus; - list_add_tail(&entry->list, &drvdata->cfg_head[curr_list]); - - return 0; -} - -static ssize_t dcc_config_add_write(struct dcc_drvdata *drvdata, char *buf, int curr_list) -{ - bool bus; - int nval; - unsigned int addr, write_val; - char apb_bus[4]; - - nval = sscanf(buf, "%x %x %3s", &addr, &write_val, apb_bus); - - if (nval <= 1 || nval > 3) - return -EINVAL; - - if (nval == 2) - bus = true; - - if (nval == 3) { - if (!strcmp("apb", apb_bus)) - bus = true; - else if (!strcmp("ahb", apb_bus)) - bus = false; - else - return -EINVAL; - } - - return dcc_add_write(drvdata, addr, write_val, bus, curr_list); -} - -static int config_show(struct seq_file *m, void *data) -{ - struct dcc_drvdata *drvdata = m->private; - struct dcc_config_entry *entry; - int index = 0, curr_list; - - curr_list = dcc_filp_curr_list(m->file); - if (curr_list < 0) - return curr_list; - - mutex_lock(&drvdata->mutex); - - list_for_each_entry(entry, &drvdata->cfg_head[curr_list], list) { - index++; - switch (entry->desc_type) { - case DCC_READ_WRITE_TYPE: - seq_printf(m, "RW mask: 0x%x, val: 0x%x\n index: 0x%x\n", - entry->mask, entry->write_val, index); - break; - case DCC_LOOP_TYPE: - seq_printf(m, "L index: 0x%x Loop: %d\n", index, entry->loop_cnt); - break; - case DCC_WRITE_TYPE: - seq_printf(m, "W Base:0x%x, Offset: 0x%x, val: 0x%x, APB: %d\n, Index: 0x%x\n", - entry->base, entry->offset, entry->write_val, entry->apb_bus, - index); - break; - case DCC_READ_TYPE: - seq_printf(m, "R Base:0x%x, Offset: 0x%x, len: 0x%x, APB: %d\n, Index: 0x%x\n", - entry->base, entry->offset, entry->len, entry->apb_bus, index); - } - } - mutex_unlock(&drvdata->mutex); - return 0; -} - -static int config_open(struct inode *inode, struct file *file) -{ - struct dcc_drvdata *drvdata = inode->i_private; - - return single_open(file, config_show, drvdata); -} - -static ssize_t config_write(struct file *filp, - const char __user *user_buf, size_t count, - loff_t *ppos) -{ - int ret, curr_list; - char *token, buf[50]; - char *bufp = buf; - char *delim = " "; - struct dcc_drvdata *drvdata = filp->private_data; - - if (count > sizeof(buf) || count == 0) - return -EINVAL; - - ret = copy_from_user(buf, user_buf, count); - if (ret) - return -EFAULT; - - curr_list = dcc_filp_curr_list(filp); - if (curr_list < 0) - return curr_list; - - if (buf[count - 1] == '\n') - buf[count - 1] = '\0'; - else - return -EINVAL; - - token = strsep(&bufp, delim); - - if (!strcmp("R", token)) { - ret = dcc_config_add_read(drvdata, bufp, curr_list); - } else if (!strcmp("W", token)) { - ret = dcc_config_add_write(drvdata, bufp, curr_list); - } else if (!strcmp("RW", token)) { - ret = dcc_config_add_read_write(drvdata, bufp, curr_list); - } else if (!strcmp("L", token)) { - ret = dcc_config_add_loop(drvdata, bufp, curr_list); - } else { - dev_err(drvdata->dev, "%s is not a correct input\n", token); - return -EINVAL; - } - - if (ret) - return ret; - - return count; -} - -static const struct file_operations config_fops = { - .open = config_open, - .read = seq_read, - .write = config_write, - .llseek = seq_lseek, - .release = single_release, -}; - -static void dcc_delete_debug_dir(struct dcc_drvdata *drvdata) -{ - debugfs_remove_recursive(drvdata->dbg_dir); -}; - -static void dcc_create_debug_dir(struct dcc_drvdata *drvdata) -{ - int i; - char list_num[10]; - struct dentry *list; - struct device *dev = drvdata->dev; - - drvdata->dbg_dir = debugfs_create_dir(dev_name(dev), NULL); - if (IS_ERR(drvdata->dbg_dir)) { - pr_err("can't create debugfs dir\n"); - return; - } - - for (i = 0; i <= drvdata->nr_link_list; i++) { - sprintf(list_num, "%d", i); - list = debugfs_create_dir(list_num, drvdata->dbg_dir); - debugfs_create_file("enable", 0600, list, drvdata, &enable_fops); - debugfs_create_file("config", 0600, list, drvdata, &config_fops); - } - - debugfs_create_file("trigger", 0200, drvdata->dbg_dir, drvdata, &trigger_fops); - debugfs_create_file("ready", 0400, drvdata->dbg_dir, drvdata, &ready_fops); - debugfs_create_file("config_reset", 0200, drvdata->dbg_dir, - drvdata, &config_reset_fops); -} - -static ssize_t dcc_sram_read(struct file *file, char __user *data, - size_t len, loff_t *ppos) -{ - struct dcc_drvdata *drvdata = container_of(file->private_data, struct dcc_drvdata, sram_dev); - unsigned char *buf; - - /* EOF check */ - if (*ppos >= drvdata->ram_size) - return 0; - - if ((*ppos + len) > drvdata->ram_size) - len = (drvdata->ram_size - *ppos); - - buf = kzalloc(len, GFP_KERNEL); - if (!buf) - return -ENOMEM; - - memcpy_fromio(buf, drvdata->ram_base + *ppos, len); - - if (copy_to_user(data, buf, len)) { - kfree(buf); - return -EFAULT; - } - - *ppos += len; - - kfree(buf); - - return len; -} - -static const struct file_operations dcc_sram_fops = { - .owner = THIS_MODULE, - .read = dcc_sram_read, - .llseek = no_llseek, -}; - -static int dcc_sram_dev_init(struct dcc_drvdata *drvdata) -{ - drvdata->sram_dev.minor = MISC_DYNAMIC_MINOR; - drvdata->sram_dev.name = DCC_SRAM_NODE; - drvdata->sram_dev.fops = &dcc_sram_fops; - - return misc_register(&drvdata->sram_dev); -} - -static void dcc_sram_dev_exit(struct dcc_drvdata *drvdata) -{ - misc_deregister(&drvdata->sram_dev); -} - -static int dcc_probe(struct platform_device *pdev) -{ - u32 val; - int ret = 0, i; - struct device *dev = &pdev->dev; - struct dcc_drvdata *drvdata; - struct resource *res; - - drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); - if (!drvdata) - return -ENOMEM; - - drvdata->dev = &pdev->dev; - platform_set_drvdata(pdev, drvdata); - - drvdata->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(drvdata->base)) - return PTR_ERR(drvdata->base); - - drvdata->ram_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); - if (IS_ERR(drvdata->ram_base)) - return PTR_ERR(drvdata->ram_base); - - drvdata->ram_size = resource_size(res); - - drvdata->ram_offset = (size_t)of_device_get_match_data(&pdev->dev); - - val = readl(drvdata->base + DCC_HW_INFO); - - if (FIELD_GET(DCC_VER_INFO_MASK, val)) { - drvdata->mem_map_ver = 3; - drvdata->nr_link_list = readl(drvdata->base + DCC_LL_NUM_INFO); - if (!drvdata->nr_link_list) - return -EINVAL; - } else if ((val & DCC_VER_MASK2) == DCC_VER_MASK2) { - drvdata->mem_map_ver = 2; - drvdata->nr_link_list = readl(drvdata->base + DCC_LL_NUM_INFO); - if (!drvdata->nr_link_list) - return -EINVAL; - } else { - drvdata->mem_map_ver = 1; - drvdata->nr_link_list = DCC_MAX_LINK_LIST; - } - - /* Either set the fixed loop offset or calculate - * it from the total number of words in dcc_sram. - * Max consecutive addresses dcc can loop is - * equivalent to the words in dcc_sram. - */ - if (val & DCC_LOOP_OFFSET_MASK) - drvdata->loop_shift = DCC_FIX_LOOP_OFFSET; - else - drvdata->loop_shift = get_bitmask_order((drvdata->ram_offset + - drvdata->ram_size) / DCC_SRAM_WORD_LENGTH - 1); - - mutex_init(&drvdata->mutex); - - drvdata->enable_bitmap = devm_kcalloc(dev, BITS_TO_LONGS(drvdata->nr_link_list), - sizeof(*drvdata->enable_bitmap), GFP_KERNEL); - if (!drvdata->enable_bitmap) - return -ENOMEM; - - drvdata->cfg_head = devm_kcalloc(dev, drvdata->nr_link_list, - sizeof(*drvdata->cfg_head), GFP_KERNEL); - if (!drvdata->cfg_head) - return -ENOMEM; - - for (i = 0; i < drvdata->nr_link_list; i++) - INIT_LIST_HEAD(&drvdata->cfg_head[i]); - - ret = dcc_sram_dev_init(drvdata); - if (ret) { - dev_err(drvdata->dev, "DCC: sram node not registered.\n"); - return ret; - } - - dcc_create_debug_dir(drvdata); - - return 0; -} - -static int dcc_remove(struct platform_device *pdev) -{ - struct dcc_drvdata *drvdata = platform_get_drvdata(pdev); - - dcc_delete_debug_dir(drvdata); - dcc_sram_dev_exit(drvdata); - dcc_config_reset(drvdata); - - return 0; -} - -static const struct of_device_id dcc_match_table[] = { - { .compatible = "qcom,sc7180-dcc", .data = (void *)0x6000 }, - { .compatible = "qcom,sc7280-dcc", .data = (void *)0x12000 }, - { .compatible = "qcom,sdm845-dcc", .data = (void *)0x6000 }, - { .compatible = "qcom,sm8150-dcc", .data = (void *)0x5000 }, - { } -}; -MODULE_DEVICE_TABLE(of, dcc_match_table); - -static struct platform_driver dcc_driver = { - .probe = dcc_probe, - .remove = dcc_remove, - .driver = { - .name = "qcom-dcc", - .of_match_table = dcc_match_table, - }, -}; -module_platform_driver(dcc_driver); - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("Qualcomm Technologies Inc. DCC driver"); -- cgit v1.2.3 From 40eaa8c0cbba4a27668c7e01373ccd5b38381e2f Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Mon, 23 Jan 2023 15:53:54 +0900 Subject: soc: apple: rtkit: Add apple_rtkit_idle() function This is yet another low power mode, used by DCP. Reviewed-by: Eric Curtin Reviewed-by: Sven Peter Signed-off-by: Hector Martin --- drivers/soc/apple/rtkit.c | 21 +++++++++++++++++++++ include/linux/soc/apple/rtkit.h | 5 +++++ 2 files changed, 26 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/apple/rtkit.c b/drivers/soc/apple/rtkit.c index 8ec74d7539eb..efb1fa77dff2 100644 --- a/drivers/soc/apple/rtkit.c +++ b/drivers/soc/apple/rtkit.c @@ -9,6 +9,7 @@ enum { APPLE_RTKIT_PWR_STATE_OFF = 0x00, /* power off, cannot be restarted */ APPLE_RTKIT_PWR_STATE_SLEEP = 0x01, /* sleeping, can be restarted */ + APPLE_RTKIT_PWR_STATE_IDLE = 0x201, /* sleeping, retain state */ APPLE_RTKIT_PWR_STATE_QUIESCED = 0x10, /* running but no communication */ APPLE_RTKIT_PWR_STATE_ON = 0x20, /* normal operating state */ }; @@ -881,6 +882,26 @@ int apple_rtkit_shutdown(struct apple_rtkit *rtk) } EXPORT_SYMBOL_GPL(apple_rtkit_shutdown); +int apple_rtkit_idle(struct apple_rtkit *rtk) +{ + int ret; + + /* if OFF is used here the co-processor will not wake up again */ + ret = apple_rtkit_set_ap_power_state(rtk, + APPLE_RTKIT_PWR_STATE_IDLE); + if (ret) + return ret; + + ret = apple_rtkit_set_iop_power_state(rtk, APPLE_RTKIT_PWR_STATE_IDLE); + if (ret) + return ret; + + rtk->iop_power_state = APPLE_RTKIT_PWR_STATE_IDLE; + rtk->ap_power_state = APPLE_RTKIT_PWR_STATE_IDLE; + return 0; +} +EXPORT_SYMBOL_GPL(apple_rtkit_idle); + int apple_rtkit_quiesce(struct apple_rtkit *rtk) { int ret; diff --git a/include/linux/soc/apple/rtkit.h b/include/linux/soc/apple/rtkit.h index c9cabb679cd1..a2446b45ed7f 100644 --- a/include/linux/soc/apple/rtkit.h +++ b/include/linux/soc/apple/rtkit.h @@ -104,6 +104,11 @@ int apple_rtkit_wake(struct apple_rtkit *rtk); */ int apple_rtkit_shutdown(struct apple_rtkit *rtk); +/* + * Put the co-processor into idle mode + */ +int apple_rtkit_idle(struct apple_rtkit *rtk); + /* * Checks if RTKit is running and ready to handle messages. */ -- cgit v1.2.3 From c289d5bce8521352a596f3ad27cd6d70b9f9f821 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Mon, 23 Jan 2023 15:51:25 +0900 Subject: soc: apple: apple-pmgr-pwrstate: Switch to IRQ-safe mode This requires changing the reset path locking primitives to the spinlock path in genpd, instead of the mutex path. Reviewed-by: Eric Curtin Reviewed-by: Sven Peter Signed-off-by: Hector Martin --- drivers/soc/apple/apple-pmgr-pwrstate.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/apple/apple-pmgr-pwrstate.c b/drivers/soc/apple/apple-pmgr-pwrstate.c index e1122288409a..a3e2bc1d2686 100644 --- a/drivers/soc/apple/apple-pmgr-pwrstate.c +++ b/drivers/soc/apple/apple-pmgr-pwrstate.c @@ -116,8 +116,9 @@ static int apple_pmgr_ps_power_off(struct generic_pm_domain *genpd) static int apple_pmgr_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) { struct apple_pmgr_ps *ps = rcdev_to_apple_pmgr_ps(rcdev); + unsigned long flags; - mutex_lock(&ps->genpd.mlock); + spin_lock_irqsave(&ps->genpd.slock, flags); if (ps->genpd.status == GENPD_STATE_OFF) dev_err(ps->dev, "PS 0x%x: asserting RESET while powered down\n", ps->offset); @@ -129,7 +130,7 @@ static int apple_pmgr_reset_assert(struct reset_controller_dev *rcdev, unsigned regmap_update_bits(ps->regmap, ps->offset, APPLE_PMGR_FLAGS | APPLE_PMGR_RESET, APPLE_PMGR_RESET); - mutex_unlock(&ps->genpd.mlock); + spin_unlock_irqrestore(&ps->genpd.slock, flags); return 0; } @@ -137,8 +138,9 @@ static int apple_pmgr_reset_assert(struct reset_controller_dev *rcdev, unsigned static int apple_pmgr_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) { struct apple_pmgr_ps *ps = rcdev_to_apple_pmgr_ps(rcdev); + unsigned long flags; - mutex_lock(&ps->genpd.mlock); + spin_lock_irqsave(&ps->genpd.slock, flags); dev_dbg(ps->dev, "PS 0x%x: deassert reset\n", ps->offset); regmap_update_bits(ps->regmap, ps->offset, APPLE_PMGR_FLAGS | APPLE_PMGR_RESET, 0); @@ -147,7 +149,7 @@ static int apple_pmgr_reset_deassert(struct reset_controller_dev *rcdev, unsigne if (ps->genpd.status == GENPD_STATE_OFF) dev_err(ps->dev, "PS 0x%x: RESET was deasserted while powered down\n", ps->offset); - mutex_unlock(&ps->genpd.mlock); + spin_unlock_irqrestore(&ps->genpd.slock, flags); return 0; } @@ -222,6 +224,7 @@ static int apple_pmgr_ps_probe(struct platform_device *pdev) return ret; } + ps->genpd.flags |= GENPD_FLAG_IRQ_SAFE; ps->genpd.name = name; ps->genpd.power_on = apple_pmgr_ps_power_on; ps->genpd.power_off = apple_pmgr_ps_power_off; -- cgit v1.2.3 From b3892860f50920ea46342d32bf51323877365082 Mon Sep 17 00:00:00 2001 From: Asahi Lina Date: Sat, 21 Jan 2023 16:41:35 +0900 Subject: soc: apple: rtkit: Export non-devm init/free functions While we normally encourage devm usage by drivers, some consumers (and in particular the upcoming Rust abstractions) might want to manually manage memory. Export the raw functions to make this possible. Signed-off-by: Asahi Lina Reviewed-by: Sven Peter Reviewed-by: Eric Curtin Signed-off-by: Hector Martin --- drivers/soc/apple/rtkit.c | 15 ++++++++++----- include/linux/soc/apple/rtkit.h | 19 +++++++++++++++++++ 2 files changed, 29 insertions(+), 5 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/apple/rtkit.c b/drivers/soc/apple/rtkit.c index efb1fa77dff2..35ec35aa500d 100644 --- a/drivers/soc/apple/rtkit.c +++ b/drivers/soc/apple/rtkit.c @@ -699,7 +699,7 @@ static int apple_rtkit_request_mbox_chan(struct apple_rtkit *rtk) return 0; } -static struct apple_rtkit *apple_rtkit_init(struct device *dev, void *cookie, +struct apple_rtkit *apple_rtkit_init(struct device *dev, void *cookie, const char *mbox_name, int mbox_idx, const struct apple_rtkit_ops *ops) { @@ -751,6 +751,7 @@ free_rtk: kfree(rtk); return ERR_PTR(ret); } +EXPORT_SYMBOL_GPL(apple_rtkit_init); static int apple_rtkit_wait_for_completion(struct completion *c) { @@ -947,10 +948,8 @@ int apple_rtkit_wake(struct apple_rtkit *rtk) } EXPORT_SYMBOL_GPL(apple_rtkit_wake); -static void apple_rtkit_free(void *data) +void apple_rtkit_free(struct apple_rtkit *rtk) { - struct apple_rtkit *rtk = data; - mbox_free_channel(rtk->mbox_chan); destroy_workqueue(rtk->wq); @@ -961,6 +960,12 @@ static void apple_rtkit_free(void *data) kfree(rtk->syslog_msg_buffer); kfree(rtk); } +EXPORT_SYMBOL_GPL(apple_rtkit_free); + +static void apple_rtkit_free_wrapper(void *data) +{ + apple_rtkit_free(data); +} struct apple_rtkit *devm_apple_rtkit_init(struct device *dev, void *cookie, const char *mbox_name, int mbox_idx, @@ -973,7 +978,7 @@ struct apple_rtkit *devm_apple_rtkit_init(struct device *dev, void *cookie, if (IS_ERR(rtk)) return rtk; - ret = devm_add_action_or_reset(dev, apple_rtkit_free, rtk); + ret = devm_add_action_or_reset(dev, apple_rtkit_free_wrapper, rtk); if (ret) return ERR_PTR(ret); diff --git a/include/linux/soc/apple/rtkit.h b/include/linux/soc/apple/rtkit.h index 927b214ef1c6..fc456f75c131 100644 --- a/include/linux/soc/apple/rtkit.h +++ b/include/linux/soc/apple/rtkit.h @@ -79,6 +79,25 @@ struct apple_rtkit *devm_apple_rtkit_init(struct device *dev, void *cookie, const char *mbox_name, int mbox_idx, const struct apple_rtkit_ops *ops); +/* + * Non-devm version of devm_apple_rtkit_init. Must be freed with + * apple_rtkit_free. + * + * @dev: Pointer to the device node this coprocessor is assocated with + * @cookie: opaque cookie passed to all functions defined in rtkit_ops + * @mbox_name: mailbox name used to communicate with the co-processor + * @mbox_idx: mailbox index to be used if mbox_name is NULL + * @ops: pointer to rtkit_ops to be used for this co-processor + */ +struct apple_rtkit *apple_rtkit_init(struct device *dev, void *cookie, + const char *mbox_name, int mbox_idx, + const struct apple_rtkit_ops *ops); + +/* + * Free an instance of apple_rtkit. + */ +void apple_rtkit_free(struct apple_rtkit *rtk); + /* * Reinitialize internal structures. Must only be called with the co-processor * is held in reset. -- cgit v1.2.3 From 22991d8d57251509b8ee5c0b3dac04506fe5ed7a Mon Sep 17 00:00:00 2001 From: Asahi Lina Date: Mon, 23 Jan 2023 12:17:28 +0900 Subject: soc: apple: rtkit: Add register dump decoding to crashlog When the coprocessor crashes, it's useful to get a proper register dump so we can find out what the firmware was doing. Add a decoder for this. Originally this had ESR decoding by reusing the ARM64 arch header for this, but that introduces some module linking and cross-arch compilation issues, so let's leave that out for now. Reviewed-by: Sven Peter Reviewed-by: Eric Curtin Signed-off-by: Asahi Lina Signed-off-by: Hector Martin --- drivers/soc/apple/rtkit-crashlog.c | 93 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/apple/rtkit-crashlog.c b/drivers/soc/apple/rtkit-crashlog.c index 732deed64660..dfa74b32eda2 100644 --- a/drivers/soc/apple/rtkit-crashlog.c +++ b/drivers/soc/apple/rtkit-crashlog.c @@ -13,6 +13,17 @@ #define APPLE_RTKIT_CRASHLOG_VERSION FOURCC('C', 'v', 'e', 'r') #define APPLE_RTKIT_CRASHLOG_MBOX FOURCC('C', 'm', 'b', 'x') #define APPLE_RTKIT_CRASHLOG_TIME FOURCC('C', 't', 'i', 'm') +#define APPLE_RTKIT_CRASHLOG_REGS FOURCC('C', 'r', 'g', '8') + +/* For COMPILE_TEST on non-ARM64 architectures */ +#ifndef PSR_MODE_EL0t +#define PSR_MODE_EL0t 0x00000000 +#define PSR_MODE_EL1t 0x00000004 +#define PSR_MODE_EL1h 0x00000005 +#define PSR_MODE_EL2t 0x00000008 +#define PSR_MODE_EL2h 0x00000009 +#define PSR_MODE_MASK 0x0000000f +#endif struct apple_rtkit_crashlog_header { u32 fourcc; @@ -31,6 +42,24 @@ struct apple_rtkit_crashlog_mbox_entry { }; static_assert(sizeof(struct apple_rtkit_crashlog_mbox_entry) == 0x18); +struct apple_rtkit_crashlog_regs { + u32 unk_0; + u32 unk_4; + u64 regs[31]; + u64 sp; + u64 pc; + u64 psr; + u64 cpacr; + u64 fpsr; + u64 fpcr; + u64 unk[64]; + u64 far; + u64 unk_X; + u64 esr; + u64 unk_Z; +}; +static_assert(sizeof(struct apple_rtkit_crashlog_regs) == 0x350); + static void apple_rtkit_crashlog_dump_str(struct apple_rtkit *rtk, u8 *bfr, size_t size) { @@ -94,6 +123,66 @@ static void apple_rtkit_crashlog_dump_mailbox(struct apple_rtkit *rtk, u8 *bfr, } } +static void apple_rtkit_crashlog_dump_regs(struct apple_rtkit *rtk, u8 *bfr, + size_t size) +{ + struct apple_rtkit_crashlog_regs regs; + const char *el; + int i; + + if (size < sizeof(regs)) { + dev_warn(rtk->dev, "RTKit: Regs section too small: 0x%zx", size); + return; + } + + memcpy(®s, bfr, sizeof(regs)); + + switch (regs.psr & PSR_MODE_MASK) { + case PSR_MODE_EL0t: + el = "EL0t"; + break; + case PSR_MODE_EL1t: + el = "EL1t"; + break; + case PSR_MODE_EL1h: + el = "EL1h"; + break; + case PSR_MODE_EL2t: + el = "EL2t"; + break; + case PSR_MODE_EL2h: + el = "EL2h"; + break; + default: + el = "unknown"; + break; + } + + dev_warn(rtk->dev, "RTKit: Exception dump:"); + dev_warn(rtk->dev, " == Exception taken from %s ==", el); + dev_warn(rtk->dev, " PSR = 0x%llx", regs.psr); + dev_warn(rtk->dev, " PC = 0x%llx\n", regs.pc); + dev_warn(rtk->dev, " ESR = 0x%llx\n", regs.esr); + dev_warn(rtk->dev, " FAR = 0x%llx\n", regs.far); + dev_warn(rtk->dev, " SP = 0x%llx\n", regs.sp); + dev_warn(rtk->dev, "\n"); + + for (i = 0; i < 31; i += 4) { + if (i < 28) + dev_warn(rtk->dev, + " x%02d-x%02d = %016llx %016llx %016llx %016llx\n", + i, i + 3, + regs.regs[i], regs.regs[i + 1], + regs.regs[i + 2], regs.regs[i + 3]); + else + dev_warn(rtk->dev, + " x%02d-x%02d = %016llx %016llx %016llx\n", i, i + 3, + regs.regs[i], regs.regs[i + 1], regs.regs[i + 2]); + } + + dev_warn(rtk->dev, "\n"); +} + void apple_rtkit_crashlog_dump(struct apple_rtkit *rtk, u8 *bfr, size_t size) { size_t offset; @@ -140,6 +229,10 @@ void apple_rtkit_crashlog_dump(struct apple_rtkit *rtk, u8 *bfr, size_t size) apple_rtkit_crashlog_dump_time(rtk, bfr + offset + 16, section_size); break; + case APPLE_RTKIT_CRASHLOG_REGS: + apple_rtkit_crashlog_dump_regs(rtk, bfr + offset + 16, + section_size); + break; default: dev_warn(rtk->dev, "RTKit: Unknown crashlog section: %x", -- cgit v1.2.3 From a0674cd237fc24b08c7dcb4f8e48df3ee769293a Mon Sep 17 00:00:00 2001 From: Roger Lu Date: Wed, 11 Jan 2023 15:45:15 +0800 Subject: soc: mediatek: mtk-svs: restore default voltages when svs_init02() fail If svs init02 fail, it means we cannot rely on svs bank voltages anymore. We need to disable svs function and restore DVFS opp voltages back to the default voltages for making sure we have enough DVFS voltages. Fixes: 681a02e95000 ("soc: mediatek: SVS: introduce MTK SVS engine") Fixes: 0bbb09b2af9d ("soc: mediatek: SVS: add mt8192 SVS GPU driver") Signed-off-by: Roger Lu Link: https://lore.kernel.org/r/20230111074528.29354-2-roger.lu@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-svs.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 75b2f534aa9d..9859e6cf6b8f 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1461,6 +1461,7 @@ static int svs_init02(struct svs_platform *svsp) { struct svs_bank *svsb; unsigned long flags, time_left; + int ret; u32 idx; for (idx = 0; idx < svsp->bank_max; idx++) { @@ -1479,7 +1480,8 @@ static int svs_init02(struct svs_platform *svsp) msecs_to_jiffies(5000)); if (!time_left) { dev_err(svsb->dev, "init02 completion timeout\n"); - return -EBUSY; + ret = -EBUSY; + goto out_of_init02; } } @@ -1497,12 +1499,30 @@ static int svs_init02(struct svs_platform *svsp) if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) { if (svs_sync_bank_volts_from_opp(svsb)) { dev_err(svsb->dev, "sync volt fail\n"); - return -EPERM; + ret = -EPERM; + goto out_of_init02; } } } return 0; + +out_of_init02: + for (idx = 0; idx < svsp->bank_max; idx++) { + svsb = &svsp->banks[idx]; + + spin_lock_irqsave(&svs_lock, flags); + svsp->pbank = svsb; + svs_switch_bank(svsp); + svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); + svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); + spin_unlock_irqrestore(&svs_lock, flags); + + svsb->phase = SVSB_PHASE_ERROR; + svs_adjust_pm_opp_volts(svsb); + } + + return ret; } static void svs_mon_mode(struct svs_platform *svsp) -- cgit v1.2.3 From f4f8ad204a15d57c1a3e8ea7eca62157b44cbf59 Mon Sep 17 00:00:00 2001 From: Roger Lu Date: Wed, 11 Jan 2023 15:45:16 +0800 Subject: soc: mediatek: mtk-svs: reset svs when svs_resume() fail Add svs reset when svs_resume() fail. Fixes: a825d72f74a3 ("soc: mediatek: fix missing clk_disable_unprepare() on err in svs_resume()") Signed-off-by: Roger Lu Link: https://lore.kernel.org/r/20230111074528.29354-3-roger.lu@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-svs.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 9859e6cf6b8f..e0b8aa75c84b 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1614,12 +1614,16 @@ static int svs_resume(struct device *dev) ret = svs_init02(svsp); if (ret) - goto out_of_resume; + goto svs_resume_reset_assert; svs_mon_mode(svsp); return 0; +svs_resume_reset_assert: + dev_err(svsp->dev, "assert reset: %d\n", + reset_control_assert(svsp->rst)); + out_of_resume: clk_disable_unprepare(svsp->main_clk); return ret; -- cgit v1.2.3 From 37fa2aff8fe490771f2229b0f2fcd15796b1bfca Mon Sep 17 00:00:00 2001 From: Shang XiaoJing Date: Wed, 11 Jan 2023 15:45:18 +0800 Subject: soc: mediatek: mtk-svs: Use pm_runtime_resume_and_get() in svs_init01() svs_init01() calls pm_runtime_get_sync() and added fail path as svs_init01_finish to put usage_counter. However, pm_runtime_get_sync() will increment usage_counter even it failed. Fix it by replacing it with pm_runtime_resume_and_get() to keep usage counter balanced. Fixes: 681a02e95000 ("soc: mediatek: SVS: introduce MTK SVS engine") Signed-off-by: Shang XiaoJing Signed-off-by: Roger Lu Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230111074528.29354-5-roger.lu@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-svs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index e0b8aa75c84b..00526fd37d7b 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1324,7 +1324,7 @@ static int svs_init01(struct svs_platform *svsp) svsb->pm_runtime_enabled_count++; } - ret = pm_runtime_get_sync(svsb->opp_dev); + ret = pm_runtime_resume_and_get(svsb->opp_dev); if (ret < 0) { dev_err(svsb->dev, "mtcmos on fail: %d\n", ret); goto svs_init01_resume_cpuidle; -- cgit v1.2.3 From 8bf305087629a98224aa97769587434ea4016767 Mon Sep 17 00:00:00 2001 From: Roger Lu Date: Wed, 11 Jan 2023 15:45:21 +0800 Subject: soc: mediatek: mtk-svs: keep svs alive if CONFIG_DEBUG_FS not supported Some projects might not support CONFIG_DEBUG_FS but still needs svs to be alive. Therefore, enclose debug cmd codes with CONFIG_DEBUG_FS to make sure svs can be alive when CONFIG_DEBUG_FS not supported. Signed-off-by: Roger Lu Link: https://lore.kernel.org/r/20230111074528.29354-8-roger.lu@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-svs.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 00526fd37d7b..e55fb16fdc5a 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -138,6 +138,7 @@ static DEFINE_SPINLOCK(svs_lock); +#ifdef CONFIG_DEBUG_FS #define debug_fops_ro(name) \ static int svs_##name##_debug_open(struct inode *inode, \ struct file *filp) \ @@ -170,6 +171,7 @@ static DEFINE_SPINLOCK(svs_lock); } #define svs_dentry_data(name) {__stringify(name), &svs_##name##_debug_fops} +#endif /** * enum svsb_phase - svs bank phase enumeration @@ -628,6 +630,7 @@ unlock_mutex: return ret; } +#ifdef CONFIG_DEBUG_FS static int svs_dump_debug_show(struct seq_file *m, void *p) { struct svs_platform *svsp = (struct svs_platform *)m->private; @@ -843,6 +846,7 @@ static int svs_create_debug_cmds(struct svs_platform *svsp) return 0; } +#endif /* CONFIG_DEBUG_FS */ static u32 interpolate(u32 f0, u32 f1, u32 v0, u32 v1, u32 fx) { @@ -2444,11 +2448,13 @@ static int svs_probe(struct platform_device *pdev) goto svs_probe_iounmap; } +#ifdef CONFIG_DEBUG_FS ret = svs_create_debug_cmds(svsp); if (ret) { dev_err(svsp->dev, "svs create debug cmds fail: %d\n", ret); goto svs_probe_iounmap; } +#endif return 0; -- cgit v1.2.3 From 3bab727bef488c3a8da281ae4f89fd5070e37559 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Wed, 11 Jan 2023 15:45:22 +0800 Subject: soc: mediatek: mtk-svs: clean up platform probing We only ever call the SoC specific probe function from svs_platform_probe. No need to carry that function in a global datastructure around. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Roger Lu Link: https://lore.kernel.org/r/20230111074528.29354-9-roger.lu@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-svs.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index e55fb16fdc5a..95147d34f4ef 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -321,7 +321,6 @@ static const u32 svs_regs_v2[] = { * @banks: svs banks that svs platform supports * @rst: svs platform reset control * @efuse_parsing: svs platform efuse parsing function pointer - * @probe: svs platform probe function pointer * @efuse_max: total number of svs efuse * @tefuse_max: total number of thermal efuse * @regs: svs platform registers map @@ -338,7 +337,6 @@ struct svs_platform { struct svs_bank *banks; struct reset_control *rst; bool (*efuse_parsing)(struct svs_platform *svsp); - int (*probe)(struct svs_platform *svsp); size_t efuse_max; size_t tefuse_max; const u32 *regs; @@ -2375,11 +2373,10 @@ static struct svs_platform *svs_platform_probe(struct platform_device *pdev) svsp->name = svsp_data->name; svsp->banks = svsp_data->banks; svsp->efuse_parsing = svsp_data->efuse_parsing; - svsp->probe = svsp_data->probe; svsp->regs = svsp_data->regs; svsp->bank_max = svsp_data->bank_max; - ret = svsp->probe(svsp); + ret = svsp_data->probe(svsp); if (ret) return ERR_PTR(ret); -- cgit v1.2.3 From 227fafd73b1c1f67114da6322fc32cb545b3a20b Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Wed, 11 Jan 2023 15:45:23 +0800 Subject: soc: mediatek: mtk-svs: improve readability of platform_probe If a compatible misses a match data entry, then something is wrong in the development phase, we don't need to check for that at runtime. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Roger Lu Link: https://lore.kernel.org/r/20230111074528.29354-10-roger.lu@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-svs.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 95147d34f4ef..937a4163bff1 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -2360,10 +2360,6 @@ static struct svs_platform *svs_platform_probe(struct platform_device *pdev) int ret; svsp_data = of_device_get_match_data(&pdev->dev); - if (!svsp_data) { - dev_err(&pdev->dev, "no svs platform data?\n"); - return ERR_PTR(-EPERM); - } svsp = devm_kzalloc(&pdev->dev, sizeof(*svsp), GFP_KERNEL); if (!svsp) -- cgit v1.2.3 From 5343e9ffb4337c22b9aef41161bc92ee5b449a17 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Wed, 11 Jan 2023 15:45:24 +0800 Subject: soc: mediatek: mtk-svs: move svs_platform_probe into probe Moving svs_platform_probe into driver probe function will allow us to reduce svs_platform members. This will be done in a follow-up patch. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Roger Lu Link: https://lore.kernel.org/r/20230111074528.29354-11-roger.lu@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-svs.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 937a4163bff1..5c5a30fbebd1 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -2353,17 +2353,17 @@ static const struct of_device_id svs_of_match[] = { }, }; -static struct svs_platform *svs_platform_probe(struct platform_device *pdev) +static int svs_probe(struct platform_device *pdev) { struct svs_platform *svsp; const struct svs_platform_data *svsp_data; - int ret; + int ret, svsp_irq; svsp_data = of_device_get_match_data(&pdev->dev); svsp = devm_kzalloc(&pdev->dev, sizeof(*svsp), GFP_KERNEL); if (!svsp) - return ERR_PTR(-ENOMEM); + return -ENOMEM; svsp->dev = &pdev->dev; svsp->name = svsp_data->name; @@ -2374,19 +2374,7 @@ static struct svs_platform *svs_platform_probe(struct platform_device *pdev) ret = svsp_data->probe(svsp); if (ret) - return ERR_PTR(ret); - - return svsp; -} - -static int svs_probe(struct platform_device *pdev) -{ - struct svs_platform *svsp; - int svsp_irq, ret; - - svsp = svs_platform_probe(pdev); - if (IS_ERR(svsp)) - return PTR_ERR(svsp); + return ret; if (!svs_is_efuse_data_correct(svsp)) { dev_notice(svsp->dev, "efuse data isn't correct\n"); -- cgit v1.2.3 From 01c9a8bd23ca43c708043c712fb4579848ae8dae Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Wed, 11 Jan 2023 15:45:25 +0800 Subject: soc: mediatek: mtk-svs: delete superfluous platform data entries The platform name and efuse parsing function pointer are only used while probing the device. Use them from the svs_platform_data struct instead. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Roger Lu Link: https://lore.kernel.org/r/20230111074528.29354-12-roger.lu@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-svs.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 5c5a30fbebd1..d5a27ad60edd 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -313,14 +313,12 @@ static const u32 svs_regs_v2[] = { /** * struct svs_platform - svs platform control - * @name: svs platform name * @base: svs platform register base * @dev: svs platform device * @main_clk: main clock for svs bank * @pbank: svs bank pointer needing to be protected by spin_lock section * @banks: svs banks that svs platform supports * @rst: svs platform reset control - * @efuse_parsing: svs platform efuse parsing function pointer * @efuse_max: total number of svs efuse * @tefuse_max: total number of thermal efuse * @regs: svs platform registers map @@ -329,14 +327,12 @@ static const u32 svs_regs_v2[] = { * @tefuse: thermal efuse data received from NVMEM framework */ struct svs_platform { - char *name; void __iomem *base; struct device *dev; struct clk *main_clk; struct svs_bank *pbank; struct svs_bank *banks; struct reset_control *rst; - bool (*efuse_parsing)(struct svs_platform *svsp); size_t efuse_max; size_t tefuse_max; const u32 *regs; @@ -2037,7 +2033,7 @@ static bool svs_is_efuse_data_correct(struct svs_platform *svsp) svsp->efuse_max /= sizeof(u32); nvmem_cell_put(cell); - return svsp->efuse_parsing(svsp); + return true; } static struct device *svs_get_subsys_device(struct svs_platform *svsp, @@ -2366,9 +2362,7 @@ static int svs_probe(struct platform_device *pdev) return -ENOMEM; svsp->dev = &pdev->dev; - svsp->name = svsp_data->name; svsp->banks = svsp_data->banks; - svsp->efuse_parsing = svsp_data->efuse_parsing; svsp->regs = svsp_data->regs; svsp->bank_max = svsp_data->bank_max; @@ -2379,6 +2373,12 @@ static int svs_probe(struct platform_device *pdev) if (!svs_is_efuse_data_correct(svsp)) { dev_notice(svsp->dev, "efuse data isn't correct\n"); ret = -EPERM; + goto svs_probe_free_efuse; + } + + if (!svsp_data->efuse_parsing(svsp)) { + dev_err(svsp->dev, "efuse data parsing failed\n"); + ret = -EPERM; goto svs_probe_free_resource; } @@ -2416,7 +2416,7 @@ static int svs_probe(struct platform_device *pdev) } ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr, - IRQF_ONESHOT, svsp->name, svsp); + IRQF_ONESHOT, svsp_data->name, svsp); if (ret) { dev_err(svsp->dev, "register irq(%d) failed: %d\n", svsp_irq, ret); @@ -2446,11 +2446,13 @@ svs_probe_clk_disable: clk_disable_unprepare(svsp->main_clk); svs_probe_free_resource: - if (!IS_ERR_OR_NULL(svsp->efuse)) - kfree(svsp->efuse); if (!IS_ERR_OR_NULL(svsp->tefuse)) kfree(svsp->tefuse); +svs_probe_free_efuse: + if (!IS_ERR_OR_NULL(svsp->efuse)) + kfree(svsp->efuse); + return ret; } -- cgit v1.2.3 From d5a7d809907c5df9e79625cd5f7d5a43b70dd913 Mon Sep 17 00:00:00 2001 From: Roger Lu Date: Wed, 11 Jan 2023 15:45:28 +0800 Subject: soc: mtk-svs: mt8183: refactor o_slope calculation The o_slope value is dependent of the o_slope_sign, refactor code to get rid of unnecessary if constructs. Signed-off-by: Roger Lu Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230111074528.29354-15-roger.lu@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-svs.c | 51 ++++++++++++++++++------------------------ 1 file changed, 22 insertions(+), 29 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index d5a27ad60edd..333d40f94c3c 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1921,26 +1921,27 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) o_slope_sign = (svsp->tefuse[0] >> 7) & BIT(0); ts_id = (svsp->tefuse[1] >> 9) & BIT(0); - o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0); - - if (adc_cali_en_t == 1) { - if (!ts_id) - o_slope = 0; - - if (adc_ge_t < 265 || adc_ge_t > 758 || - adc_oe_t < 265 || adc_oe_t > 758 || - o_vtsmcu[0] < -8 || o_vtsmcu[0] > 484 || - o_vtsmcu[1] < -8 || o_vtsmcu[1] > 484 || - o_vtsmcu[2] < -8 || o_vtsmcu[2] > 484 || - o_vtsmcu[3] < -8 || o_vtsmcu[3] > 484 || - o_vtsmcu[4] < -8 || o_vtsmcu[4] > 484 || - o_vtsabb < -8 || o_vtsabb > 484 || - degc_cali < 1 || degc_cali > 63) { - dev_err(svsp->dev, "bad thermal efuse, no mon mode\n"); - goto remove_mt8183_svsb_mon_mode; - } + if (!ts_id) { + o_slope = 1534; } else { - dev_err(svsp->dev, "no thermal efuse, no mon mode\n"); + o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0); + if (!o_slope_sign) + o_slope = 1534 + o_slope * 10; + else + o_slope = 1534 - o_slope * 10; + } + + if (adc_cali_en_t == 0 || + adc_ge_t < 265 || adc_ge_t > 758 || + adc_oe_t < 265 || adc_oe_t > 758 || + o_vtsmcu[0] < -8 || o_vtsmcu[0] > 484 || + o_vtsmcu[1] < -8 || o_vtsmcu[1] > 484 || + o_vtsmcu[2] < -8 || o_vtsmcu[2] > 484 || + o_vtsmcu[3] < -8 || o_vtsmcu[3] > 484 || + o_vtsmcu[4] < -8 || o_vtsmcu[4] > 484 || + o_vtsabb < -8 || o_vtsabb > 484 || + degc_cali < 1 || degc_cali > 63) { + dev_err(svsp->dev, "bad thermal efuse, no mon mode\n"); goto remove_mt8183_svsb_mon_mode; } @@ -1959,11 +1960,7 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) x_roomt[i] = (((format[i] * 10000) / 4096) * 10000) / gain; temp0 = (10000 * 100000 / gain) * 15 / 18; - - if (!o_slope_sign) - mts = (temp0 * 10) / (1534 + o_slope * 10); - else - mts = (temp0 * 10) / (1534 - o_slope * 10); + mts = (temp0 * 10) / o_slope; for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; @@ -1990,11 +1987,7 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) temp0 = (degc_cali * 10 / 2); temp1 = ((10000 * 100000 / 4096 / gain) * oe + tb_roomt * 10) * 15 / 18; - - if (!o_slope_sign) - temp2 = temp1 * 100 / (1534 + o_slope * 10); - else - temp2 = temp1 * 100 / (1534 - o_slope * 10); + temp2 = temp1 * 100 / o_slope; svsb->bts = (temp0 + temp2 - 250) * 4 / 10; } -- cgit v1.2.3 From 916120df5aa926d65f4666c075ed8d4955ef7bab Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 6 Oct 2022 13:09:35 +0200 Subject: soc: mediatek: mtk-devapc: Switch to devm_clk_get_enabled() This driver does exactly devm_clk_get() and clk_prepare_enable() right after, which is exactly what devm_clk_get_enabled() does: clean that up by switching to the latter. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221006110935.59695-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-devapc.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c index fc13334db1b1..bad139cb117e 100644 --- a/drivers/soc/mediatek/mtk-devapc.c +++ b/drivers/soc/mediatek/mtk-devapc.c @@ -276,19 +276,14 @@ static int mtk_devapc_probe(struct platform_device *pdev) if (!devapc_irq) return -EINVAL; - ctx->infra_clk = devm_clk_get(&pdev->dev, "devapc-infra-clock"); + ctx->infra_clk = devm_clk_get_enabled(&pdev->dev, "devapc-infra-clock"); if (IS_ERR(ctx->infra_clk)) return -EINVAL; - if (clk_prepare_enable(ctx->infra_clk)) - return -EINVAL; - ret = devm_request_irq(&pdev->dev, devapc_irq, devapc_violation_irq, IRQF_TRIGGER_NONE, "devapc", ctx); - if (ret) { - clk_disable_unprepare(ctx->infra_clk); + if (ret) return ret; - } platform_set_drvdata(pdev, ctx); @@ -303,8 +298,6 @@ static int mtk_devapc_remove(struct platform_device *pdev) stop_devapc(ctx); - clk_disable_unprepare(ctx->infra_clk); - return 0; } -- cgit v1.2.3 From 6f42f5e73bb431c7e01c15dadfdc15872aa85db5 Mon Sep 17 00:00:00 2001 From: Zeng Heng Date: Wed, 28 Sep 2022 23:13:46 +0800 Subject: soc: mediatek: mtk-svs: add missing MODULE_DEVICE_TABLE This patch adds missing MODULE_DEVICE_TABLE definition which generates correct modalias for automatic loading of this driver when it is built as an external module. Signed-off-by: Zeng Heng Link: https://lore.kernel.org/r/20220928151346.1942977-1-zengheng4@huawei.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-svs.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 333d40f94c3c..f26eb2f637d5 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -2341,6 +2341,7 @@ static const struct of_device_id svs_of_match[] = { /* Sentinel */ }, }; +MODULE_DEVICE_TABLE(of, svs_of_match); static int svs_probe(struct platform_device *pdev) { -- cgit v1.2.3 From 7dbb4a38bff3449317abec5e0187ad97f699d5a6 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Wed, 1 Feb 2023 15:47:17 +1030 Subject: soc: nuvoton: Add SoC info driver for WPCM450 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a SoC information driver for Nuvoton WPCM450 SoCs. It provides information such as the SoC revision. Usage example: # grep . /sys/devices/soc0/* /sys/devices/soc0/family:Nuvoton NPCM /sys/devices/soc0/revision:A3 /sys/devices/soc0/soc_id:WPCM450 Signed-off-by: Jonathan Neuschäfer Reviewed-by: Joel Stanley Reviewed-by: Paul Menzel Link: https://lore.kernel.org/r/20221031223926.241641-1-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley Link: https://lore.kernel.org/r/20230201051717.1005938-1-joel@jms.id.au Signed-off-by: Arnd Bergmann --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/nuvoton/Kconfig | 11 ++++ drivers/soc/nuvoton/Makefile | 2 + drivers/soc/nuvoton/wpcm450-soc.c | 109 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 124 insertions(+) create mode 100644 drivers/soc/nuvoton/Kconfig create mode 100644 drivers/soc/nuvoton/Makefile create mode 100644 drivers/soc/nuvoton/wpcm450-soc.c (limited to 'drivers/soc') diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 81ae4f77974b..4e176280113a 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -16,6 +16,7 @@ source "drivers/soc/litex/Kconfig" source "drivers/soc/loongson/Kconfig" source "drivers/soc/mediatek/Kconfig" source "drivers/soc/microchip/Kconfig" +source "drivers/soc/nuvoton/Kconfig" source "drivers/soc/pxa/Kconfig" source "drivers/soc/qcom/Kconfig" source "drivers/soc/renesas/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 0447ec7b5552..3b0f9fb3b5c8 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_LITEX_SOC_CONTROLLER) += litex/ obj-y += loongson/ obj-y += mediatek/ obj-y += microchip/ +obj-y += nuvoton/ obj-y += pxa/ obj-y += amlogic/ obj-y += qcom/ diff --git a/drivers/soc/nuvoton/Kconfig b/drivers/soc/nuvoton/Kconfig new file mode 100644 index 000000000000..df46182088ec --- /dev/null +++ b/drivers/soc/nuvoton/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0 +menuconfig WPCM450_SOC + tristate "Nuvoton WPCM450 SoC driver" + default y if ARCH_WPCM450 + select SOC_BUS + help + Say Y here to compile the SoC information driver for Nuvoton + WPCM450 SoCs. + + This driver provides information such as the SoC model and + revision. diff --git a/drivers/soc/nuvoton/Makefile b/drivers/soc/nuvoton/Makefile new file mode 100644 index 000000000000..e30317b4e829 --- /dev/null +++ b/drivers/soc/nuvoton/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_WPCM450_SOC) += wpcm450-soc.o diff --git a/drivers/soc/nuvoton/wpcm450-soc.c b/drivers/soc/nuvoton/wpcm450-soc.c new file mode 100644 index 000000000000..c5e0d11c383b --- /dev/null +++ b/drivers/soc/nuvoton/wpcm450-soc.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Nuvoton WPCM450 SoC Identification + * + * Copyright (C) 2022 Jonathan Neuschäfer + */ + +#include +#include +#include +#include +#include + +#define GCR_PDID 0 +#define PDID_CHIP(x) ((x) & 0x00ffffff) +#define CHIP_WPCM450 0x926450 +#define PDID_REV(x) ((x) >> 24) + +struct revision { + u8 number; + const char *name; +}; + +static const struct revision revisions[] __initconst = { + { 0x00, "Z1" }, + { 0x03, "Z2" }, + { 0x04, "Z21" }, + { 0x08, "A1" }, + { 0x09, "A2" }, + { 0x0a, "A3" }, + {} +}; + +static const char * __init get_revision(unsigned int rev) +{ + int i; + + for (i = 0; revisions[i].name; i++) + if (revisions[i].number == rev) + return revisions[i].name; + return NULL; +} + +static struct soc_device_attribute *wpcm450_attr; +static struct soc_device *wpcm450_soc; + +static int __init wpcm450_soc_init(void) +{ + struct soc_device_attribute *attr; + struct soc_device *soc; + const char *revision; + struct regmap *gcr; + u32 pdid; + int ret; + + if (!of_machine_is_compatible("nuvoton,wpcm450")) + return 0; + + gcr = syscon_regmap_lookup_by_compatible("nuvoton,wpcm450-gcr"); + if (IS_ERR(gcr)) + return PTR_ERR(gcr); + ret = regmap_read(gcr, GCR_PDID, &pdid); + if (ret) + return ret; + + if (PDID_CHIP(pdid) != CHIP_WPCM450) { + pr_warn("Unknown chip ID in GCR.PDID: 0x%06x\n", PDID_CHIP(pdid)); + return -ENODEV; + } + + revision = get_revision(PDID_REV(pdid)); + if (!revision) { + pr_warn("Unknown chip revision in GCR.PDID: 0x%02x\n", PDID_REV(pdid)); + return -ENODEV; + } + + attr = kzalloc(sizeof(*attr), GFP_KERNEL); + if (!attr) + return -ENOMEM; + + attr->family = "Nuvoton NPCM"; + attr->soc_id = "WPCM450"; + attr->revision = revision; + soc = soc_device_register(attr); + if (IS_ERR(soc)) { + kfree(attr); + pr_warn("Could not register SoC device\n"); + return PTR_ERR(soc); + } + + wpcm450_soc = soc; + wpcm450_attr = attr; + return 0; +} +module_init(wpcm450_soc_init); + +static void __exit wpcm450_soc_exit(void) +{ + if (wpcm450_soc) { + soc_device_unregister(wpcm450_soc); + wpcm450_soc = NULL; + kfree(wpcm450_attr); + } +} +module_exit(wpcm450_soc_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Jonathan Neuschäfer"); +MODULE_DESCRIPTION("Nuvoton WPCM450 SoC Identification driver"); -- cgit v1.2.3 From 58ef4ece1e41ac525db3e79529909683325d85df Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 31 Jan 2023 20:18:51 -0800 Subject: soc: qcom: pmic_glink: Introduce base PMIC GLINK driver The PMIC GLINK service runs on one of the co-processors of some modern Qualcomm platforms and implements USB-C and battery managements. It uses a message based protocol over GLINK for communication with the OS, hence the name. The driver implemented provides the rpmsg device for communication and uses auxiliary bus to spawn off individual devices in respective subsystem. The auxiliary devices are spawned off from a platform_device, so that the drm_bridge is available early, to allow the DisplayPort driver to probe even before the remoteproc has spun up. Signed-off-by: Bjorn Andersson Tested-by: Konrad Dybcio # SM8350 PDX215 Reviewed-by: Neil Armstrong Tested-by: Neil Armstrong # on SM8550-MTP & SM8450-HDK Signed-off-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230201041853.1934355-3-quic_bjorande@quicinc.com --- drivers/soc/qcom/Kconfig | 15 ++ drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/pmic_glink.c | 336 ++++++++++++++++++++++++++++++++++++ include/linux/soc/qcom/pmic_glink.h | 32 ++++ 4 files changed, 384 insertions(+) create mode 100644 drivers/soc/qcom/pmic_glink.c create mode 100644 include/linux/soc/qcom/pmic_glink.h (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index ae504c43d9e7..df6ff7bf90cb 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -92,6 +92,21 @@ config QCOM_PDR_HELPERS tristate select QCOM_QMI_HELPERS +config QCOM_PMIC_GLINK + tristate "Qualcomm PMIC GLINK driver" + depends on RPMSG + depends on TYPEC + depends on DRM + select AUXILIARY_BUS + select QCOM_PDR_HELPERS + help + The Qualcomm PMIC GLINK driver provides access, over GLINK, to the + USB and battery firmware running on one of the coprocessors in + several modern Qualcomm platforms. + + Say yes here to support USB-C and battery status on modern Qualcomm + platforms. + config QCOM_QMI_HELPERS tristate depends on NET diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index d66604aff2b0..fbbd1231e554 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o obj-$(CONFIG_QCOM_OCMEM) += ocmem.o obj-$(CONFIG_QCOM_PDR_HELPERS) += pdr_interface.o +obj-$(CONFIG_QCOM_PMIC_GLINK) += pmic_glink.o obj-$(CONFIG_QCOM_QMI_HELPERS) += qmi_helpers.o qmi_helpers-y += qmi_encdec.o qmi_interface.o obj-$(CONFIG_QCOM_RMTFS_MEM) += rmtfs_mem.o diff --git a/drivers/soc/qcom/pmic_glink.c b/drivers/soc/qcom/pmic_glink.c new file mode 100644 index 000000000000..bb3fb57abcc6 --- /dev/null +++ b/drivers/soc/qcom/pmic_glink.c @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Ltd + */ +#include +#include +#include +#include +#include +#include +#include + +struct pmic_glink { + struct device *dev; + struct pdr_handle *pdr; + + struct rpmsg_endpoint *ept; + + struct auxiliary_device altmode_aux; + struct auxiliary_device ps_aux; + struct auxiliary_device ucsi_aux; + + /* serializing client_state and pdr_state updates */ + struct mutex state_lock; + unsigned int client_state; + unsigned int pdr_state; + + /* serializing clients list updates */ + struct mutex client_lock; + struct list_head clients; +}; + +static struct pmic_glink *__pmic_glink; +static DEFINE_MUTEX(__pmic_glink_lock); + +struct pmic_glink_client { + struct list_head node; + + struct pmic_glink *pg; + unsigned int id; + + void (*cb)(const void *data, size_t len, void *priv); + void (*pdr_notify)(void *priv, int state); + void *priv; +}; + +static void _devm_pmic_glink_release_client(struct device *dev, void *res) +{ + struct pmic_glink_client *client = (struct pmic_glink_client *)res; + struct pmic_glink *pg = client->pg; + + mutex_lock(&pg->client_lock); + list_del(&client->node); + mutex_unlock(&pg->client_lock); +} + +struct pmic_glink_client *devm_pmic_glink_register_client(struct device *dev, + unsigned int id, + void (*cb)(const void *, size_t, void *), + void (*pdr)(void *, int), + void *priv) +{ + struct pmic_glink_client *client; + struct pmic_glink *pg = dev_get_drvdata(dev->parent); + + client = devres_alloc(_devm_pmic_glink_release_client, sizeof(*client), GFP_KERNEL); + if (!client) + return ERR_PTR(-ENOMEM); + + client->pg = pg; + client->id = id; + client->cb = cb; + client->pdr_notify = pdr; + client->priv = priv; + + mutex_lock(&pg->client_lock); + list_add(&client->node, &pg->clients); + mutex_unlock(&pg->client_lock); + + devres_add(dev, client); + + return client; +} +EXPORT_SYMBOL_GPL(devm_pmic_glink_register_client); + +int pmic_glink_send(struct pmic_glink_client *client, void *data, size_t len) +{ + struct pmic_glink *pg = client->pg; + + return rpmsg_send(pg->ept, data, len); +} +EXPORT_SYMBOL_GPL(pmic_glink_send); + +static int pmic_glink_rpmsg_callback(struct rpmsg_device *rpdev, void *data, + int len, void *priv, u32 addr) +{ + struct pmic_glink_client *client; + struct pmic_glink_hdr *hdr; + struct pmic_glink *pg = dev_get_drvdata(&rpdev->dev); + + if (len < sizeof(*hdr)) { + dev_warn(pg->dev, "ignoring truncated message\n"); + return 0; + } + + hdr = data; + + list_for_each_entry(client, &pg->clients, node) { + if (client->id == le32_to_cpu(hdr->owner)) + client->cb(data, len, client->priv); + } + + return 0; +} + +static void pmic_glink_aux_release(struct device *dev) {} + +static int pmic_glink_add_aux_device(struct pmic_glink *pg, + struct auxiliary_device *aux, + const char *name) +{ + struct device *parent = pg->dev; + int ret; + + aux->name = name; + aux->dev.parent = parent; + aux->dev.release = pmic_glink_aux_release; + device_set_of_node_from_dev(&aux->dev, parent); + ret = auxiliary_device_init(aux); + if (ret) + return ret; + + ret = auxiliary_device_add(aux); + if (ret) + auxiliary_device_uninit(aux); + + return ret; +} + +static void pmic_glink_del_aux_device(struct pmic_glink *pg, + struct auxiliary_device *aux) +{ + auxiliary_device_delete(aux); + auxiliary_device_uninit(aux); +} + +static void pmic_glink_state_notify_clients(struct pmic_glink *pg) +{ + struct pmic_glink_client *client; + unsigned int new_state = pg->client_state; + + if (pg->client_state != SERVREG_SERVICE_STATE_UP) { + if (pg->pdr_state == SERVREG_SERVICE_STATE_UP && pg->ept) + new_state = SERVREG_SERVICE_STATE_UP; + } else { + if (pg->pdr_state == SERVREG_SERVICE_STATE_UP && pg->ept) + new_state = SERVREG_SERVICE_STATE_DOWN; + } + + if (new_state != pg->client_state) { + list_for_each_entry(client, &pg->clients, node) + client->pdr_notify(client->priv, new_state); + pg->client_state = new_state; + } +} + +static void pmic_glink_pdr_callback(int state, char *svc_path, void *priv) +{ + struct pmic_glink *pg = priv; + + mutex_lock(&pg->state_lock); + pg->pdr_state = state; + + pmic_glink_state_notify_clients(pg); + mutex_unlock(&pg->state_lock); +} + +static int pmic_glink_rpmsg_probe(struct rpmsg_device *rpdev) +{ + struct pmic_glink *pg = __pmic_glink; + int ret = 0; + + mutex_lock(&__pmic_glink_lock); + if (!pg) { + ret = dev_err_probe(&rpdev->dev, -ENODEV, "no pmic_glink device to attach to\n"); + goto out_unlock; + } + + dev_set_drvdata(&rpdev->dev, pg); + + mutex_lock(&pg->state_lock); + pg->ept = rpdev->ept; + pmic_glink_state_notify_clients(pg); + mutex_unlock(&pg->state_lock); + +out_unlock: + mutex_unlock(&__pmic_glink_lock); + return ret; +} + +static void pmic_glink_rpmsg_remove(struct rpmsg_device *rpdev) +{ + struct pmic_glink *pg; + + mutex_lock(&__pmic_glink_lock); + pg = __pmic_glink; + if (!pg) + goto out_unlock; + + mutex_lock(&pg->state_lock); + pg->ept = NULL; + pmic_glink_state_notify_clients(pg); + mutex_unlock(&pg->state_lock); +out_unlock: + mutex_unlock(&__pmic_glink_lock); +} + +static const struct rpmsg_device_id pmic_glink_rpmsg_id_match[] = { + { "PMIC_RTR_ADSP_APPS" }, + {} +}; + +static struct rpmsg_driver pmic_glink_rpmsg_driver = { + .probe = pmic_glink_rpmsg_probe, + .remove = pmic_glink_rpmsg_remove, + .callback = pmic_glink_rpmsg_callback, + .id_table = pmic_glink_rpmsg_id_match, + .drv = { + .name = "qcom_pmic_glink_rpmsg", + }, +}; + +static int pmic_glink_probe(struct platform_device *pdev) +{ + struct pdr_service *service; + struct pmic_glink *pg; + int ret; + + pg = devm_kzalloc(&pdev->dev, sizeof(*pg), GFP_KERNEL); + if (!pg) + return -ENOMEM; + + dev_set_drvdata(&pdev->dev, pg); + + pg->dev = &pdev->dev; + + INIT_LIST_HEAD(&pg->clients); + mutex_init(&pg->client_lock); + mutex_init(&pg->state_lock); + + ret = pmic_glink_add_aux_device(pg, &pg->altmode_aux, "altmode"); + if (ret) + return ret; + ret = pmic_glink_add_aux_device(pg, &pg->ps_aux, "power-supply"); + if (ret) + goto out_release_altmode_aux; + + pg->pdr = pdr_handle_alloc(pmic_glink_pdr_callback, pg); + if (IS_ERR(pg->pdr)) { + ret = dev_err_probe(&pdev->dev, PTR_ERR(pg->pdr), "failed to initialize pdr\n"); + goto out_release_aux_devices; + } + + service = pdr_add_lookup(pg->pdr, "tms/servreg", "msm/adsp/charger_pd"); + if (IS_ERR(service)) { + ret = dev_err_probe(&pdev->dev, PTR_ERR(service), + "failed adding pdr lookup for charger_pd\n"); + goto out_release_pdr_handle; + } + + mutex_lock(&__pmic_glink_lock); + __pmic_glink = pg; + mutex_unlock(&__pmic_glink_lock); + + return 0; + +out_release_pdr_handle: + pdr_handle_release(pg->pdr); +out_release_aux_devices: + pmic_glink_del_aux_device(pg, &pg->ps_aux); +out_release_altmode_aux: + pmic_glink_del_aux_device(pg, &pg->altmode_aux); + + return ret; +} + +static int pmic_glink_remove(struct platform_device *pdev) +{ + struct pmic_glink *pg = dev_get_drvdata(&pdev->dev); + + pdr_handle_release(pg->pdr); + + pmic_glink_del_aux_device(pg, &pg->ps_aux); + pmic_glink_del_aux_device(pg, &pg->altmode_aux); + + mutex_lock(&__pmic_glink_lock); + __pmic_glink = NULL; + mutex_unlock(&__pmic_glink_lock); + + return 0; +} + +static const struct of_device_id pmic_glink_of_match[] = { + { .compatible = "qcom,pmic-glink", }, + {} +}; +MODULE_DEVICE_TABLE(of, pmic_glink_of_match); + +static struct platform_driver pmic_glink_driver = { + .probe = pmic_glink_probe, + .remove = pmic_glink_remove, + .driver = { + .name = "qcom_pmic_glink", + .of_match_table = pmic_glink_of_match, + }, +}; + +static int pmic_glink_init(void) +{ + platform_driver_register(&pmic_glink_driver); + register_rpmsg_driver(&pmic_glink_rpmsg_driver); + + return 0; +}; +module_init(pmic_glink_init); + +static void pmic_glink_exit(void) +{ + unregister_rpmsg_driver(&pmic_glink_rpmsg_driver); + platform_driver_unregister(&pmic_glink_driver); +}; +module_exit(pmic_glink_exit); + +MODULE_DESCRIPTION("Qualcomm PMIC GLINK driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/soc/qcom/pmic_glink.h b/include/linux/soc/qcom/pmic_glink.h new file mode 100644 index 000000000000..fd124aa18c81 --- /dev/null +++ b/include/linux/soc/qcom/pmic_glink.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022, Linaro Ltd + */ +#ifndef __SOC_QCOM_PMIC_GLINK_H__ +#define __SOC_QCOM_PMIC_GLINK_H__ + +struct pmic_glink; +struct pmic_glink_client; + +#define PMIC_GLINK_OWNER_BATTMGR 32778 +#define PMIC_GLINK_OWNER_USBC 32779 +#define PMIC_GLINK_OWNER_USBC_PAN 32780 + +#define PMIC_GLINK_REQ_RESP 1 +#define PMIC_GLINK_NOTIFY 2 + +struct pmic_glink_hdr { + __le32 owner; + __le32 type; + __le32 opcode; +}; + +int pmic_glink_send(struct pmic_glink_client *client, void *data, size_t len); + +struct pmic_glink_client *devm_pmic_glink_register_client(struct device *dev, + unsigned int id, + void (*cb)(const void *, size_t, void *), + void (*pdr)(void *, int), + void *priv); + +#endif -- cgit v1.2.3 From 080b4e24852b1d5b66929f69344e6c3eeb963941 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 31 Jan 2023 20:18:52 -0800 Subject: soc: qcom: pmic_glink: Introduce altmode support With the PMIC GLINK service, the host OS subscribes to USB-C altmode messages, which are sent by the firmware to notify the host OS about state updates and HPD interrupts. The pmic_glink_altmode driver registers for these notifications and propagates the notifications as typec_mux, typec_switch and DRM OOB notifications as necessary to implement DisplayPort altmode support. Signed-off-by: Bjorn Andersson Acked-by: Neil Armstrong Tested-by: Konrad Dybcio # SM8350 PDX215 Reviewed-by: Neil Armstrong Tested-by: Neil Armstrong # on SM8550-MTP & SM8450-HDK Signed-off-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230201041853.1934355-4-quic_bjorande@quicinc.com --- drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/pmic_glink_altmode.c | 478 ++++++++++++++++++++++++++++++++++ 2 files changed, 479 insertions(+) create mode 100644 drivers/soc/qcom/pmic_glink_altmode.c (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index fbbd1231e554..8d62a17863c1 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o obj-$(CONFIG_QCOM_OCMEM) += ocmem.o obj-$(CONFIG_QCOM_PDR_HELPERS) += pdr_interface.o obj-$(CONFIG_QCOM_PMIC_GLINK) += pmic_glink.o +obj-$(CONFIG_QCOM_PMIC_GLINK) += pmic_glink_altmode.o obj-$(CONFIG_QCOM_QMI_HELPERS) += qmi_helpers.o qmi_helpers-y += qmi_encdec.o qmi_interface.o obj-$(CONFIG_QCOM_RMTFS_MEM) += rmtfs_mem.o diff --git a/drivers/soc/qcom/pmic_glink_altmode.c b/drivers/soc/qcom/pmic_glink_altmode.c new file mode 100644 index 000000000000..71f861b8cb51 --- /dev/null +++ b/drivers/soc/qcom/pmic_glink_altmode.c @@ -0,0 +1,478 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Ltd + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#define PMIC_GLINK_MAX_PORTS 2 + +#define USBC_SC8180X_NOTIFY_IND 0x13 +#define USBC_CMD_WRITE_REQ 0x15 +#define USBC_NOTIFY_IND 0x16 + +#define ALTMODE_PAN_EN 0x10 +#define ALTMODE_PAN_ACK 0x11 + +struct usbc_write_req { + struct pmic_glink_hdr hdr; + __le32 cmd; + __le32 arg; + __le32 reserved; +}; + +#define NOTIFY_PAYLOAD_SIZE 16 +struct usbc_notify { + struct pmic_glink_hdr hdr; + char payload[NOTIFY_PAYLOAD_SIZE]; + u32 reserved; +}; + +struct usbc_sc8180x_notify { + struct pmic_glink_hdr hdr; + __le32 notification; + __le32 reserved[2]; +}; + +enum pmic_glink_altmode_pin_assignment { + DPAM_HPD_OUT, + DPAM_HPD_A, + DPAM_HPD_B, + DPAM_HPD_C, + DPAM_HPD_D, + DPAM_HPD_E, + DPAM_HPD_F, +}; + +struct pmic_glink_altmode; + +#define work_to_altmode_port(w) container_of((w), struct pmic_glink_altmode_port, work) + +struct pmic_glink_altmode_port { + struct pmic_glink_altmode *altmode; + unsigned int index; + + struct typec_switch *typec_switch; + struct typec_mux *typec_mux; + struct typec_mux_state state; + struct typec_altmode dp_alt; + + struct work_struct work; + + struct drm_bridge bridge; + + enum typec_orientation orientation; + u16 svid; + u8 dp_data; + u8 mode; + u8 hpd_state; + u8 hpd_irq; +}; + +#define work_to_altmode(w) container_of((w), struct pmic_glink_altmode, enable_work) + +struct pmic_glink_altmode { + struct device *dev; + + unsigned int owner_id; + + /* To synchronize WRITE_REQ acks */ + struct mutex lock; + + struct completion pan_ack; + struct pmic_glink_client *client; + + struct work_struct enable_work; + + struct pmic_glink_altmode_port ports[PMIC_GLINK_MAX_PORTS]; +}; + +static int pmic_glink_altmode_request(struct pmic_glink_altmode *altmode, u32 cmd, u32 arg) +{ + struct usbc_write_req req = {}; + unsigned long left; + int ret; + + /* + * The USBC_CMD_WRITE_REQ ack doesn't identify the request, so wait for + * one ack at a time. + */ + mutex_lock(&altmode->lock); + + req.hdr.owner = cpu_to_le32(altmode->owner_id); + req.hdr.type = cpu_to_le32(PMIC_GLINK_REQ_RESP); + req.hdr.opcode = cpu_to_le32(USBC_CMD_WRITE_REQ); + req.cmd = cpu_to_le32(cmd); + req.arg = cpu_to_le32(arg); + + ret = pmic_glink_send(altmode->client, &req, sizeof(req)); + if (ret) { + dev_err(altmode->dev, "failed to send altmode request: %#x (%d)\n", cmd, ret); + goto out_unlock; + } + + left = wait_for_completion_timeout(&altmode->pan_ack, 5 * HZ); + if (!left) { + dev_err(altmode->dev, "timeout waiting for altmode request ack for: %#x\n", cmd); + ret = -ETIMEDOUT; + } + +out_unlock: + mutex_unlock(&altmode->lock); + return ret; +} + +static void pmic_glink_altmode_enable_dp(struct pmic_glink_altmode *altmode, + struct pmic_glink_altmode_port *port, + u8 mode, bool hpd_state, + bool hpd_irq) +{ + struct typec_displayport_data dp_data = {}; + int ret; + + dp_data.status = DP_STATUS_ENABLED; + if (hpd_state) + dp_data.status |= DP_STATUS_HPD_STATE; + if (hpd_irq) + dp_data.status |= DP_STATUS_IRQ_HPD; + dp_data.conf = DP_CONF_SET_PIN_ASSIGN(mode); + + port->state.alt = &port->dp_alt; + port->state.data = &dp_data; + port->state.mode = TYPEC_MODAL_STATE(mode); + + ret = typec_mux_set(port->typec_mux, &port->state); + if (ret) + dev_err(altmode->dev, "failed to switch mux to DP\n"); +} + +static void pmic_glink_altmode_enable_usb(struct pmic_glink_altmode *altmode, + struct pmic_glink_altmode_port *port) +{ + int ret; + + port->state.alt = NULL; + port->state.data = NULL; + port->state.mode = TYPEC_STATE_USB; + + ret = typec_mux_set(port->typec_mux, &port->state); + if (ret) + dev_err(altmode->dev, "failed to switch mux to USB\n"); +} + +static void pmic_glink_altmode_worker(struct work_struct *work) +{ + struct pmic_glink_altmode_port *alt_port = work_to_altmode_port(work); + struct pmic_glink_altmode *altmode = alt_port->altmode; + + typec_switch_set(alt_port->typec_switch, alt_port->orientation); + + if (alt_port->svid == USB_TYPEC_DP_SID) + pmic_glink_altmode_enable_dp(altmode, alt_port, alt_port->mode, + alt_port->hpd_state, alt_port->hpd_irq); + else + pmic_glink_altmode_enable_usb(altmode, alt_port); + + if (alt_port->hpd_state) + drm_bridge_hpd_notify(&alt_port->bridge, connector_status_connected); + else + drm_bridge_hpd_notify(&alt_port->bridge, connector_status_disconnected); + + pmic_glink_altmode_request(altmode, ALTMODE_PAN_ACK, alt_port->index); +}; + +static enum typec_orientation pmic_glink_altmode_orientation(unsigned int orientation) +{ + if (orientation == 0) + return TYPEC_ORIENTATION_NORMAL; + else if (orientation == 1) + return TYPEC_ORIENTATION_REVERSE; + else + return TYPEC_ORIENTATION_NONE; +} + +#define SC8180X_PORT_MASK 0x000000ff +#define SC8180X_ORIENTATION_MASK 0x0000ff00 +#define SC8180X_MUX_MASK 0x00ff0000 +#define SC8180X_MODE_MASK 0x3f000000 +#define SC8180X_HPD_STATE_MASK 0x40000000 +#define SC8180X_HPD_IRQ_MASK 0x80000000 + +static void pmic_glink_altmode_sc8180xp_notify(struct pmic_glink_altmode *altmode, + const void *data, size_t len) +{ + struct pmic_glink_altmode_port *alt_port; + const struct usbc_sc8180x_notify *msg; + u32 notification; + u8 orientation; + u8 hpd_state; + u8 hpd_irq; + u16 svid; + u8 port; + u8 mode; + u8 mux; + + if (len != sizeof(*msg)) { + dev_warn(altmode->dev, "invalid length of USBC_NOTIFY indication: %zd\n", len); + return; + } + + msg = data; + notification = le32_to_cpu(msg->notification); + port = FIELD_GET(SC8180X_PORT_MASK, notification); + orientation = FIELD_GET(SC8180X_ORIENTATION_MASK, notification); + mux = FIELD_GET(SC8180X_MUX_MASK, notification); + mode = FIELD_GET(SC8180X_MODE_MASK, notification); + hpd_state = FIELD_GET(SC8180X_HPD_STATE_MASK, notification); + hpd_irq = FIELD_GET(SC8180X_HPD_IRQ_MASK, notification); + + svid = mux == 2 ? USB_TYPEC_DP_SID : 0; + + if (!altmode->ports[port].altmode) { + dev_dbg(altmode->dev, "notification on undefined port %d\n", port); + return; + } + + alt_port = &altmode->ports[port]; + alt_port->orientation = pmic_glink_altmode_orientation(orientation); + alt_port->svid = mux == 2 ? USB_TYPEC_DP_SID : 0; + alt_port->mode = mode; + alt_port->hpd_state = hpd_state; + alt_port->hpd_irq = hpd_irq; + schedule_work(&alt_port->work); +} + +#define SC8280XP_DPAM_MASK 0x3f +#define SC8280XP_HPD_STATE_MASK BIT(6) +#define SC8280XP_HPD_IRQ_MASK BIT(7) + +static void pmic_glink_altmode_sc8280xp_notify(struct pmic_glink_altmode *altmode, + u16 svid, const void *data, size_t len) +{ + struct pmic_glink_altmode_port *alt_port; + const struct usbc_notify *notify; + u8 orientation; + u8 hpd_state; + u8 hpd_irq; + u8 mode; + u8 port; + + if (len != sizeof(*notify)) { + dev_warn(altmode->dev, "invalid length USBC_NOTIFY_IND: %zd\n", + len); + return; + } + + notify = data; + + port = notify->payload[0]; + orientation = notify->payload[1]; + mode = FIELD_GET(SC8280XP_DPAM_MASK, notify->payload[8]) - DPAM_HPD_A; + hpd_state = FIELD_GET(SC8280XP_HPD_STATE_MASK, notify->payload[8]); + hpd_irq = FIELD_GET(SC8280XP_HPD_IRQ_MASK, notify->payload[8]); + + if (!altmode->ports[port].altmode) { + dev_dbg(altmode->dev, "notification on undefined port %d\n", port); + return; + } + + alt_port = &altmode->ports[port]; + alt_port->orientation = pmic_glink_altmode_orientation(orientation); + alt_port->svid = svid; + alt_port->mode = mode; + alt_port->hpd_state = hpd_state; + alt_port->hpd_irq = hpd_irq; + schedule_work(&alt_port->work); +} + +static void pmic_glink_altmode_callback(const void *data, size_t len, void *priv) +{ + struct pmic_glink_altmode *altmode = priv; + const struct pmic_glink_hdr *hdr = data; + u16 opcode; + u16 svid; + + opcode = le32_to_cpu(hdr->opcode) & 0xff; + svid = le32_to_cpu(hdr->opcode) >> 16; + + switch (opcode) { + case USBC_CMD_WRITE_REQ: + complete(&altmode->pan_ack); + break; + case USBC_NOTIFY_IND: + pmic_glink_altmode_sc8280xp_notify(altmode, svid, data, len); + break; + case USBC_SC8180X_NOTIFY_IND: + pmic_glink_altmode_sc8180xp_notify(altmode, data, len); + break; + } +} + +static int pmic_glink_altmode_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + return flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR ? 0 : -EINVAL; +} + +static const struct drm_bridge_funcs pmic_glink_altmode_bridge_funcs = { + .attach = pmic_glink_altmode_attach, +}; + +static void pmic_glink_altmode_put_mux(void *data) +{ + typec_mux_put(data); +} + +static void pmic_glink_altmode_put_switch(void *data) +{ + typec_switch_put(data); +} + +static void pmic_glink_altmode_enable_worker(struct work_struct *work) +{ + struct pmic_glink_altmode *altmode = work_to_altmode(work); + int ret; + + ret = pmic_glink_altmode_request(altmode, ALTMODE_PAN_EN, 0); + if (ret) + dev_err(altmode->dev, "failed to request altmode notifications\n"); +} + +static void pmic_glink_altmode_pdr_notify(void *priv, int state) +{ + struct pmic_glink_altmode *altmode = priv; + + if (state == SERVREG_SERVICE_STATE_UP) + schedule_work(&altmode->enable_work); +} + +static const struct of_device_id pmic_glink_altmode_of_quirks[] = { + { .compatible = "qcom,sc8180x-pmic-glink", .data = (void *)PMIC_GLINK_OWNER_USBC }, + {} +}; + +static int pmic_glink_altmode_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct pmic_glink_altmode_port *alt_port; + struct pmic_glink_altmode *altmode; + struct typec_altmode_desc mux_desc = {}; + const struct of_device_id *match; + struct fwnode_handle *fwnode; + struct device *dev = &adev->dev; + u32 port; + int ret; + + altmode = devm_kzalloc(dev, sizeof(*altmode), GFP_KERNEL); + if (!altmode) + return -ENOMEM; + + altmode->dev = dev; + + match = of_match_device(pmic_glink_altmode_of_quirks, dev->parent); + if (match) + altmode->owner_id = (unsigned long)match->data; + else + altmode->owner_id = PMIC_GLINK_OWNER_USBC_PAN; + + INIT_WORK(&altmode->enable_work, pmic_glink_altmode_enable_worker); + init_completion(&altmode->pan_ack); + mutex_init(&altmode->lock); + + device_for_each_child_node(dev, fwnode) { + ret = fwnode_property_read_u32(fwnode, "reg", &port); + if (ret < 0) { + dev_err(dev, "missing reg property of %pOFn\n", fwnode); + return ret; + } + + if (port >= ARRAY_SIZE(altmode->ports)) { + dev_warn(dev, "invalid connector number, ignoring\n"); + continue; + } + + if (altmode->ports[port].altmode) { + dev_err(dev, "multiple connector definition for port %u\n", port); + return -EINVAL; + } + + alt_port = &altmode->ports[port]; + alt_port->altmode = altmode; + alt_port->index = port; + INIT_WORK(&alt_port->work, pmic_glink_altmode_worker); + + alt_port->bridge.funcs = &pmic_glink_altmode_bridge_funcs; + alt_port->bridge.of_node = to_of_node(fwnode); + alt_port->bridge.ops = DRM_BRIDGE_OP_HPD; + alt_port->bridge.type = DRM_MODE_CONNECTOR_USB; + + ret = devm_drm_bridge_add(dev, &alt_port->bridge); + if (ret) + return ret; + + alt_port->dp_alt.svid = USB_TYPEC_DP_SID; + alt_port->dp_alt.mode = USB_TYPEC_DP_MODE; + alt_port->dp_alt.active = 1; + + mux_desc.svid = USB_TYPEC_DP_SID; + mux_desc.mode = USB_TYPEC_DP_MODE; + alt_port->typec_mux = fwnode_typec_mux_get(fwnode, &mux_desc); + if (IS_ERR(alt_port->typec_mux)) + return dev_err_probe(dev, PTR_ERR(alt_port->typec_mux), + "failed to acquire mode-switch for port: %d\n", + port); + + ret = devm_add_action_or_reset(dev, pmic_glink_altmode_put_mux, + alt_port->typec_mux); + if (ret) + return ret; + + alt_port->typec_switch = fwnode_typec_switch_get(fwnode); + if (IS_ERR(alt_port->typec_switch)) + return dev_err_probe(dev, PTR_ERR(alt_port->typec_switch), + "failed to acquire orientation-switch for port: %d\n", + port); + + ret = devm_add_action_or_reset(dev, pmic_glink_altmode_put_switch, + alt_port->typec_switch); + if (ret) + return ret; + } + + altmode->client = devm_pmic_glink_register_client(dev, + altmode->owner_id, + pmic_glink_altmode_callback, + pmic_glink_altmode_pdr_notify, + altmode); + return PTR_ERR_OR_ZERO(altmode->client); +} + +static const struct auxiliary_device_id pmic_glink_altmode_id_table[] = { + { .name = "pmic_glink.altmode", }, + {}, +}; +MODULE_DEVICE_TABLE(auxiliary, pmic_glink_altmode_id_table); + +static struct auxiliary_driver pmic_glink_altmode_driver = { + .name = "pmic_glink_altmode", + .probe = pmic_glink_altmode_probe, + .id_table = pmic_glink_altmode_id_table, +}; + +module_auxiliary_driver(pmic_glink_altmode_driver); + +MODULE_DESCRIPTION("Qualcomm PMIC GLINK Altmode driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 9049453a56300b04164c78a8ae3fbd5c225483bc Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 6 Feb 2023 20:37:58 +0100 Subject: soc: qcom: pmic_glink: add CONFIG_NET/CONFIG_OF dependencies QMI is a network protocol, so anything using requires CONFIG_NET to be enabled as well: WARNING: unmet direct dependencies detected for QCOM_QMI_HELPERS Depends on [n]: NET [=n] Selected by [m]: - QCOM_PDR_HELPERS [=m] arm-linux-gnueabi-ld: drivers/soc/qcom/qmi_interface.o: in function `qmi_send_new_lookup': qmi_interface.c:(.text+0xf0): undefined reference to `kernel_sendmsg' Add the dependency to both QCOM_PDR_HELPERS and QCOM_PMIC_GLINK to make it clearly what the dependency is when another PDR user is added. pmic_glink also needs CONFIG_OF: drivers/soc/qcom/pmic_glink_altmode.c: In function 'pmic_glink_altmode_probe': drivers/soc/qcom/pmic_glink_altmode.c:418:33: error: 'struct drm_bridge' has no member named 'of_node' Fixes: 58ef4ece1e41 ("soc: qcom: pmic_glink: Introduce base PMIC GLINK driver") Signed-off-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230206193804.191343-1-arnd@kernel.org --- drivers/soc/qcom/Kconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 348fde2a8aae..a8f283086a21 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -91,12 +91,15 @@ config QCOM_OCMEM config QCOM_PDR_HELPERS tristate select QCOM_QMI_HELPERS + depends on NET config QCOM_PMIC_GLINK tristate "Qualcomm PMIC GLINK driver" depends on RPMSG depends on TYPEC depends on DRM + depends on NET + depends on OF select AUXILIARY_BUS select QCOM_PDR_HELPERS help -- cgit v1.2.3 From acdbf5f9b2c492505145f6e50c65418521a547c4 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 18 Jan 2023 19:23:29 -0800 Subject: soc: qcom: stats: Populate all subsystem debugfs files This driver relies on SMEM to populate items for each subsystem before the device probes. The items in SMEM that are being looked for are populated by the subsystems lazily, and therefore may not exist until the device has booted. For example, if I build this driver into the kernel on Trogdor Lazor and boot up, I don't see a 'modem' debugfs file populated, because the modem boots and populates the SMEM item after this driver probes. Always populate the files for the subsystems if they're in SMEM, and make the qcom_subsystem_sleep_stats_show() function return 0 if the SMEM items still isn't there. This way we can run a simple command like grep ^ /sys/kernel/debug/qcom_stats/* and collect the subsystem sleep stats without interspersed errors or missing details entirely because this driver probed first. Fixes: 1d7724690344 ("soc: qcom: Add Sleep stats driver") Cc: Matthias Kaehlcke Signed-off-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230119032329.2909383-1-swboyd@chromium.org --- drivers/soc/qcom/qcom_stats.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/qcom_stats.c b/drivers/soc/qcom/qcom_stats.c index 6228af057120..c207bb96c523 100644 --- a/drivers/soc/qcom/qcom_stats.c +++ b/drivers/soc/qcom/qcom_stats.c @@ -92,7 +92,7 @@ static int qcom_subsystem_sleep_stats_show(struct seq_file *s, void *unused) /* Items are allocated lazily, so lookup pointer each time */ stat = qcom_smem_get(subsystem->pid, subsystem->smem_item, NULL); if (IS_ERR(stat)) - return -EIO; + return 0; qcom_print_stats(s, stat); @@ -170,20 +170,14 @@ static void qcom_create_soc_sleep_stat_files(struct dentry *root, void __iomem * static void qcom_create_subsystem_stat_files(struct dentry *root, const struct stats_config *config) { - const struct sleep_stats *stat; int i; if (!config->subsystem_stats_in_smem) return; - for (i = 0; i < ARRAY_SIZE(subsystems); i++) { - stat = qcom_smem_get(subsystems[i].pid, subsystems[i].smem_item, NULL); - if (IS_ERR(stat)) - continue; - + for (i = 0; i < ARRAY_SIZE(subsystems); i++) debugfs_create_file(subsystems[i].name, 0400, root, (void *)&subsystems[i], &qcom_subsystem_sleep_stats_fops); - } } static int qcom_stats_probe(struct platform_device *pdev) -- cgit v1.2.3 From dcb4e7a57cbe8d85e4927f517ae28aab17596419 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Mon, 6 Feb 2023 05:58:31 -0800 Subject: soc: qcom: pmic_glink: remove redundant calculation of svid MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit gcc with W=1 reports drivers/soc/qcom/pmic_glink_altmode.c:223:13: error: variable ‘svid’ set but not used [-Werror=unused-but-set-variable] 223 | u16 svid; From reviewing the code, the setting of alt_port->svid does the same calculation. Both are not needed. For debuggablity, keep the setting of local svid. Signed-off-by: Tom Rix Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230206135831.1794583-1-trix@redhat.com --- drivers/soc/qcom/pmic_glink_altmode.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/pmic_glink_altmode.c b/drivers/soc/qcom/pmic_glink_altmode.c index 71f861b8cb51..4d7895bdeaf2 100644 --- a/drivers/soc/qcom/pmic_glink_altmode.c +++ b/drivers/soc/qcom/pmic_glink_altmode.c @@ -248,7 +248,7 @@ static void pmic_glink_altmode_sc8180xp_notify(struct pmic_glink_altmode *altmod alt_port = &altmode->ports[port]; alt_port->orientation = pmic_glink_altmode_orientation(orientation); - alt_port->svid = mux == 2 ? USB_TYPEC_DP_SID : 0; + alt_port->svid = svid; alt_port->mode = mode; alt_port->hpd_state = hpd_state; alt_port->hpd_irq = hpd_irq; -- cgit v1.2.3 From 64dc69f3f36a71a95bfed8054d49600a7872415e Mon Sep 17 00:00:00 2001 From: devi priya Date: Fri, 13 Jan 2023 20:33:05 +0530 Subject: soc: qcom: smd-rpm: Add IPQ9574 compatible Adding compatible string to support RPM communication over SMD for IPQ9574 SoC Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: devi priya Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230113150310.29709-2-quic_devipriy@quicinc.com --- drivers/soc/qcom/smd-rpm.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c index 7e3b6a7ea34c..523627d5d398 100644 --- a/drivers/soc/qcom/smd-rpm.c +++ b/drivers/soc/qcom/smd-rpm.c @@ -233,6 +233,7 @@ static void qcom_smd_rpm_remove(struct rpmsg_device *rpdev) static const struct of_device_id qcom_smd_rpm_of_match[] = { { .compatible = "qcom,rpm-apq8084" }, { .compatible = "qcom,rpm-ipq6018" }, + { .compatible = "qcom,rpm-ipq9574" }, { .compatible = "qcom,rpm-msm8226" }, { .compatible = "qcom,rpm-msm8909" }, { .compatible = "qcom,rpm-msm8916" }, -- cgit v1.2.3 From 6bdab60d5cbd7996e371305433e943a82cde0d4c Mon Sep 17 00:00:00 2001 From: Naman Jain Date: Fri, 27 Jan 2023 09:42:00 +0530 Subject: soc: qcom: socinfo: Add support for new field in revision 17 Add support for new field coming with socinfo structure under v17 to get hardware platform's oem variant id. This is to enable OEMs to have minor changes in the board, but to use the same platform subtype as the one supported by Qualcomm. The new field is to be used in platform overlay file. Default value is 0, reserved for Qualcomm platforms. Also, add debugfs support to read this field for a device. Signed-off-by: Naman Jain Reviewed-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230127041200.29094-1-quic_namajain@quicinc.com --- drivers/soc/qcom/socinfo.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 3b970a80f3aa..e24895f98600 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -174,6 +174,8 @@ struct socinfo { __le32 pcode; __le32 npartnamemap_offset; __le32 nnum_partname_mapping; + /* Version 17 */ + __le32 oem_variant; }; #ifdef CONFIG_DEBUG_FS @@ -196,6 +198,7 @@ struct socinfo_params { u32 nmodem_supported; u32 feature_code; u32 pcode; + u32 oem_variant; }; struct smem_image_version { @@ -593,6 +596,11 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, &qcom_socinfo->info.fmt); switch (qcom_socinfo->info.fmt) { + case SOCINFO_VERSION(0, 17): + qcom_socinfo->info.oem_variant = __le32_to_cpu(info->oem_variant); + debugfs_create_u32("oem_variant", 0444, qcom_socinfo->dbg_root, + &qcom_socinfo->info.oem_variant); + fallthrough; case SOCINFO_VERSION(0, 16): qcom_socinfo->info.feature_code = __le32_to_cpu(info->feature_code); qcom_socinfo->info.pcode = __le32_to_cpu(info->pcode); -- cgit v1.2.3 From 79802479250f4ea25b49571f982786c7ef42c43b Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Tue, 24 Jan 2023 15:32:36 +0100 Subject: soc: qcom: socinfo: Add Soc IDs for IPQ8064 and variants Add Soc IDs table entries for Qualcomm IPQ8064 and variants. Signed-off-by: Christian Marangi Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230124143236.1038-2-ansuelsmth@gmail.com --- drivers/soc/qcom/socinfo.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index e24895f98600..46d71d735947 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -284,6 +284,10 @@ static const struct soc_id soc_id[] = { { qcom_board_id(MSM8126) }, { qcom_board_id(APQ8026) }, { qcom_board_id(MSM8926) }, + { qcom_board_id(IPQ8062) }, + { qcom_board_id(IPQ8064) }, + { qcom_board_id(IPQ8066) }, + { qcom_board_id(IPQ8068) }, { qcom_board_id(MSM8326) }, { qcom_board_id(MSM8916) }, { qcom_board_id(MSM8994) }, @@ -339,6 +343,8 @@ static const struct soc_id soc_id[] = { { qcom_board_id(MSM8609) }, { qcom_board_id(APQ8076) }, { qcom_board_id(MSM8976) }, + { qcom_board_id(IPQ8065) }, + { qcom_board_id(IPQ8069) }, { qcom_board_id(MDM9650) }, { qcom_board_id(MDM9655) }, { qcom_board_id(MDM9250) }, -- cgit v1.2.3 From 3bf90eca76c98c55c975fa817799789b9176f9f3 Mon Sep 17 00:00:00 2001 From: Elliot Berman Date: Fri, 3 Feb 2023 13:09:52 -0800 Subject: firmware: qcom_scm: Move qcom_scm.h to include/linux/firmware/qcom/ Move include/linux/qcom_scm.h to include/linux/firmware/qcom/qcom_scm.h. This removes 1 of a few remaining Qualcomm-specific headers into a more approciate subdirectory under include/. Suggested-by: Bjorn Andersson Signed-off-by: Elliot Berman Reviewed-by: Guru Das Srinagesh Acked-by: Mukesh Ojha Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230203210956.3580811-1-quic_eberman@quicinc.com --- arch/arm/mach-qcom/platsmp.c | 2 +- drivers/cpuidle/cpuidle-qcom-spm.c | 2 +- drivers/firmware/qcom_scm-legacy.c | 2 +- drivers/firmware/qcom_scm-smc.c | 2 +- drivers/firmware/qcom_scm.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c | 2 +- drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 2 +- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 +- drivers/iommu/arm/arm-smmu/qcom_iommu.c | 2 +- drivers/media/platform/qcom/venus/firmware.c | 2 +- drivers/misc/fastrpc.c | 2 +- drivers/mmc/host/sdhci-msm.c | 2 +- drivers/net/ipa/ipa_main.c | 2 +- drivers/net/wireless/ath/ath10k/qmi.c | 2 +- drivers/pinctrl/qcom/pinctrl-msm.c | 2 +- drivers/remoteproc/qcom_q6v5_mss.c | 2 +- drivers/remoteproc/qcom_q6v5_pas.c | 2 +- drivers/remoteproc/qcom_wcnss.c | 2 +- drivers/soc/qcom/mdt_loader.c | 2 +- drivers/soc/qcom/ocmem.c | 2 +- drivers/soc/qcom/rmtfs_mem.c | 2 +- drivers/thermal/qcom/lmh.c | 2 +- drivers/ufs/host/ufs-qcom-ice.c | 2 +- include/linux/firmware/qcom/qcom_scm.h | 125 +++++++++++++++++++++++ include/linux/qcom_scm.h | 125 ----------------------- 27 files changed, 150 insertions(+), 150 deletions(-) create mode 100644 include/linux/firmware/qcom/qcom_scm.h delete mode 100644 include/linux/qcom_scm.h (limited to 'drivers/soc') diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c index 5d2f386a46d8..eca2fe0f4314 100644 --- a/arch/arm/mach-qcom/platsmp.c +++ b/arch/arm/mach-qcom/platsmp.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include diff --git a/drivers/cpuidle/cpuidle-qcom-spm.c b/drivers/cpuidle/cpuidle-qcom-spm.c index beedf22cbe78..4ac83918edf2 100644 --- a/drivers/cpuidle/cpuidle-qcom-spm.c +++ b/drivers/cpuidle/cpuidle-qcom-spm.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/firmware/qcom_scm-legacy.c b/drivers/firmware/qcom_scm-legacy.c index 9f918b9e6f8f..029e6d117cb8 100644 --- a/drivers/firmware/qcom_scm-legacy.c +++ b/drivers/firmware/qcom_scm-legacy.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/firmware/qcom_scm-smc.c b/drivers/firmware/qcom_scm-smc.c index bb3235a64b8f..16cf88acfa8e 100644 --- a/drivers/firmware/qcom_scm-smc.c +++ b/drivers/firmware/qcom_scm-smc.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 2000323722bf..468d4d5ab550 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 660ba0db8900..d09221f97f71 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 57586c794b84..89ff978b81bb 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -8,7 +8,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c b/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c index e7748461cffc..0752fe373351 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c @@ -3,7 +3,7 @@ */ #include "hdmi.h" -#include +#include #define HDCP_REG_ENABLE 0x01 #define HDCP_REG_DISABLE 0x00 diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c index 74e9ef2fd580..b5b14108e086 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c @@ -4,7 +4,7 @@ */ #include -#include +#include #include #include "arm-smmu.h" diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 91d404deb115..ef42329e82ce 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include "arm-smmu.h" #include "arm-smmu-qcom.h" diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c index 270c3d9128ba..1e0b7b2e9fbd 100644 --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/media/platform/qcom/venus/firmware.c b/drivers/media/platform/qcom/venus/firmware.c index 142d4c74017c..e5759d7e9ede 100644 --- a/drivers/media/platform/qcom/venus/firmware.c +++ b/drivers/media/platform/qcom/venus/firmware.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index c9902a1dcf5d..04f80e754477 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 4ac8651d0b29..8ac81d57a3df 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c index 4fb92f771974..90baf7a54d9a 100644 --- a/drivers/net/ipa/ipa_main.c +++ b/drivers/net/ipa/ipa_main.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include "ipa.h" diff --git a/drivers/net/wireless/ath/ath10k/qmi.c b/drivers/net/wireless/ath/ath10k/qmi.c index 3f94fbf83702..90f457b8e1fe 100644 --- a/drivers/net/wireless/ath/ath10k/qmi.c +++ b/drivers/net/wireless/ath/ath10k/qmi.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 47e9a8b0d474..e0128c69bfbf 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c index fddb63cffee0..da2513bb6387 100644 --- a/drivers/remoteproc/qcom_q6v5_mss.c +++ b/drivers/remoteproc/qcom_q6v5_mss.c @@ -34,7 +34,7 @@ #include "qcom_pil_info.h" #include "qcom_q6v5.h" -#include +#include #define MPSS_CRASH_REASON_SMEM 421 diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index dc6f07ca8341..d5a049669616 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/remoteproc/qcom_wcnss.c b/drivers/remoteproc/qcom_wcnss.c index 68f37296b151..9881443cb8df 100644 --- a/drivers/remoteproc/qcom_wcnss.c +++ b/drivers/remoteproc/qcom_wcnss.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index 3f11554df2f3..33dd8c315eb7 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/soc/qcom/ocmem.c b/drivers/soc/qcom/ocmem.c index c92d26b73e6f..199fe9872035 100644 --- a/drivers/soc/qcom/ocmem.c +++ b/drivers/soc/qcom/ocmem.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/soc/qcom/rmtfs_mem.c b/drivers/soc/qcom/rmtfs_mem.c index 9d59ad509a5c..2d3ee22b9249 100644 --- a/drivers/soc/qcom/rmtfs_mem.c +++ b/drivers/soc/qcom/rmtfs_mem.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #define QCOM_RMTFS_MEM_DEV_MAX (MINORMASK + 1) #define NUM_MAX_VMIDS 2 diff --git a/drivers/thermal/qcom/lmh.c b/drivers/thermal/qcom/lmh.c index 4122a51e9874..f6edb12ec004 100644 --- a/drivers/thermal/qcom/lmh.c +++ b/drivers/thermal/qcom/lmh.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #define LMH_NODE_DCVS 0x44435653 #define LMH_CLUSTER0_NODE_ID 0x6370302D diff --git a/drivers/ufs/host/ufs-qcom-ice.c b/drivers/ufs/host/ufs-qcom-ice.c index 62387ccd5b30..453978877ae9 100644 --- a/drivers/ufs/host/ufs-qcom-ice.c +++ b/drivers/ufs/host/ufs-qcom-ice.c @@ -8,7 +8,7 @@ #include #include -#include +#include #include "ufs-qcom.h" diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h new file mode 100644 index 000000000000..1e449a5d7f5c --- /dev/null +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved. + * Copyright (C) 2015 Linaro Ltd. + */ +#ifndef __QCOM_SCM_H +#define __QCOM_SCM_H + +#include +#include +#include + +#include + +#define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF)) +#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0 +#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1 +#define QCOM_SCM_HDCP_MAX_REQ_CNT 5 + +struct qcom_scm_hdcp_req { + u32 addr; + u32 val; +}; + +struct qcom_scm_vmperm { + int vmid; + int perm; +}; + +enum qcom_scm_ocmem_client { + QCOM_SCM_OCMEM_UNUSED_ID = 0x0, + QCOM_SCM_OCMEM_GRAPHICS_ID, + QCOM_SCM_OCMEM_VIDEO_ID, + QCOM_SCM_OCMEM_LP_AUDIO_ID, + QCOM_SCM_OCMEM_SENSORS_ID, + QCOM_SCM_OCMEM_OTHER_OS_ID, + QCOM_SCM_OCMEM_DEBUG_ID, +}; + +enum qcom_scm_sec_dev_id { + QCOM_SCM_MDSS_DEV_ID = 1, + QCOM_SCM_OCMEM_DEV_ID = 5, + QCOM_SCM_PCIE0_DEV_ID = 11, + QCOM_SCM_PCIE1_DEV_ID = 12, + QCOM_SCM_GFX_DEV_ID = 18, + QCOM_SCM_UFS_DEV_ID = 19, + QCOM_SCM_ICE_DEV_ID = 20, +}; + +enum qcom_scm_ice_cipher { + QCOM_SCM_ICE_CIPHER_AES_128_XTS = 0, + QCOM_SCM_ICE_CIPHER_AES_128_CBC = 1, + QCOM_SCM_ICE_CIPHER_AES_256_XTS = 3, + QCOM_SCM_ICE_CIPHER_AES_256_CBC = 4, +}; + +#define QCOM_SCM_PERM_READ 0x4 +#define QCOM_SCM_PERM_WRITE 0x2 +#define QCOM_SCM_PERM_EXEC 0x1 +#define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE) +#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC) + +extern bool qcom_scm_is_available(void); + +extern int qcom_scm_set_cold_boot_addr(void *entry); +extern int qcom_scm_set_warm_boot_addr(void *entry); +extern void qcom_scm_cpu_power_down(u32 flags); +extern int qcom_scm_set_remote_state(u32 state, u32 id); + +struct qcom_scm_pas_metadata { + void *ptr; + dma_addr_t phys; + ssize_t size; +}; + +extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, + size_t size, + struct qcom_scm_pas_metadata *ctx); +void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx); +extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, + phys_addr_t size); +extern int qcom_scm_pas_auth_and_reset(u32 peripheral); +extern int qcom_scm_pas_shutdown(u32 peripheral); +extern bool qcom_scm_pas_supported(u32 peripheral); + +extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); +extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); + +extern bool qcom_scm_restore_sec_cfg_available(void); +extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare); +extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size); +extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare); +extern int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size); +extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size, + u32 cp_nonpixel_start, + u32 cp_nonpixel_size); +extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, + unsigned int *src, + const struct qcom_scm_vmperm *newvm, + unsigned int dest_cnt); + +extern bool qcom_scm_ocmem_lock_available(void); +extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, + u32 size, u32 mode); +extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, + u32 size); + +extern bool qcom_scm_ice_available(void); +extern int qcom_scm_ice_invalidate_key(u32 index); +extern int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size, + enum qcom_scm_ice_cipher cipher, + u32 data_unit_size); + +extern bool qcom_scm_hdcp_available(void); +extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, + u32 *resp); + +extern int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt); +extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en); + +extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, + u64 limit_node, u32 node_id, u64 version); +extern int qcom_scm_lmh_profile_change(u32 profile_id); +extern bool qcom_scm_lmh_dcvsh_available(void); + +#endif diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h deleted file mode 100644 index 1e449a5d7f5c..000000000000 --- a/include/linux/qcom_scm.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved. - * Copyright (C) 2015 Linaro Ltd. - */ -#ifndef __QCOM_SCM_H -#define __QCOM_SCM_H - -#include -#include -#include - -#include - -#define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF)) -#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0 -#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1 -#define QCOM_SCM_HDCP_MAX_REQ_CNT 5 - -struct qcom_scm_hdcp_req { - u32 addr; - u32 val; -}; - -struct qcom_scm_vmperm { - int vmid; - int perm; -}; - -enum qcom_scm_ocmem_client { - QCOM_SCM_OCMEM_UNUSED_ID = 0x0, - QCOM_SCM_OCMEM_GRAPHICS_ID, - QCOM_SCM_OCMEM_VIDEO_ID, - QCOM_SCM_OCMEM_LP_AUDIO_ID, - QCOM_SCM_OCMEM_SENSORS_ID, - QCOM_SCM_OCMEM_OTHER_OS_ID, - QCOM_SCM_OCMEM_DEBUG_ID, -}; - -enum qcom_scm_sec_dev_id { - QCOM_SCM_MDSS_DEV_ID = 1, - QCOM_SCM_OCMEM_DEV_ID = 5, - QCOM_SCM_PCIE0_DEV_ID = 11, - QCOM_SCM_PCIE1_DEV_ID = 12, - QCOM_SCM_GFX_DEV_ID = 18, - QCOM_SCM_UFS_DEV_ID = 19, - QCOM_SCM_ICE_DEV_ID = 20, -}; - -enum qcom_scm_ice_cipher { - QCOM_SCM_ICE_CIPHER_AES_128_XTS = 0, - QCOM_SCM_ICE_CIPHER_AES_128_CBC = 1, - QCOM_SCM_ICE_CIPHER_AES_256_XTS = 3, - QCOM_SCM_ICE_CIPHER_AES_256_CBC = 4, -}; - -#define QCOM_SCM_PERM_READ 0x4 -#define QCOM_SCM_PERM_WRITE 0x2 -#define QCOM_SCM_PERM_EXEC 0x1 -#define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE) -#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC) - -extern bool qcom_scm_is_available(void); - -extern int qcom_scm_set_cold_boot_addr(void *entry); -extern int qcom_scm_set_warm_boot_addr(void *entry); -extern void qcom_scm_cpu_power_down(u32 flags); -extern int qcom_scm_set_remote_state(u32 state, u32 id); - -struct qcom_scm_pas_metadata { - void *ptr; - dma_addr_t phys; - ssize_t size; -}; - -extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, - size_t size, - struct qcom_scm_pas_metadata *ctx); -void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx); -extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, - phys_addr_t size); -extern int qcom_scm_pas_auth_and_reset(u32 peripheral); -extern int qcom_scm_pas_shutdown(u32 peripheral); -extern bool qcom_scm_pas_supported(u32 peripheral); - -extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); -extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); - -extern bool qcom_scm_restore_sec_cfg_available(void); -extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare); -extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size); -extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare); -extern int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size); -extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size, - u32 cp_nonpixel_start, - u32 cp_nonpixel_size); -extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, - unsigned int *src, - const struct qcom_scm_vmperm *newvm, - unsigned int dest_cnt); - -extern bool qcom_scm_ocmem_lock_available(void); -extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, - u32 size, u32 mode); -extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, - u32 size); - -extern bool qcom_scm_ice_available(void); -extern int qcom_scm_ice_invalidate_key(u32 index); -extern int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size, - enum qcom_scm_ice_cipher cipher, - u32 data_unit_size); - -extern bool qcom_scm_hdcp_available(void); -extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, - u32 *resp); - -extern int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt); -extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en); - -extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, - u64 limit_node, u32 node_id, u64 version); -extern int qcom_scm_lmh_profile_change(u32 profile_id); -extern bool qcom_scm_lmh_dcvsh_available(void); - -#endif -- cgit v1.2.3 From b0bc8c893ae07acd4829a158e83902897a31a490 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Wed, 8 Feb 2023 11:27:09 +0530 Subject: soc: qcom: socinfo: Add IDs for IPQ5332 and its variant Add SOC ID for Qualcomm IPQ5332 and IPQ5322 variants. Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230208055709.13162-3-quic_kathirav@quicinc.com --- drivers/soc/qcom/socinfo.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 46d71d735947..e9012ca1a87b 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -448,6 +448,8 @@ static const struct soc_id soc_id[] = { { qcom_board_id(QRU1032) }, { qcom_board_id(QRU1052) }, { qcom_board_id(QRU1062) }, + { qcom_board_id(IPQ5332) }, + { qcom_board_id(IPQ5322) }, }; static const char *socinfo_machine(struct device *dev, unsigned int id) -- cgit v1.2.3 From 4a54ecf3031c6631515ae7a708b8ccd5f1bd1fe8 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Thu, 9 Feb 2023 09:23:59 -0800 Subject: soc: sunxi: SUN20I_PPU should depend on PM An $ARCH or a platform should select PM. Single device drivers should only depend on PM, not select it. Having SUN20I_PPU depend on PM removes a kconfig warning: WARNING: unmet direct dependencies detected for PM Depends on [n]: !MMU [=y] Selected by [y]: - SUN20I_PPU [=y] && (ARCH_SUNXI || COMPILE_TEST [=y]) Fixes: 0ad2185dcb5e ("soc: sunxi: select CONFIG_PM") Signed-off-by: Randy Dunlap Cc: Chen-Yu Tsai Cc: Jernej Skrabec Cc: Samuel Holland Cc: linux-arm-kernel@lists.infradead.org Cc: linux-sunxi@lists.linux.dev Cc: Arnd Bergmann Cc: Geert Uytterhoeven Signed-off-by: Arnd Bergmann --- drivers/soc/sunxi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/sunxi/Kconfig b/drivers/soc/sunxi/Kconfig index 02d0b338feb3..c5070914fc6a 100644 --- a/drivers/soc/sunxi/Kconfig +++ b/drivers/soc/sunxi/Kconfig @@ -23,7 +23,7 @@ config SUNXI_SRAM config SUN20I_PPU bool "Allwinner D1 PPU power domain driver" depends on ARCH_SUNXI || COMPILE_TEST - select PM + depends on PM select PM_GENERIC_DOMAINS help Say y to enable the PPU power domain driver. This saves power -- cgit v1.2.3 From 4ec98e6db9f24a9f4716685c62c9f6c348fec45b Mon Sep 17 00:00:00 2001 From: Asahi Lina Date: Sat, 11 Feb 2023 18:13:02 +0900 Subject: soc: apple: rtkit: Do not copy the reg state structure to the stack The register state struct is 848 bytes, which ends up bloating the apple_rtkit_crashlog_dump_regs stack frame beyond 1024 on some 32-bit platforms, triggering compile warnings. This doesn't matter for 64BIT/ARM64, but there's also no good reason to copy the structure to the stack in this case. We can use __packed to avoid alignment issues, there are no double-read hazards, and this is a fatal error path so performance does not matter. Fixes: 22991d8d5725 ("soc: apple: rtkit: Add register dump decoding to crashlog") Signed-off-by: Asahi Lina Reviewed-by: Eric Curtin Signed-off-by: Arnd Bergmann --- drivers/soc/apple/rtkit-crashlog.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/apple/rtkit-crashlog.c b/drivers/soc/apple/rtkit-crashlog.c index dfa74b32eda2..8319e365110b 100644 --- a/drivers/soc/apple/rtkit-crashlog.c +++ b/drivers/soc/apple/rtkit-crashlog.c @@ -57,7 +57,7 @@ struct apple_rtkit_crashlog_regs { u64 unk_X; u64 esr; u64 unk_Z; -}; +} __packed; static_assert(sizeof(struct apple_rtkit_crashlog_regs) == 0x350); static void apple_rtkit_crashlog_dump_str(struct apple_rtkit *rtk, u8 *bfr, @@ -126,18 +126,18 @@ static void apple_rtkit_crashlog_dump_mailbox(struct apple_rtkit *rtk, u8 *bfr, static void apple_rtkit_crashlog_dump_regs(struct apple_rtkit *rtk, u8 *bfr, size_t size) { - struct apple_rtkit_crashlog_regs regs; + struct apple_rtkit_crashlog_regs *regs; const char *el; int i; - if (size < sizeof(regs)) { + if (size < sizeof(*regs)) { dev_warn(rtk->dev, "RTKit: Regs section too small: 0x%zx", size); return; } - memcpy(®s, bfr, sizeof(regs)); + regs = (struct apple_rtkit_crashlog_regs *)bfr; - switch (regs.psr & PSR_MODE_MASK) { + switch (regs->psr & PSR_MODE_MASK) { case PSR_MODE_EL0t: el = "EL0t"; break; @@ -160,11 +160,11 @@ static void apple_rtkit_crashlog_dump_regs(struct apple_rtkit *rtk, u8 *bfr, dev_warn(rtk->dev, "RTKit: Exception dump:"); dev_warn(rtk->dev, " == Exception taken from %s ==", el); - dev_warn(rtk->dev, " PSR = 0x%llx", regs.psr); - dev_warn(rtk->dev, " PC = 0x%llx\n", regs.pc); - dev_warn(rtk->dev, " ESR = 0x%llx\n", regs.esr); - dev_warn(rtk->dev, " FAR = 0x%llx\n", regs.far); - dev_warn(rtk->dev, " SP = 0x%llx\n", regs.sp); + dev_warn(rtk->dev, " PSR = 0x%llx", regs->psr); + dev_warn(rtk->dev, " PC = 0x%llx\n", regs->pc); + dev_warn(rtk->dev, " ESR = 0x%llx\n", regs->esr); + dev_warn(rtk->dev, " FAR = 0x%llx\n", regs->far); + dev_warn(rtk->dev, " SP = 0x%llx\n", regs->sp); dev_warn(rtk->dev, "\n"); for (i = 0; i < 31; i += 4) { @@ -172,12 +172,12 @@ static void apple_rtkit_crashlog_dump_regs(struct apple_rtkit *rtk, u8 *bfr, dev_warn(rtk->dev, " x%02d-x%02d = %016llx %016llx %016llx %016llx\n", i, i + 3, - regs.regs[i], regs.regs[i + 1], - regs.regs[i + 2], regs.regs[i + 3]); + regs->regs[i], regs->regs[i + 1], + regs->regs[i + 2], regs->regs[i + 3]); else dev_warn(rtk->dev, " x%02d-x%02d = %016llx %016llx %016llx\n", i, i + 3, - regs.regs[i], regs.regs[i + 1], regs.regs[i + 2]); + regs->regs[i], regs->regs[i + 1], regs->regs[i + 2]); } dev_warn(rtk->dev, "\n"); -- cgit v1.2.3