From 0d3d30db93635936652417efd0f4a3e9049d0938 Mon Sep 17 00:00:00 2001 From: Abhilash Kesavan Date: Thu, 9 Oct 2014 19:24:29 +0530 Subject: pinctrl: exynos: Generalize the eint16_31 demux code The function exynos_irq_demux_eint16_31 uses pre-defined offsets for external interrupt pending status and mask registers. So this function is not extensible for Exynos7 SoC which has these registers at different offsets. Generalize the exynos_irq_demux_eint16_31 function by using the pending/mask register offset values from the exynos_irq_chip structure. This is done by adding a irq_chip field to the samsung_pin_bank struct. Signed-off-by: Abhilash Kesavan Reviewed-by: Thomas Abraham Tested-by: Thomas Abraham Acked-by: Tomasz Figa Cc: Linus Walleij Signed-off-by: Tomasz Figa --- drivers/pinctrl/samsung/pinctrl-samsung.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/pinctrl/samsung/pinctrl-samsung.h') diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index ec43b7d49fb9..3076b8b591c7 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -151,6 +151,7 @@ struct samsung_pin_bank_data { * @irq_domain: IRQ domain of the bank. * @gpio_chip: GPIO chip of the bank. * @grange: linux gpio pin range supported by this bank. + * @irq_chip: link to irq chip for external gpio and wakeup interrupts. * @slock: spinlock protecting bank registers * @pm_save: saved register values during suspend */ @@ -171,6 +172,7 @@ struct samsung_pin_bank { struct irq_domain *irq_domain; struct gpio_chip gpio_chip; struct pinctrl_gpio_range grange; + struct exynos_irq_chip *irq_chip; spinlock_t slock; u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/ -- cgit v1.2.3