From 260f99591c8c4c27e9e023287151031df97bd6d5 Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Mon, 17 Jan 2022 01:26:40 +0100 Subject: drivers: phy: qcom: ipq806x-usb: convert to BITFIELD macro Convert some define to BITFIELD macro to tidy things up. Signed-off-by: Ansuel Smith Link: https://lore.kernel.org/r/20220117002641.26773-1-ansuelsmth@gmail.com Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'drivers/phy/qualcomm') diff --git a/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c index fec1da470d26..2aca0e28ff59 100644 --- a/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c @@ -10,6 +10,7 @@ #include #include #include +#include /* USB QSCRATCH Hardware registers */ #define QSCRATCH_GENERAL_CFG (0x08) @@ -74,20 +75,20 @@ PHY_PARAM_CTRL1_LOS_BIAS_MASK) #define PHY_PARAM_CTRL1_TX_FULL_SWING(x) \ - (((x) << 20) & PHY_PARAM_CTRL1_TX_FULL_SWING_MASK) + FIELD_PREP(PHY_PARAM_CTRL1_TX_FULL_SWING_MASK, (x)) #define PHY_PARAM_CTRL1_TX_DEEMPH_6DB(x) \ - (((x) << 14) & PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK) + FIELD_PREP(PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK, (x)) #define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(x) \ - (((x) << 8) & PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK) + FIELD_PREP(PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK, x) #define PHY_PARAM_CTRL1_LOS_BIAS(x) \ - (((x) << 3) & PHY_PARAM_CTRL1_LOS_BIAS_MASK) + FIELD_PREP(PHY_PARAM_CTRL1_LOS_BIAS_MASK, (x)) /* RX OVRD IN HI bits */ #define RX_OVRD_IN_HI_RX_RESET_OVRD BIT(13) #define RX_OVRD_IN_HI_RX_RX_RESET BIT(12) #define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11) #define RX_OVRD_IN_HI_RX_EQ_MASK GENMASK(10, 7) -#define RX_OVRD_IN_HI_RX_EQ(x) ((x) << 8) +#define RX_OVRD_IN_HI_RX_EQ(x) FIELD_PREP(RX_OVRD_IN_HI_RX_EQ_MASK, (x)) #define RX_OVRD_IN_HI_RX_EQ_EN_OVRD BIT(7) #define RX_OVRD_IN_HI_RX_EQ_EN BIT(6) #define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD BIT(5) -- cgit v1.2.3 From dc9d167737a5814c8dcbdc33a298dc4b9407bba5 Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Mon, 17 Jan 2022 01:26:41 +0100 Subject: drivers: phy: qcom: ipq806x-usb: conver latch function to pool macro Convert latch function to readl pool macro to tidy things up. Signed-off-by: Ansuel Smith Link: https://lore.kernel.org/r/20220117002641.26773-2-ansuelsmth@gmail.com Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) (limited to 'drivers/phy/qualcomm') diff --git a/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c index 2aca0e28ff59..7bacc527fbad 100644 --- a/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c @@ -112,6 +112,9 @@ #define SS_CR_READ_REG BIT(0) #define SS_CR_WRITE_REG BIT(0) +#define LATCH_SLEEP 40 +#define LATCH_TIMEOUT 100 + struct usb_phy { void __iomem *base; struct device *dev; @@ -157,19 +160,9 @@ static inline void usb_phy_write_readback(struct usb_phy *phy_dwc3, static int wait_for_latch(void __iomem *addr) { - u32 retry = 10; - - while (true) { - if (!readl(addr)) - break; - - if (--retry == 0) - return -ETIMEDOUT; - - usleep_range(10, 20); - } + u32 val; - return 0; + return readl_poll_timeout(addr, val, !val, LATCH_SLEEP, LATCH_TIMEOUT); } /** -- cgit v1.2.3 From 8456caa61c112ad8fdfcc1052f3d2881349ce9ea Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 12 Jan 2022 20:40:51 +0100 Subject: phy: qcom-qusb2: Add compatible for MSM8953 Add compatible for MSM8953 QUSB2 device which reuses MSM8996 configuration. Signed-off-by: Luca Weiss Acked-by: Konrad Dybcio Link: https://lore.kernel.org/r/20220112194118.178026-3-luca@z3ntu.xyz Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/phy/qualcomm') diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c index 032d02bf50c5..7529a7e6e5df 100644 --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c @@ -911,6 +911,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = { }, { .compatible = "qcom,ipq8074-qusb2-phy", .data = &msm8996_phy_cfg, + }, { + .compatible = "qcom,msm8953-qusb2-phy", + .data = &msm8996_phy_cfg, }, { .compatible = "qcom,msm8996-qusb2-phy", .data = &msm8996_phy_cfg, -- cgit v1.2.3 From cc62512c1be39f19dc4d5c9831c4ff00481f9de9 Mon Sep 17 00:00:00 2001 From: Sankeerth Billakanti Date: Mon, 7 Feb 2022 16:17:03 -0800 Subject: phy: qcom: Add support for eDP PHY on sc7280 The sc7280 platform supports native eDP controller and PHY. This change will add support for the eDP PHY on sc7280. Signed-off-by: Sankeerth Billakanti Reviewed-by: Stephen Boyd Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20220207161612.REPOST.v1.2.Iff75c0ea8499f0baf2aa5800f2c45c4128e2415a@changeid Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-edp.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/phy/qualcomm') diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index a8ecd2e8442d..21cafbb623f8 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -654,6 +654,7 @@ static int qcom_edp_phy_probe(struct platform_device *pdev) } static const struct of_device_id qcom_edp_phy_match_table[] = { + { .compatible = "qcom,sc7280-edp-phy" }, { .compatible = "qcom,sc8180x-edp-phy" }, { } }; -- cgit v1.2.3 From 4a4c3cc146b12fea3a25748c43abfb461978bcee Mon Sep 17 00:00:00 2001 From: Sankeerth Billakanti Date: Mon, 7 Feb 2022 16:17:04 -0800 Subject: phy: qcom: Program SSC only if supported by sink Some legacy eDP sinks may not support SSC. The support for SSC is indicated through an opts flag from the controller driver. This change will enable SSC only if the sink supports it. Signed-off-by: Sankeerth Billakanti Reviewed-by: Stephen Boyd Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20220207161612.REPOST.v1.3.Ie81d594ec2327dae6410db359cc492484bab171f@changeid Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-edp.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers/phy/qualcomm') diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index 21cafbb623f8..cacd32f6e0cc 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -335,9 +335,11 @@ static int qcom_edp_phy_power_on(struct phy *phy) writel(0x00, edp->tx0 + TXn_LANE_MODE_1); writel(0x00, edp->tx1 + TXn_LANE_MODE_1); - ret = qcom_edp_configure_ssc(edp); - if (ret) - return ret; + if (edp->dp_opts.ssc) { + ret = qcom_edp_configure_ssc(edp); + if (ret) + return ret; + } ret = qcom_edp_configure_pll(edp); if (ret) -- cgit v1.2.3 From 7addff4018f0d5b94a8f5816fa752ea05ccfa23e Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 24 Feb 2022 19:40:49 -0800 Subject: phy: qcom-snps: Add sc8280xp support The Qualcomm sc8280xp platform comes with a 5nm femto USB PHY which, in contrast to previously seen platforms, has the SIDDQ bit in the COMMON0 register default to high. So make the driver match on the 5nm compatible and make sure to clear the SIDDQ bit on phy_init. Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220225034049.2294207-2-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/phy/qualcomm') diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c index 7e61202aa234..5d203784f75d 100644 --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c @@ -32,6 +32,7 @@ #define POR BIT(1) #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) +#define SIDDQ BIT(2) #define RETENABLEN BIT(3) #define FSEL_MASK GENMASK(6, 4) #define FSEL_DEFAULT (0x3 << 4) @@ -233,6 +234,9 @@ static int qcom_snps_hsphy_init(struct phy *phy) qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM); + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, + SIDDQ, 0); + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, POR, 0); @@ -275,6 +279,7 @@ static const struct phy_ops qcom_snps_hsphy_gen_ops = { static const struct of_device_id qcom_snps_hsphy_of_match_table[] = { { .compatible = "qcom,sm8150-usb-hs-phy", }, + { .compatible = "qcom,usb-snps-hs-5nm-phy", }, { .compatible = "qcom,usb-snps-hs-7nm-phy", }, { .compatible = "qcom,usb-snps-femto-v2-phy", }, { } -- cgit v1.2.3 From c6455af548991ed22c89528f998fd965c052fb2e Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 24 Feb 2022 19:51:05 -0800 Subject: phy: qcom-qmp: add sc8280xp UFS PHY Reuse the SM8350 UFS PHY initialization sequence to add support for the same found in the Qualcomm SC8280XP platform. Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220225035105.2294599-2-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/phy/qualcomm') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 8ea87c69f463..b144ae1f729a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -5977,6 +5977,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { }, { .compatible = "qcom,sc8180x-qmp-ufs-phy", .data = &sm8150_ufsphy_cfg, + }, { + .compatible = "qcom,sc8280xp-qmp-ufs-phy", + .data = &sm8350_ufsphy_cfg, }, { .compatible = "qcom,sc8180x-qmp-usb3-phy", .data = &sm8150_usb3phy_cfg, -- cgit v1.2.3