From 78f6a6bd89e9a33e4be1bc61e6990a1172aa396e Mon Sep 17 00:00:00 2001 From: Francois Romieu Date: Sun, 21 Aug 2011 18:32:05 +0200 Subject: dl2k: use standard #defines from mii.h. Signed-off-by: Francois Romieu --- drivers/net/ethernet/dlink/dl2k.h | 110 +------------------------------------- 1 file changed, 2 insertions(+), 108 deletions(-) (limited to 'drivers/net/ethernet/dlink/dl2k.h') diff --git a/drivers/net/ethernet/dlink/dl2k.h b/drivers/net/ethernet/dlink/dl2k.h index 7caab3d26a9e..ba0adcafa55a 100644 --- a/drivers/net/ethernet/dlink/dl2k.h +++ b/drivers/net/ethernet/dlink/dl2k.h @@ -28,6 +28,7 @@ #include #include #include +#include #include #include /* Processor type for cache alignment. */ #include @@ -271,20 +272,9 @@ enum RFS_bits { #define MII_RESET_TIME_OUT 10000 /* MII register */ enum _mii_reg { - MII_BMCR = 0, - MII_BMSR = 1, - MII_PHY_ID1 = 2, - MII_PHY_ID2 = 3, - MII_ANAR = 4, - MII_ANLPAR = 5, - MII_ANER = 6, - MII_ANNPT = 7, - MII_ANLPRNP = 8, - MII_MSCR = 9, - MII_MSSR = 10, - MII_ESR = 15, MII_PHY_SCR = 16, }; + /* PCS register */ enum _pcs_reg { PCS_BMCR = 0, @@ -297,102 +287,6 @@ enum _pcs_reg { PCS_ESR = 15, }; -/* Basic Mode Control Register */ -enum _mii_bmcr { - MII_BMCR_RESET = 0x8000, - MII_BMCR_LOOP_BACK = 0x4000, - MII_BMCR_SPEED_LSB = 0x2000, - MII_BMCR_AN_ENABLE = 0x1000, - MII_BMCR_POWER_DOWN = 0x0800, - MII_BMCR_ISOLATE = 0x0400, - MII_BMCR_RESTART_AN = 0x0200, - MII_BMCR_DUPLEX_MODE = 0x0100, - MII_BMCR_COL_TEST = 0x0080, - MII_BMCR_SPEED_MSB = 0x0040, - MII_BMCR_SPEED_RESERVED = 0x003f, - MII_BMCR_SPEED_10 = 0, - MII_BMCR_SPEED_100 = MII_BMCR_SPEED_LSB, - MII_BMCR_SPEED_1000 = MII_BMCR_SPEED_MSB, -}; - -/* Basic Mode Status Register */ -enum _mii_bmsr { - MII_BMSR_100BT4 = 0x8000, - MII_BMSR_100BX_FD = 0x4000, - MII_BMSR_100BX_HD = 0x2000, - MII_BMSR_10BT_FD = 0x1000, - MII_BMSR_10BT_HD = 0x0800, - MII_BMSR_100BT2_FD = 0x0400, - MII_BMSR_100BT2_HD = 0x0200, - MII_BMSR_EXT_STATUS = 0x0100, - MII_BMSR_PREAMBLE_SUPP = 0x0040, - MII_BMSR_AN_COMPLETE = 0x0020, - MII_BMSR_REMOTE_FAULT = 0x0010, - MII_BMSR_AN_ABILITY = 0x0008, - MII_BMSR_LINK_STATUS = 0x0004, - MII_BMSR_JABBER_DETECT = 0x0002, - MII_BMSR_EXT_CAP = 0x0001, -}; - -/* ANAR */ -enum _mii_anar { - MII_ANAR_NEXT_PAGE = 0x8000, - MII_ANAR_REMOTE_FAULT = 0x4000, - MII_ANAR_ASYMMETRIC = 0x0800, - MII_ANAR_PAUSE = 0x0400, - MII_ANAR_100BT4 = 0x0200, - MII_ANAR_100BX_FD = 0x0100, - MII_ANAR_100BX_HD = 0x0080, - MII_ANAR_10BT_FD = 0x0020, - MII_ANAR_10BT_HD = 0x0010, - MII_ANAR_SELECTOR = 0x001f, - MII_IEEE8023_CSMACD = 0x0001, -}; - -/* ANLPAR */ -enum _mii_anlpar { - MII_ANLPAR_NEXT_PAGE = MII_ANAR_NEXT_PAGE, - MII_ANLPAR_REMOTE_FAULT = MII_ANAR_REMOTE_FAULT, - MII_ANLPAR_ASYMMETRIC = MII_ANAR_ASYMMETRIC, - MII_ANLPAR_PAUSE = MII_ANAR_PAUSE, - MII_ANLPAR_100BT4 = MII_ANAR_100BT4, - MII_ANLPAR_100BX_FD = MII_ANAR_100BX_FD, - MII_ANLPAR_100BX_HD = MII_ANAR_100BX_HD, - MII_ANLPAR_10BT_FD = MII_ANAR_10BT_FD, - MII_ANLPAR_10BT_HD = MII_ANAR_10BT_HD, - MII_ANLPAR_SELECTOR = MII_ANAR_SELECTOR, -}; - -/* Auto-Negotiation Expansion Register */ -enum _mii_aner { - MII_ANER_PAR_DETECT_FAULT = 0x0010, - MII_ANER_LP_NEXTPAGABLE = 0x0008, - MII_ANER_NETXTPAGABLE = 0x0004, - MII_ANER_PAGE_RECEIVED = 0x0002, - MII_ANER_LP_NEGOTIABLE = 0x0001, -}; - -/* MASTER-SLAVE Control Register */ -enum _mii_mscr { - MII_MSCR_TEST_MODE = 0xe000, - MII_MSCR_CFG_ENABLE = 0x1000, - MII_MSCR_CFG_VALUE = 0x0800, - MII_MSCR_PORT_VALUE = 0x0400, - MII_MSCR_1000BT_FD = 0x0200, - MII_MSCR_1000BT_HD = 0X0100, -}; - -/* MASTER-SLAVE Status Register */ -enum _mii_mssr { - MII_MSSR_CFG_FAULT = 0x8000, - MII_MSSR_CFG_RES = 0x4000, - MII_MSSR_LOCAL_RCV_STATUS = 0x2000, - MII_MSSR_REMOTE_RCVR = 0x1000, - MII_MSSR_LP_1000BT_FD = 0x0800, - MII_MSSR_LP_1000BT_HD = 0x0400, - MII_MSSR_IDLE_ERR_COUNT = 0x00ff, -}; - /* IEEE Extened Status Register */ enum _mii_esr { MII_ESR_1000BX_FD = 0x8000, -- cgit v1.2.3