From cfd95a634f49358ab8d2a759c637fef0b50e7583 Mon Sep 17 00:00:00 2001 From: Bill Pemberton Date: Mon, 3 Dec 2012 09:22:58 -0500 Subject: bnx2: remove __dev* attributes CONFIG_HOTPLUG is going away as an option. As result the __dev* markings will be going away. Remove use of __devinit, __devexit_p, __devinitdata, __devinitconst, and __devexit. Signed-off-by: Bill Pemberton Cc: Michael Chan Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/broadcom/bnx2.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'drivers/net/ethernet/broadcom/bnx2.c') diff --git a/drivers/net/ethernet/broadcom/bnx2.c b/drivers/net/ethernet/broadcom/bnx2.c index d4310700c7a7..e264e960a762 100644 --- a/drivers/net/ethernet/broadcom/bnx2.c +++ b/drivers/net/ethernet/broadcom/bnx2.c @@ -71,7 +71,7 @@ /* Time in jiffies before concluding the transmitter is hung. */ #define TX_TIMEOUT (5*HZ) -static char version[] __devinitdata = +static char version[] = "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; MODULE_AUTHOR("Michael Chan "); @@ -106,7 +106,7 @@ typedef enum { /* indexed by board_t, above */ static struct { char *name; -} board_info[] __devinitdata = { +} board_info[] = { { "Broadcom NetXtreme II BCM5706 1000Base-T" }, { "HP NC370T Multifunction Gigabit Server Adapter" }, { "HP NC370i Multifunction Gigabit Server Adapter" }, @@ -7896,7 +7896,7 @@ poll_bnx2(struct net_device *dev) } #endif -static void __devinit +static void bnx2_get_5709_media(struct bnx2 *bp) { u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL); @@ -7934,7 +7934,7 @@ bnx2_get_5709_media(struct bnx2 *bp) } } -static void __devinit +static void bnx2_get_pci_speed(struct bnx2 *bp) { u32 reg; @@ -7986,7 +7986,7 @@ bnx2_get_pci_speed(struct bnx2 *bp) } -static void __devinit +static void bnx2_read_vpd_fw_ver(struct bnx2 *bp) { int rc, i, j; @@ -8054,7 +8054,7 @@ vpd_done: kfree(data); } -static int __devinit +static int bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) { struct bnx2 *bp; @@ -8439,7 +8439,7 @@ err_out: return rc; } -static char * __devinit +static char * bnx2_bus_string(struct bnx2 *bp, char *str) { char *s = str; @@ -8505,7 +8505,7 @@ static const struct net_device_ops bnx2_netdev_ops = { #endif }; -static int __devinit +static int bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) { static int version_printed = 0; @@ -8573,7 +8573,7 @@ err_free: return rc; } -static void __devexit +static void bnx2_remove_one(struct pci_dev *pdev) { struct net_device *dev = pci_get_drvdata(pdev); @@ -8752,7 +8752,7 @@ static struct pci_driver bnx2_pci_driver = { .name = DRV_MODULE_NAME, .id_table = bnx2_pci_tbl, .probe = bnx2_init_one, - .remove = __devexit_p(bnx2_remove_one), + .remove = bnx2_remove_one, .suspend = bnx2_suspend, .resume = bnx2_resume, .err_handler = &bnx2_err_handler, -- cgit v1.2.3 From e503e0662447ce2bd7c0a73c90395c78ebee494c Mon Sep 17 00:00:00 2001 From: Michael Chan Date: Thu, 6 Dec 2012 10:33:08 +0000 Subject: bnx2: Rename register read and write macros with BNX2_ prefix for namespace consistency. Currently, these macro names conflict with similar macros in bnx2x.h, preventing the cnic driver from including both bnx2.h and bnx2x.h. Including bnx2x.h in cnic.c will remove many redundant definitions and simplify the interface. Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/ethernet/broadcom/bnx2.c | 636 +++++++++++++++++------------------ drivers/net/ethernet/broadcom/bnx2.h | 6 +- 2 files changed, 321 insertions(+), 321 deletions(-) (limited to 'drivers/net/ethernet/broadcom/bnx2.c') diff --git a/drivers/net/ethernet/broadcom/bnx2.c b/drivers/net/ethernet/broadcom/bnx2.c index e264e960a762..41fa6af2fd86 100644 --- a/drivers/net/ethernet/broadcom/bnx2.c +++ b/drivers/net/ethernet/broadcom/bnx2.c @@ -274,8 +274,8 @@ bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset) u32 val; spin_lock_bh(&bp->indirect_lock); - REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); - val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW); + BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); + val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW); spin_unlock_bh(&bp->indirect_lock); return val; } @@ -284,8 +284,8 @@ static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val) { spin_lock_bh(&bp->indirect_lock); - REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); - REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val); + BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); + BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val); spin_unlock_bh(&bp->indirect_lock); } @@ -309,18 +309,18 @@ bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) if (CHIP_NUM(bp) == CHIP_NUM_5709) { int i; - REG_WR(bp, BNX2_CTX_CTX_DATA, val); - REG_WR(bp, BNX2_CTX_CTX_CTRL, - offset | BNX2_CTX_CTX_CTRL_WRITE_REQ); + BNX2_WR(bp, BNX2_CTX_CTX_DATA, val); + BNX2_WR(bp, BNX2_CTX_CTX_CTRL, + offset | BNX2_CTX_CTX_CTRL_WRITE_REQ); for (i = 0; i < 5; i++) { - val = REG_RD(bp, BNX2_CTX_CTX_CTRL); + val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL); if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0) break; udelay(5); } } else { - REG_WR(bp, BNX2_CTX_DATA_ADR, offset); - REG_WR(bp, BNX2_CTX_DATA, val); + BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset); + BNX2_WR(bp, BNX2_CTX_DATA, val); } spin_unlock_bh(&bp->indirect_lock); } @@ -494,11 +494,11 @@ bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) int i, ret; if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { - val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); + val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; - REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); - REG_RD(bp, BNX2_EMAC_MDIO_MODE); + BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); + BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); udelay(40); } @@ -506,16 +506,16 @@ bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) val1 = (bp->phy_addr << 21) | (reg << 16) | BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT | BNX2_EMAC_MDIO_COMM_START_BUSY; - REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1); + BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1); for (i = 0; i < 50; i++) { udelay(10); - val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); + val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { udelay(5); - val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); + val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); val1 &= BNX2_EMAC_MDIO_COMM_DATA; break; @@ -532,11 +532,11 @@ bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) } if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { - val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); + val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; - REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); - REG_RD(bp, BNX2_EMAC_MDIO_MODE); + BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); + BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); udelay(40); } @@ -551,11 +551,11 @@ bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) int i, ret; if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { - val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); + val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; - REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); - REG_RD(bp, BNX2_EMAC_MDIO_MODE); + BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); + BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); udelay(40); } @@ -563,12 +563,12 @@ bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) val1 = (bp->phy_addr << 21) | (reg << 16) | val | BNX2_EMAC_MDIO_COMM_COMMAND_WRITE | BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT; - REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1); + BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1); for (i = 0; i < 50; i++) { udelay(10); - val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); + val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM); if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { udelay(5); break; @@ -581,11 +581,11 @@ bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) ret = 0; if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { - val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); + val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; - REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); - REG_RD(bp, BNX2_EMAC_MDIO_MODE); + BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1); + BNX2_RD(bp, BNX2_EMAC_MDIO_MODE); udelay(40); } @@ -601,10 +601,10 @@ bnx2_disable_int(struct bnx2 *bp) for (i = 0; i < bp->irq_nvecs; i++) { bnapi = &bp->bnx2_napi[i]; - REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | + BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); } - REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD); + BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD); } static void @@ -616,16 +616,16 @@ bnx2_enable_int(struct bnx2 *bp) for (i = 0; i < bp->irq_nvecs; i++) { bnapi = &bp->bnx2_napi[i]; - REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | - BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | - BNX2_PCICFG_INT_ACK_CMD_MASK_INT | - bnapi->last_status_idx); + BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | + BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | + BNX2_PCICFG_INT_ACK_CMD_MASK_INT | + bnapi->last_status_idx); - REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | - BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | - bnapi->last_status_idx); + BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | + BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | + bnapi->last_status_idx); } - REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); + BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); } static void @@ -1294,14 +1294,14 @@ bnx2_set_mac_link(struct bnx2 *bp) { u32 val; - REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620); + BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620); if (bp->link_up && (bp->line_speed == SPEED_1000) && (bp->duplex == DUPLEX_HALF)) { - REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff); + BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff); } /* Configure the EMAC mode register. */ - val = REG_RD(bp, BNX2_EMAC_MODE); + val = BNX2_RD(bp, BNX2_EMAC_MODE); val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | @@ -1333,25 +1333,25 @@ bnx2_set_mac_link(struct bnx2 *bp) /* Set the MAC to operate in the appropriate duplex mode. */ if (bp->duplex == DUPLEX_HALF) val |= BNX2_EMAC_MODE_HALF_DUPLEX; - REG_WR(bp, BNX2_EMAC_MODE, val); + BNX2_WR(bp, BNX2_EMAC_MODE, val); /* Enable/disable rx PAUSE. */ bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN; if (bp->flow_ctrl & FLOW_CTRL_RX) bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN; - REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode); + BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode); /* Enable/disable tx PAUSE. */ - val = REG_RD(bp, BNX2_EMAC_TX_MODE); + val = BNX2_RD(bp, BNX2_EMAC_TX_MODE); val &= ~BNX2_EMAC_TX_MODE_FLOW_EN; if (bp->flow_ctrl & FLOW_CTRL_TX) val |= BNX2_EMAC_TX_MODE_FLOW_EN; - REG_WR(bp, BNX2_EMAC_TX_MODE, val); + BNX2_WR(bp, BNX2_EMAC_TX_MODE, val); /* Acknowledge the interrupt. */ - REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE); + BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE); bnx2_init_all_rx_contexts(bp); } @@ -1554,7 +1554,7 @@ bnx2_set_link(struct bnx2 *bp) bnx2_5706s_force_link_dn(bp, 0); bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN; } - val = REG_RD(bp, BNX2_EMAC_STATUS); + val = BNX2_RD(bp, BNX2_EMAC_STATUS); bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); @@ -1942,8 +1942,8 @@ bnx2_send_heart_beat(struct bnx2 *bp) spin_lock(&bp->indirect_lock); msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK); addr = bp->shmem_base + BNX2_DRV_PULSE_MB; - REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr); - REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg); + BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr); + BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg); spin_unlock(&bp->indirect_lock); } @@ -2269,7 +2269,7 @@ bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy) bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; if (CHIP_NUM(bp) == CHIP_NUM_5706) - REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300); + BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300); if (bp->dev->mtu > 1500) { u32 val; @@ -2368,7 +2368,7 @@ __acquires(&bp->phy_lock) bp->mii_adv = MII_ADVERTISE; bp->mii_lpa = MII_LPA; - REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); + BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) goto setup_phy; @@ -2402,10 +2402,10 @@ bnx2_set_mac_loopback(struct bnx2 *bp) { u32 mac_mode; - mac_mode = REG_RD(bp, BNX2_EMAC_MODE); + mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE); mac_mode &= ~BNX2_EMAC_MODE_PORT; mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK; - REG_WR(bp, BNX2_EMAC_MODE, mac_mode); + BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode); bp->link_up = 1; return 0; } @@ -2431,13 +2431,13 @@ bnx2_set_phy_loopback(struct bnx2 *bp) msleep(100); } - mac_mode = REG_RD(bp, BNX2_EMAC_MODE); + mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE); mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK | BNX2_EMAC_MODE_25G_MODE); mac_mode |= BNX2_EMAC_MODE_PORT_GMII; - REG_WR(bp, BNX2_EMAC_MODE, mac_mode); + BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode); bp->link_up = 1; return 0; } @@ -2539,9 +2539,9 @@ bnx2_init_5709_context(struct bnx2 *bp) val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12); val |= (BCM_PAGE_BITS - 8) << 16; - REG_WR(bp, BNX2_CTX_COMMAND, val); + BNX2_WR(bp, BNX2_CTX_COMMAND, val); for (i = 0; i < 10; i++) { - val = REG_RD(bp, BNX2_CTX_COMMAND); + val = BNX2_RD(bp, BNX2_CTX_COMMAND); if (!(val & BNX2_CTX_COMMAND_MEM_INIT)) break; udelay(2); @@ -2557,16 +2557,16 @@ bnx2_init_5709_context(struct bnx2 *bp) else return -ENOMEM; - REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0, - (bp->ctx_blk_mapping[i] & 0xffffffff) | - BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID); - REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1, - (u64) bp->ctx_blk_mapping[i] >> 32); - REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i | - BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); + BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0, + (bp->ctx_blk_mapping[i] & 0xffffffff) | + BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID); + BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1, + (u64) bp->ctx_blk_mapping[i] >> 32); + BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i | + BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); for (j = 0; j < 10; j++) { - val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL); + val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL); if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ)) break; udelay(5); @@ -2612,8 +2612,8 @@ bnx2_init_context(struct bnx2 *bp) vcid_addr += (i << PHY_CTX_SHIFT); pcid_addr += (i << PHY_CTX_SHIFT); - REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr); - REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); + BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr); + BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); /* Zero out the context. */ for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) @@ -2633,7 +2633,7 @@ bnx2_alloc_bad_rbuf(struct bnx2 *bp) if (good_mbuf == NULL) return -ENOMEM; - REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, + BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE); good_mbuf_cnt = 0; @@ -2678,12 +2678,12 @@ bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos) val = (mac_addr[0] << 8) | mac_addr[1]; - REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val); + BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val); val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | (mac_addr[4] << 8) | mac_addr[5]; - REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val); + BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val); } static inline int @@ -2770,9 +2770,9 @@ bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event) old_link_state = sblk->status_attn_bits_ack & event; if (new_link_state != old_link_state) { if (new_link_state) - REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event); + BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event); else - REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event); + BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event); } else is_set = 0; @@ -3255,11 +3255,11 @@ next_rx: rxr->rx_prod = sw_prod; if (pg_ring_used) - REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); + BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); - REG_WR16(bp, rxr->rx_bidx_addr, sw_prod); + BNX2_WR16(bp, rxr->rx_bidx_addr, sw_prod); - REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); + BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); mmiowb(); @@ -3277,7 +3277,7 @@ bnx2_msi(int irq, void *dev_instance) struct bnx2 *bp = bnapi->bp; prefetch(bnapi->status_blk.msi); - REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, + BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); @@ -3321,18 +3321,18 @@ bnx2_interrupt(int irq, void *dev_instance) * the status block write. */ if ((sblk->status_idx == bnapi->last_status_idx) && - (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) & + (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) & BNX2_PCICFG_MISC_STATUS_INTA_VALUE)) return IRQ_NONE; - REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, + BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); /* Read back to deassert IRQ immediately to avoid too many * spurious interrupts. */ - REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD); + BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD); /* Return here if interrupt is shared and is disabled. */ if (unlikely(atomic_read(&bp->intr_sem) != 0)) @@ -3388,14 +3388,14 @@ bnx2_chk_missed_msi(struct bnx2 *bp) u32 msi_ctrl; if (bnx2_has_work(bnapi)) { - msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL); + msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL); if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE)) return; if (bnapi->last_status_idx == bp->idle_chk_status_idx) { - REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl & - ~BNX2_PCICFG_MSI_CONTROL_ENABLE); - REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl); + BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl & + ~BNX2_PCICFG_MSI_CONTROL_ENABLE); + BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl); bnx2_msi(bp->irq_tbl[0].vector, bnapi); } } @@ -3434,9 +3434,9 @@ static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi) /* This is needed to take care of transient status * during link changes. */ - REG_WR(bp, BNX2_HC_COMMAND, - bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); - REG_RD(bp, BNX2_HC_COMMAND); + BNX2_WR(bp, BNX2_HC_COMMAND, + bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); + BNX2_RD(bp, BNX2_HC_COMMAND); } } @@ -3473,9 +3473,9 @@ static int bnx2_poll_msix(struct napi_struct *napi, int budget) if (likely(!bnx2_has_fast_work(bnapi))) { napi_complete(napi); - REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | - BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | - bnapi->last_status_idx); + BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num | + BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | + bnapi->last_status_idx); break; } } @@ -3511,19 +3511,19 @@ static int bnx2_poll(struct napi_struct *napi, int budget) if (likely(!bnx2_has_work(bnapi))) { napi_complete(napi); if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) { - REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, - BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | - bnapi->last_status_idx); + BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, + BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | + bnapi->last_status_idx); break; } - REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, - BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | - BNX2_PCICFG_INT_ACK_CMD_MASK_INT | - bnapi->last_status_idx); - - REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, - BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | - bnapi->last_status_idx); + BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, + BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | + BNX2_PCICFG_INT_ACK_CMD_MASK_INT | + bnapi->last_status_idx); + + BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, + BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | + bnapi->last_status_idx); break; } } @@ -3561,8 +3561,8 @@ bnx2_set_rx_mode(struct net_device *dev) } else if (dev->flags & IFF_ALLMULTI) { for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { - REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), - 0xffffffff); + BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), + 0xffffffff); } sort_mode |= BNX2_RPM_SORT_USER0_MC_EN; } @@ -3584,8 +3584,8 @@ bnx2_set_rx_mode(struct net_device *dev) } for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { - REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), - mc_filter[i]); + BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), + mc_filter[i]); } sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN; @@ -3610,12 +3610,12 @@ bnx2_set_rx_mode(struct net_device *dev) if (rx_mode != bp->rx_mode) { bp->rx_mode = rx_mode; - REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode); + BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode); } - REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0); - REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode); - REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA); + BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0); + BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode); + BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA); spin_unlock_bh(&bp->phy_lock); } @@ -3756,13 +3756,13 @@ load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc, } for (i = 0; i < rv2p_code_len; i += 8) { - REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code)); + BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code)); rv2p_code++; - REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code)); + BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code)); rv2p_code++; val = (i / 8) | cmd; - REG_WR(bp, addr, val); + BNX2_WR(bp, addr, val); } rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset); @@ -3772,22 +3772,22 @@ load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc, loc = be32_to_cpu(fw_entry->fixup[i]); if (loc && ((loc * 4) < rv2p_code_len)) { code = be32_to_cpu(*(rv2p_code + loc - 1)); - REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code); + BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code); code = be32_to_cpu(*(rv2p_code + loc)); code = rv2p_fw_fixup(rv2p_proc, i, loc, code); - REG_WR(bp, BNX2_RV2P_INSTR_LOW, code); + BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code); val = (loc / 2) | cmd; - REG_WR(bp, addr, val); + BNX2_WR(bp, addr, val); } } /* Reset the processor, un-stall is done later. */ if (rv2p_proc == RV2P_PROC1) { - REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET); + BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET); } else { - REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET); + BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET); } return 0; @@ -3924,14 +3924,14 @@ bnx2_set_power_state(struct bnx2 *bp, pci_power_t state) /* delay required during transition out of D3hot */ msleep(20); - val = REG_RD(bp, BNX2_EMAC_MODE); + val = BNX2_RD(bp, BNX2_EMAC_MODE); val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD; val &= ~BNX2_EMAC_MODE_MPKT; - REG_WR(bp, BNX2_EMAC_MODE, val); + BNX2_WR(bp, BNX2_EMAC_MODE, val); - val = REG_RD(bp, BNX2_RPM_CONFIG); + val = BNX2_RD(bp, BNX2_RPM_CONFIG); val &= ~BNX2_RPM_CONFIG_ACPI_ENA; - REG_WR(bp, BNX2_RPM_CONFIG, val); + BNX2_WR(bp, BNX2_RPM_CONFIG, val); break; } case PCI_D3hot: { @@ -3963,7 +3963,7 @@ bnx2_set_power_state(struct bnx2 *bp, pci_power_t state) bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); - val = REG_RD(bp, BNX2_EMAC_MODE); + val = BNX2_RD(bp, BNX2_EMAC_MODE); /* Enable port mode. */ val &= ~BNX2_EMAC_MODE_PORT; @@ -3978,32 +3978,32 @@ bnx2_set_power_state(struct bnx2 *bp, pci_power_t state) val |= BNX2_EMAC_MODE_25G_MODE; } - REG_WR(bp, BNX2_EMAC_MODE, val); + BNX2_WR(bp, BNX2_EMAC_MODE, val); /* receive all multicast */ for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { - REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), - 0xffffffff); + BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), + 0xffffffff); } - REG_WR(bp, BNX2_EMAC_RX_MODE, - BNX2_EMAC_RX_MODE_SORT_MODE); + BNX2_WR(bp, BNX2_EMAC_RX_MODE, + BNX2_EMAC_RX_MODE_SORT_MODE); val = 1 | BNX2_RPM_SORT_USER0_BC_EN | BNX2_RPM_SORT_USER0_MC_EN; - REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0); - REG_WR(bp, BNX2_RPM_SORT_USER0, val); - REG_WR(bp, BNX2_RPM_SORT_USER0, val | - BNX2_RPM_SORT_USER0_ENA); + BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0); + BNX2_WR(bp, BNX2_RPM_SORT_USER0, val); + BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | + BNX2_RPM_SORT_USER0_ENA); /* Need to enable EMAC and RPM for WOL. */ - REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, - BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE | - BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE | - BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE); + BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, + BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE | + BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE | + BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE); - val = REG_RD(bp, BNX2_RPM_CONFIG); + val = BNX2_RD(bp, BNX2_RPM_CONFIG); val &= ~BNX2_RPM_CONFIG_ACPI_ENA; - REG_WR(bp, BNX2_RPM_CONFIG, val); + BNX2_WR(bp, BNX2_RPM_CONFIG, val); wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL; } @@ -4050,9 +4050,9 @@ bnx2_acquire_nvram_lock(struct bnx2 *bp) int j; /* Request access to the flash interface. */ - REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2); + BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2); for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { - val = REG_RD(bp, BNX2_NVM_SW_ARB); + val = BNX2_RD(bp, BNX2_NVM_SW_ARB); if (val & BNX2_NVM_SW_ARB_ARB_ARB2) break; @@ -4072,10 +4072,10 @@ bnx2_release_nvram_lock(struct bnx2 *bp) u32 val; /* Relinquish nvram interface. */ - REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2); + BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2); for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { - val = REG_RD(bp, BNX2_NVM_SW_ARB); + val = BNX2_RD(bp, BNX2_NVM_SW_ARB); if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2)) break; @@ -4094,20 +4094,20 @@ bnx2_enable_nvram_write(struct bnx2 *bp) { u32 val; - val = REG_RD(bp, BNX2_MISC_CFG); - REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI); + val = BNX2_RD(bp, BNX2_MISC_CFG); + BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI); if (bp->flash_info->flags & BNX2_NV_WREN) { int j; - REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); - REG_WR(bp, BNX2_NVM_COMMAND, - BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT); + BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); + BNX2_WR(bp, BNX2_NVM_COMMAND, + BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT); for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { udelay(5); - val = REG_RD(bp, BNX2_NVM_COMMAND); + val = BNX2_RD(bp, BNX2_NVM_COMMAND); if (val & BNX2_NVM_COMMAND_DONE) break; } @@ -4123,8 +4123,8 @@ bnx2_disable_nvram_write(struct bnx2 *bp) { u32 val; - val = REG_RD(bp, BNX2_MISC_CFG); - REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN); + val = BNX2_RD(bp, BNX2_MISC_CFG); + BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN); } @@ -4133,10 +4133,10 @@ bnx2_enable_nvram_access(struct bnx2 *bp) { u32 val; - val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE); + val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE); /* Enable both bits, even on read. */ - REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, - val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN); + BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE, + val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN); } static void @@ -4144,9 +4144,9 @@ bnx2_disable_nvram_access(struct bnx2 *bp) { u32 val; - val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE); + val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE); /* Disable both bits, even after read. */ - REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, + BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE, val & ~(BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN)); } @@ -4166,13 +4166,13 @@ bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset) BNX2_NVM_COMMAND_DOIT; /* Need to clear DONE bit separately. */ - REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); + BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); /* Address of the NVRAM to read from. */ - REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); + BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); /* Issue an erase command. */ - REG_WR(bp, BNX2_NVM_COMMAND, cmd); + BNX2_WR(bp, BNX2_NVM_COMMAND, cmd); /* Wait for completion. */ for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { @@ -4180,7 +4180,7 @@ bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset) udelay(5); - val = REG_RD(bp, BNX2_NVM_COMMAND); + val = BNX2_RD(bp, BNX2_NVM_COMMAND); if (val & BNX2_NVM_COMMAND_DONE) break; } @@ -4208,13 +4208,13 @@ bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags) } /* Need to clear DONE bit separately. */ - REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); + BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); /* Address of the NVRAM to read from. */ - REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); + BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); /* Issue a read command. */ - REG_WR(bp, BNX2_NVM_COMMAND, cmd); + BNX2_WR(bp, BNX2_NVM_COMMAND, cmd); /* Wait for completion. */ for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { @@ -4222,9 +4222,9 @@ bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags) udelay(5); - val = REG_RD(bp, BNX2_NVM_COMMAND); + val = BNX2_RD(bp, BNX2_NVM_COMMAND); if (val & BNX2_NVM_COMMAND_DONE) { - __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ)); + __be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ)); memcpy(ret_val, &v, 4); break; } @@ -4254,24 +4254,24 @@ bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags) } /* Need to clear DONE bit separately. */ - REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); + BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); memcpy(&val32, val, 4); /* Write the data. */ - REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32)); + BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32)); /* Address of the NVRAM to write to. */ - REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); + BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); /* Issue the write command. */ - REG_WR(bp, BNX2_NVM_COMMAND, cmd); + BNX2_WR(bp, BNX2_NVM_COMMAND, cmd); /* Wait for completion. */ for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { udelay(5); - if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE) + if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE) break; } if (j >= NVRAM_TIMEOUT_COUNT) @@ -4293,7 +4293,7 @@ bnx2_init_nvram(struct bnx2 *bp) } /* Determine the selected interface. */ - val = REG_RD(bp, BNX2_NVM_CFG1); + val = BNX2_RD(bp, BNX2_NVM_CFG1); entry_count = ARRAY_SIZE(flash_table); @@ -4332,10 +4332,10 @@ bnx2_init_nvram(struct bnx2 *bp) bnx2_enable_nvram_access(bp); /* Reconfigure the flash interface */ - REG_WR(bp, BNX2_NVM_CFG1, flash->config1); - REG_WR(bp, BNX2_NVM_CFG2, flash->config2); - REG_WR(bp, BNX2_NVM_CFG3, flash->config3); - REG_WR(bp, BNX2_NVM_WRITE1, flash->write1); + BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1); + BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2); + BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3); + BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1); /* Disable access to flash interface */ bnx2_disable_nvram_access(bp); @@ -4696,10 +4696,10 @@ bnx2_init_fw_cap(struct bnx2 *bp) static void bnx2_setup_msix_tbl(struct bnx2 *bp) { - REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN); + BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN); - REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR); - REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR); + BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR); + BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR); } static int @@ -4713,22 +4713,22 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) * issuing a reset. */ if ((CHIP_NUM(bp) == CHIP_NUM_5706) || (CHIP_NUM(bp) == CHIP_NUM_5708)) { - REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS, - BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | - BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | - BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | - BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); - val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS); + BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS, + BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | + BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | + BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | + BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); + val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS); udelay(5); } else { /* 5709 */ - val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL); + val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE; - REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); - val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL); + BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); + val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); for (i = 0; i < 100; i++) { msleep(1); - val = REG_RD(bp, BNX2_PCICFG_DEVICE_CONTROL); + val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL); if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND)) break; } @@ -4744,17 +4744,17 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) /* Do a dummy read to force the chip to complete all current transaction * before we issue a reset. */ - val = REG_RD(bp, BNX2_MISC_ID); + val = BNX2_RD(bp, BNX2_MISC_ID); if (CHIP_NUM(bp) == CHIP_NUM_5709) { - REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET); - REG_RD(bp, BNX2_MISC_COMMAND); + BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET); + BNX2_RD(bp, BNX2_MISC_COMMAND); udelay(5); val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; - REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); + BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); } else { val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | @@ -4762,7 +4762,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; /* Chip reset. */ - REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); + BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); /* Reading back any register after chip reset will hang the * bus on 5706 A0 and A1. The msleep below provides plenty @@ -4774,7 +4774,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) /* Reset takes approximate 30 usec */ for (i = 0; i < 10; i++) { - val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG); + val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG); if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) break; @@ -4789,7 +4789,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) } /* Make sure byte swapping is properly configured. */ - val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0); + val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0); if (val != 0x01020304) { pr_err("Chip not in correct endian mode\n"); return -ENODEV; @@ -4811,7 +4811,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) if (CHIP_ID(bp) == CHIP_ID_5706_A0) { /* Adjust the voltage regular to two steps lower. The default * of this register is 0x0000000e. */ - REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa); + BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa); /* Remove bad rbuf memory from the free pool. */ rc = bnx2_alloc_bad_rbuf(bp); @@ -4820,7 +4820,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) if (bp->flags & BNX2_FLAG_USING_MSIX) { bnx2_setup_msix_tbl(bp); /* Prevent MSIX table reads and write from timing out */ - REG_WR(bp, BNX2_MISC_ECO_HW_CTL, + BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL, BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN); } @@ -4834,7 +4834,7 @@ bnx2_init_chip(struct bnx2 *bp) int rc, i; /* Make sure the interrupt is not active. */ - REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT); + BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT); val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP | BNX2_DMA_CONFIG_DATA_WORD_SWAP | @@ -4854,12 +4854,12 @@ bnx2_init_chip(struct bnx2 *bp) (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX)) val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA; - REG_WR(bp, BNX2_DMA_CONFIG, val); + BNX2_WR(bp, BNX2_DMA_CONFIG, val); if (CHIP_ID(bp) == CHIP_ID_5706_A0) { - val = REG_RD(bp, BNX2_TDMA_CONFIG); + val = BNX2_RD(bp, BNX2_TDMA_CONFIG); val |= BNX2_TDMA_CONFIG_ONE_DMA; - REG_WR(bp, BNX2_TDMA_CONFIG, val); + BNX2_WR(bp, BNX2_TDMA_CONFIG, val); } if (bp->flags & BNX2_FLAG_PCIX) { @@ -4871,10 +4871,10 @@ bnx2_init_chip(struct bnx2 *bp) val16 & ~PCI_X_CMD_ERO); } - REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, - BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | - BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | - BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); + BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, + BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | + BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | + BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); /* Initialize context mapping and zero out the quick contexts. The * context block must have already been enabled. */ @@ -4892,7 +4892,7 @@ bnx2_init_chip(struct bnx2 *bp) bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0); - val = REG_RD(bp, BNX2_MQ_CONFIG); + val = BNX2_RD(bp, BNX2_MQ_CONFIG); val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; if (CHIP_NUM(bp) == CHIP_NUM_5709) { @@ -4901,20 +4901,20 @@ bnx2_init_chip(struct bnx2 *bp) val |= BNX2_MQ_CONFIG_HALT_DIS; } - REG_WR(bp, BNX2_MQ_CONFIG, val); + BNX2_WR(bp, BNX2_MQ_CONFIG, val); val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); - REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val); - REG_WR(bp, BNX2_MQ_KNL_WIND_END, val); + BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val); + BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val); val = (BCM_PAGE_BITS - 8) << 24; - REG_WR(bp, BNX2_RV2P_CONFIG, val); + BNX2_WR(bp, BNX2_RV2P_CONFIG, val); /* Configure page size. */ - val = REG_RD(bp, BNX2_TBDR_CONFIG); + val = BNX2_RD(bp, BNX2_TBDR_CONFIG); val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE; val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; - REG_WR(bp, BNX2_TBDR_CONFIG, val); + BNX2_WR(bp, BNX2_TBDR_CONFIG, val); val = bp->mac_addr[0] + (bp->mac_addr[1] << 8) + @@ -4922,14 +4922,14 @@ bnx2_init_chip(struct bnx2 *bp) bp->mac_addr[3] + (bp->mac_addr[4] << 8) + (bp->mac_addr[5] << 16); - REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val); + BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val); /* Program the MTU. Also include 4 bytes for CRC32. */ mtu = bp->dev->mtu; val = mtu + ETH_HLEN + ETH_FCS_LEN; if (val > (MAX_ETHERNET_PACKET_SIZE + 4)) val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA; - REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val); + BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val); if (mtu < 1500) mtu = 1500; @@ -4947,41 +4947,41 @@ bnx2_init_chip(struct bnx2 *bp) bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE; /* Set up how to generate a link change interrupt. */ - REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); + BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); - REG_WR(bp, BNX2_HC_STATUS_ADDR_L, - (u64) bp->status_blk_mapping & 0xffffffff); - REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32); + BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L, + (u64) bp->status_blk_mapping & 0xffffffff); + BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32); - REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L, - (u64) bp->stats_blk_mapping & 0xffffffff); - REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H, - (u64) bp->stats_blk_mapping >> 32); + BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L, + (u64) bp->stats_blk_mapping & 0xffffffff); + BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H, + (u64) bp->stats_blk_mapping >> 32); - REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, - (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip); + BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, + (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip); - REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP, - (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip); + BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP, + (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip); - REG_WR(bp, BNX2_HC_COMP_PROD_TRIP, - (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip); + BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP, + (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip); - REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks); + BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks); - REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks); + BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks); - REG_WR(bp, BNX2_HC_COM_TICKS, - (bp->com_ticks_int << 16) | bp->com_ticks); + BNX2_WR(bp, BNX2_HC_COM_TICKS, + (bp->com_ticks_int << 16) | bp->com_ticks); - REG_WR(bp, BNX2_HC_CMD_TICKS, - (bp->cmd_ticks_int << 16) | bp->cmd_ticks); + BNX2_WR(bp, BNX2_HC_CMD_TICKS, + (bp->cmd_ticks_int << 16) | bp->cmd_ticks); if (bp->flags & BNX2_FLAG_BROKEN_STATS) - REG_WR(bp, BNX2_HC_STATS_TICKS, 0); + BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0); else - REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks); - REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ + BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks); + BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ if (CHIP_ID(bp) == CHIP_ID_5706_A1) val = BNX2_HC_CONFIG_COLLECT_STATS; @@ -4991,8 +4991,8 @@ bnx2_init_chip(struct bnx2 *bp) } if (bp->flags & BNX2_FLAG_USING_MSIX) { - REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR, - BNX2_HC_MSIX_BIT_VECTOR_VAL); + BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR, + BNX2_HC_MSIX_BIT_VECTOR_VAL); val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B; } @@ -5000,7 +5000,7 @@ bnx2_init_chip(struct bnx2 *bp) if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI) val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM; - REG_WR(bp, BNX2_HC_CONFIG, val); + BNX2_WR(bp, BNX2_HC_CONFIG, val); if (bp->rx_ticks < 25) bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1); @@ -5011,48 +5011,48 @@ bnx2_init_chip(struct bnx2 *bp) u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) + BNX2_HC_SB_CONFIG_1; - REG_WR(bp, base, + BNX2_WR(bp, base, BNX2_HC_SB_CONFIG_1_TX_TMR_MODE | BNX2_HC_SB_CONFIG_1_RX_TMR_MODE | BNX2_HC_SB_CONFIG_1_ONE_SHOT); - REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF, + BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF, (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip); - REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF, + BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF, (bp->tx_ticks_int << 16) | bp->tx_ticks); - REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF, - (bp->rx_quick_cons_trip_int << 16) | + BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF, + (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip); - REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF, + BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF, (bp->rx_ticks_int << 16) | bp->rx_ticks); } /* Clear internal stats counters. */ - REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW); + BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW); - REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS); + BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS); /* Initialize the receive filter. */ bnx2_set_rx_mode(bp->dev); if (CHIP_NUM(bp) == CHIP_NUM_5709) { - val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL); + val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE; - REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); + BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); } rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET, 1, 0); - REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT); - REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS); + BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT); + BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS); udelay(20); - bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND); + bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND); return rc; } @@ -5188,8 +5188,8 @@ bnx2_init_rx_ring(struct bnx2 *bp, int ring_num) bnx2_init_rx_context(bp, cid); if (CHIP_NUM(bp) == CHIP_NUM_5709) { - val = REG_RD(bp, BNX2_MQ_MAP_L2_5); - REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM); + val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5); + BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM); } bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0); @@ -5209,7 +5209,7 @@ bnx2_init_rx_ring(struct bnx2 *bp, int ring_num) bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val); if (CHIP_NUM(bp) == CHIP_NUM_5709) - REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT); + BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT); } val = (u64) rxr->rx_desc_mapping[0] >> 32; @@ -5246,10 +5246,10 @@ bnx2_init_rx_ring(struct bnx2 *bp, int ring_num) rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ; rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX; - REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); - REG_WR16(bp, rxr->rx_bidx_addr, prod); + BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod); + BNX2_WR16(bp, rxr->rx_bidx_addr, prod); - REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); + BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq); } static void @@ -5260,15 +5260,15 @@ bnx2_init_all_rings(struct bnx2 *bp) bnx2_clear_ring_states(bp); - REG_WR(bp, BNX2_TSCH_TSS_CFG, 0); + BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0); for (i = 0; i < bp->num_tx_rings; i++) bnx2_init_tx_ring(bp, i); if (bp->num_tx_rings > 1) - REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) | - (TX_TSS_CID << 7)); + BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) | + (TX_TSS_CID << 7)); - REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0); + BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0); bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0); for (i = 0; i < bp->num_rx_rings; i++) @@ -5282,8 +5282,8 @@ bnx2_init_all_rings(struct bnx2 *bp) tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift; if ((i % 8) == 7) { - REG_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32); - REG_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) | + BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32); + BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) | BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK | BNX2_RLUP_RSS_COMMAND_WRITE | BNX2_RLUP_RSS_COMMAND_HASH_MASK); @@ -5294,7 +5294,7 @@ bnx2_init_all_rings(struct bnx2 *bp) val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI | BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI; - REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val); + BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val); } } @@ -5784,10 +5784,10 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) return -EIO; } - REG_WR(bp, BNX2_HC_COMMAND, - bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); + BNX2_WR(bp, BNX2_HC_COMMAND, + bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); - REG_RD(bp, BNX2_HC_COMMAND); + BNX2_RD(bp, BNX2_HC_COMMAND); udelay(5); rx_start_idx = bnx2_get_hw_rx_cons(bnapi); @@ -5805,15 +5805,15 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) txr->tx_prod = NEXT_TX_BD(txr->tx_prod); txr->tx_prod_bseq += pkt_size; - REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod); - REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); + BNX2_WR16(bp, txr->tx_bidx_addr, txr->tx_prod); + BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); udelay(100); - REG_WR(bp, BNX2_HC_COMMAND, - bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); + BNX2_WR(bp, BNX2_HC_COMMAND, + bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT); - REG_RD(bp, BNX2_HC_COMMAND); + BNX2_RD(bp, BNX2_HC_COMMAND); udelay(5); @@ -5962,14 +5962,14 @@ bnx2_test_intr(struct bnx2 *bp) if (!netif_running(bp->dev)) return -ENODEV; - status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff; + status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff; /* This register is not touched during run-time. */ - REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); - REG_RD(bp, BNX2_HC_COMMAND); + BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); + BNX2_RD(bp, BNX2_HC_COMMAND); for (i = 0; i < 10; i++) { - if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) != + if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) != status_idx) { break; @@ -6132,8 +6132,8 @@ bnx2_timer(unsigned long data) /* workaround occasional corrupted counters */ if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks) - REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | - BNX2_HC_COMMAND_STATS_NOW); + BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | + BNX2_HC_COMMAND_STATS_NOW); if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { if (CHIP_NUM(bp) == CHIP_NUM_5706) @@ -6205,13 +6205,13 @@ bnx2_enable_msix(struct bnx2 *bp, int msix_vecs) const int len = sizeof(bp->irq_tbl[0].name); bnx2_setup_msix_tbl(bp); - REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1); - REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE); - REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE); + BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1); + BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE); + BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE); /* Need to flush the previous three writes to ensure MSI-X * is setup properly */ - REG_RD(bp, BNX2_PCI_MSIX_CONTROL); + BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL); for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { msix_ent[i].entry = i; @@ -6464,22 +6464,22 @@ bnx2_dump_ftq(struct bnx2 *bp) netdev_err(dev, "<--- end FTQ dump --->\n"); netdev_err(dev, "<--- start TBDC dump --->\n"); netdev_err(dev, "TBDC free cnt: %ld\n", - REG_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT); + BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT); netdev_err(dev, "LINE CID BIDX CMD VALIDS\n"); for (i = 0; i < 0x20; i++) { int j = 0; - REG_WR(bp, BNX2_TBDC_BD_ADDR, i); - REG_WR(bp, BNX2_TBDC_CAM_OPCODE, - BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_READ); - REG_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB); - while ((REG_RD(bp, BNX2_TBDC_COMMAND) & + BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i); + BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE, + BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_READ); + BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB); + while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) & BNX2_TBDC_COMMAND_CMD_REG_ARB) && j < 100) j++; - cid = REG_RD(bp, BNX2_TBDC_CID); - bdidx = REG_RD(bp, BNX2_TBDC_BIDX); - valid = REG_RD(bp, BNX2_TBDC_CAM_OPCODE); + cid = BNX2_RD(bp, BNX2_TBDC_CID); + bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX); + valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE); netdev_err(dev, "%02x %06x %04lx %02x [%x]\n", i, cid, bdidx & BNX2_TBDC_BDIDX_BDIDX, bdidx >> 24, (valid >> 8) & 0x0ff); @@ -6500,15 +6500,15 @@ bnx2_dump_state(struct bnx2 *bp) pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2); netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2); netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n", - REG_RD(bp, BNX2_EMAC_TX_STATUS), - REG_RD(bp, BNX2_EMAC_RX_STATUS)); + BNX2_RD(bp, BNX2_EMAC_TX_STATUS), + BNX2_RD(bp, BNX2_EMAC_RX_STATUS)); netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n", - REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL)); + BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL)); netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n", - REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS)); + BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS)); if (bp->flags & BNX2_FLAG_USING_MSIX) netdev_err(dev, "DEBUG: PBA[%08x]\n", - REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE)); + BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE)); } static void @@ -6655,8 +6655,8 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) prod = NEXT_TX_BD(prod); txr->tx_prod_bseq += skb->len; - REG_WR16(bp, txr->tx_bidx_addr, prod); - REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); + BNX2_WR16(bp, txr->tx_bidx_addr, prod); + BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq); mmiowb(); @@ -7030,7 +7030,7 @@ bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p) offset = reg_boundaries[0]; p += offset; while (offset < BNX2_REGDUMP_LEN) { - *p++ = REG_RD(bp, offset); + *p++ = BNX2_RD(bp, offset); offset += 4; if (offset == reg_boundaries[i + 1]) { offset = reg_boundaries[i + 2]; @@ -7655,26 +7655,26 @@ bnx2_set_phys_id(struct net_device *dev, enum ethtool_phys_id_state state) case ETHTOOL_ID_ACTIVE: bnx2_set_power_state(bp, PCI_D0); - bp->leds_save = REG_RD(bp, BNX2_MISC_CFG); - REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC); + bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG); + BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC); return 1; /* cycle on/off once per second */ case ETHTOOL_ID_ON: - REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE | - BNX2_EMAC_LED_1000MB_OVERRIDE | - BNX2_EMAC_LED_100MB_OVERRIDE | - BNX2_EMAC_LED_10MB_OVERRIDE | - BNX2_EMAC_LED_TRAFFIC_OVERRIDE | - BNX2_EMAC_LED_TRAFFIC); + BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE | + BNX2_EMAC_LED_1000MB_OVERRIDE | + BNX2_EMAC_LED_100MB_OVERRIDE | + BNX2_EMAC_LED_10MB_OVERRIDE | + BNX2_EMAC_LED_TRAFFIC_OVERRIDE | + BNX2_EMAC_LED_TRAFFIC); break; case ETHTOOL_ID_OFF: - REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE); + BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE); break; case ETHTOOL_ID_INACTIVE: - REG_WR(bp, BNX2_EMAC_LED, 0); - REG_WR(bp, BNX2_MISC_CFG, bp->leds_save); + BNX2_WR(bp, BNX2_EMAC_LED, 0); + BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save); if (!netif_running(dev)) bnx2_set_power_state(bp, PCI_D3hot); @@ -7899,7 +7899,7 @@ poll_bnx2(struct net_device *dev) static void bnx2_get_5709_media(struct bnx2 *bp) { - u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL); + u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL); u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID; u32 strap; @@ -7939,13 +7939,13 @@ bnx2_get_pci_speed(struct bnx2 *bp) { u32 reg; - reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS); + reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS); if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) { u32 clkreg; bp->flags |= BNX2_FLAG_PCIX; - clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS); + clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS); clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; switch (clkreg) { @@ -8131,11 +8131,11 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) * Rely on CPU to do target byte swapping on big endian systems * The chip's target access swapping will not swap all accesses */ - REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, - BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | - BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); + BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, + BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | + BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); - bp->chip_id = REG_RD(bp, BNX2_MISC_ID); + bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID); if (CHIP_NUM(bp) == CHIP_NUM_5709) { if (!pci_is_pcie(pdev)) { @@ -8198,9 +8198,9 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) /* 5706A0 may falsely detect SERR and PERR. */ if (CHIP_ID(bp) == CHIP_ID_5706_A0) { - reg = REG_RD(bp, PCI_COMMAND); + reg = BNX2_RD(bp, PCI_COMMAND); reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); - REG_WR(bp, PCI_COMMAND, reg); + BNX2_WR(bp, PCI_COMMAND, reg); } else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) && !(bp->flags & BNX2_FLAG_PCIX)) { @@ -8358,7 +8358,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || (CHIP_ID(bp) == CHIP_ID_5708_B0) || (CHIP_ID(bp) == CHIP_ID_5708_B1) || - !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) { + !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) { bp->flags |= BNX2_FLAG_NO_WOL; bp->wol = 0; } diff --git a/drivers/net/ethernet/broadcom/bnx2.h b/drivers/net/ethernet/broadcom/bnx2.h index af6451dec295..5f136745ffdd 100644 --- a/drivers/net/ethernet/broadcom/bnx2.h +++ b/drivers/net/ethernet/broadcom/bnx2.h @@ -6991,13 +6991,13 @@ struct bnx2 { const struct firmware *rv2p_firmware; }; -#define REG_RD(bp, offset) \ +#define BNX2_RD(bp, offset) \ readl(bp->regview + offset) -#define REG_WR(bp, offset, val) \ +#define BNX2_WR(bp, offset, val) \ writel(val, bp->regview + offset) -#define REG_WR16(bp, offset, val) \ +#define BNX2_WR16(bp, offset, val) \ writew(val, bp->regview + offset) struct cpu_reg { -- cgit v1.2.3 From 2bc4078e92b28375a762d7236c1c9619eecab315 Mon Sep 17 00:00:00 2001 From: Michael Chan Date: Thu, 6 Dec 2012 10:33:09 +0000 Subject: bnx2: Add BNX2 prefix to descriptor structures and macros for namespace consistency. Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/ethernet/broadcom/bnx2.c | 190 ++++++++++++++++++----------------- drivers/net/ethernet/broadcom/bnx2.h | 79 ++++++++------- drivers/net/ethernet/broadcom/cnic.c | 70 ++++++------- drivers/net/ethernet/broadcom/cnic.h | 14 +-- 4 files changed, 181 insertions(+), 172 deletions(-) (limited to 'drivers/net/ethernet/broadcom/bnx2.c') diff --git a/drivers/net/ethernet/broadcom/bnx2.c b/drivers/net/ethernet/broadcom/bnx2.c index 41fa6af2fd86..98cb76b9482c 100644 --- a/drivers/net/ethernet/broadcom/bnx2.c +++ b/drivers/net/ethernet/broadcom/bnx2.c @@ -260,10 +260,10 @@ static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr) * needs to be skipped. */ diff = txr->tx_prod - txr->tx_cons; - if (unlikely(diff >= TX_DESC_CNT)) { + if (unlikely(diff >= BNX2_TX_DESC_CNT)) { diff &= 0xffff; - if (diff == TX_DESC_CNT) - diff = MAX_TX_DESC_CNT; + if (diff == BNX2_TX_DESC_CNT) + diff = BNX2_MAX_TX_DESC_CNT; } return bp->tx_ring_size - diff; } @@ -824,7 +824,7 @@ bnx2_free_mem(struct bnx2 *bp) for (i = 0; i < bp->ctx_pages; i++) { if (bp->ctx_blk[i]) { - dma_free_coherent(&bp->pdev->dev, BCM_PAGE_SIZE, + dma_free_coherent(&bp->pdev->dev, BNX2_PAGE_SIZE, bp->ctx_blk[i], bp->ctx_blk_mapping[i]); bp->ctx_blk[i] = NULL; @@ -888,12 +888,12 @@ bnx2_alloc_mem(struct bnx2 *bp) bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size; if (CHIP_NUM(bp) == CHIP_NUM_5709) { - bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE; + bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE; if (bp->ctx_pages == 0) bp->ctx_pages = 1; for (i = 0; i < bp->ctx_pages; i++) { bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev, - BCM_PAGE_SIZE, + BNX2_PAGE_SIZE, &bp->ctx_blk_mapping[i], GFP_KERNEL); if (bp->ctx_blk[i] == NULL) @@ -2538,7 +2538,7 @@ bnx2_init_5709_context(struct bnx2 *bp) u32 val; val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12); - val |= (BCM_PAGE_BITS - 8) << 16; + val |= (BNX2_PAGE_BITS - 8) << 16; BNX2_WR(bp, BNX2_CTX_COMMAND, val); for (i = 0; i < 10; i++) { val = BNX2_RD(bp, BNX2_CTX_COMMAND); @@ -2553,7 +2553,7 @@ bnx2_init_5709_context(struct bnx2 *bp) int j; if (bp->ctx_blk[i]) - memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE); + memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE); else return -ENOMEM; @@ -2690,9 +2690,9 @@ static inline int bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp) { dma_addr_t mapping; - struct sw_pg *rx_pg = &rxr->rx_pg_ring[index]; - struct rx_bd *rxbd = - &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)]; + struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index]; + struct bnx2_rx_bd *rxbd = + &rxr->rx_pg_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)]; struct page *page = alloc_page(gfp); if (!page) @@ -2714,7 +2714,7 @@ bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gf static void bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index) { - struct sw_pg *rx_pg = &rxr->rx_pg_ring[index]; + struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index]; struct page *page = rx_pg->page; if (!page) @@ -2731,9 +2731,10 @@ static inline int bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp) { u8 *data; - struct sw_bd *rx_buf = &rxr->rx_buf_ring[index]; + struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[index]; dma_addr_t mapping; - struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)]; + struct bnx2_rx_bd *rxbd = + &rxr->rx_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)]; data = kmalloc(bp->rx_buf_size, gfp); if (!data) @@ -2802,7 +2803,7 @@ bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi) barrier(); cons = *bnapi->hw_tx_cons_ptr; barrier(); - if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT)) + if (unlikely((cons & BNX2_MAX_TX_DESC_CNT) == BNX2_MAX_TX_DESC_CNT)) cons++; return cons; } @@ -2823,11 +2824,11 @@ bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) sw_cons = txr->tx_cons; while (sw_cons != hw_cons) { - struct sw_tx_bd *tx_buf; + struct bnx2_sw_tx_bd *tx_buf; struct sk_buff *skb; int i, last; - sw_ring_cons = TX_RING_IDX(sw_cons); + sw_ring_cons = BNX2_TX_RING_IDX(sw_cons); tx_buf = &txr->tx_buf_ring[sw_ring_cons]; skb = tx_buf->skb; @@ -2841,7 +2842,7 @@ bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) last_idx = sw_cons + tx_buf->nr_frags + 1; last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1; - if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) { + if (unlikely(last_ring_idx >= BNX2_MAX_TX_DESC_CNT)) { last_idx++; } if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) { @@ -2856,17 +2857,18 @@ bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) last = tx_buf->nr_frags; for (i = 0; i < last; i++) { - sw_cons = NEXT_TX_BD(sw_cons); + struct bnx2_sw_tx_bd *tx_buf; + sw_cons = BNX2_NEXT_TX_BD(sw_cons); + + tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(sw_cons)]; dma_unmap_page(&bp->pdev->dev, - dma_unmap_addr( - &txr->tx_buf_ring[TX_RING_IDX(sw_cons)], - mapping), + dma_unmap_addr(tx_buf, mapping), skb_frag_size(&skb_shinfo(skb)->frags[i]), PCI_DMA_TODEVICE); } - sw_cons = NEXT_TX_BD(sw_cons); + sw_cons = BNX2_NEXT_TX_BD(sw_cons); tx_bytes += skb->len; dev_kfree_skb(skb); @@ -2905,8 +2907,8 @@ static void bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb, int count) { - struct sw_pg *cons_rx_pg, *prod_rx_pg; - struct rx_bd *cons_bd, *prod_bd; + struct bnx2_sw_pg *cons_rx_pg, *prod_rx_pg; + struct bnx2_rx_bd *cons_bd, *prod_bd; int i; u16 hw_prod, prod; u16 cons = rxr->rx_pg_cons; @@ -2933,12 +2935,14 @@ bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, hw_prod = rxr->rx_pg_prod; for (i = 0; i < count; i++) { - prod = RX_PG_RING_IDX(hw_prod); + prod = BNX2_RX_PG_RING_IDX(hw_prod); prod_rx_pg = &rxr->rx_pg_ring[prod]; cons_rx_pg = &rxr->rx_pg_ring[cons]; - cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)]; - prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; + cons_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(cons)] + [BNX2_RX_IDX(cons)]; + prod_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(prod)] + [BNX2_RX_IDX(prod)]; if (prod != cons) { prod_rx_pg->page = cons_rx_pg->page; @@ -2950,8 +2954,8 @@ bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; } - cons = RX_PG_RING_IDX(NEXT_RX_BD(cons)); - hw_prod = NEXT_RX_BD(hw_prod); + cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(cons)); + hw_prod = BNX2_NEXT_RX_BD(hw_prod); } rxr->rx_pg_prod = hw_prod; rxr->rx_pg_cons = cons; @@ -2961,8 +2965,8 @@ static inline void bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data, u16 cons, u16 prod) { - struct sw_bd *cons_rx_buf, *prod_rx_buf; - struct rx_bd *cons_bd, *prod_bd; + struct bnx2_sw_bd *cons_rx_buf, *prod_rx_buf; + struct bnx2_rx_bd *cons_bd, *prod_bd; cons_rx_buf = &rxr->rx_buf_ring[cons]; prod_rx_buf = &rxr->rx_buf_ring[prod]; @@ -2981,8 +2985,8 @@ bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, dma_unmap_addr_set(prod_rx_buf, mapping, dma_unmap_addr(cons_rx_buf, mapping)); - cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; - prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; + cons_bd = &rxr->rx_desc_ring[BNX2_RX_RING(cons)][BNX2_RX_IDX(cons)]; + prod_bd = &rxr->rx_desc_ring[BNX2_RX_RING(prod)][BNX2_RX_IDX(prod)]; prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi; prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo; } @@ -3022,7 +3026,7 @@ error: return skb; } else { unsigned int i, frag_len, frag_size, pages; - struct sw_pg *rx_pg; + struct bnx2_sw_pg *rx_pg; u16 pg_cons = rxr->rx_pg_cons; u16 pg_prod = rxr->rx_pg_prod; @@ -3065,7 +3069,7 @@ error: rx_pg->page = NULL; err = bnx2_alloc_rx_page(bp, rxr, - RX_PG_RING_IDX(pg_prod), + BNX2_RX_PG_RING_IDX(pg_prod), GFP_ATOMIC); if (unlikely(err)) { rxr->rx_pg_cons = pg_cons; @@ -3083,8 +3087,8 @@ error: skb->truesize += PAGE_SIZE; skb->len += frag_len; - pg_prod = NEXT_RX_BD(pg_prod); - pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons)); + pg_prod = BNX2_NEXT_RX_BD(pg_prod); + pg_cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(pg_cons)); } rxr->rx_pg_prod = pg_prod; rxr->rx_pg_cons = pg_cons; @@ -3101,7 +3105,7 @@ bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi) barrier(); cons = *bnapi->hw_rx_cons_ptr; barrier(); - if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)) + if (unlikely((cons & BNX2_MAX_RX_DESC_CNT) == BNX2_MAX_RX_DESC_CNT)) cons++; return cons; } @@ -3125,13 +3129,14 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) while (sw_cons != hw_cons) { unsigned int len, hdr_len; u32 status; - struct sw_bd *rx_buf, *next_rx_buf; + struct bnx2_sw_bd *rx_buf, *next_rx_buf; struct sk_buff *skb; dma_addr_t dma_addr; u8 *data; + u16 next_ring_idx; - sw_ring_cons = RX_RING_IDX(sw_cons); - sw_ring_prod = RX_RING_IDX(sw_prod); + sw_ring_cons = BNX2_RX_RING_IDX(sw_cons); + sw_ring_prod = BNX2_RX_RING_IDX(sw_prod); rx_buf = &rxr->rx_buf_ring[sw_ring_cons]; data = rx_buf->data; @@ -3146,8 +3151,8 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE); - next_rx_buf = - &rxr->rx_buf_ring[RX_RING_IDX(NEXT_RX_BD(sw_cons))]; + next_ring_idx = BNX2_RX_RING_IDX(BNX2_NEXT_RX_BD(sw_cons)); + next_rx_buf = &rxr->rx_buf_ring[next_ring_idx]; prefetch(get_l2_fhdr(next_rx_buf->data)); len = rx_hdr->l2_fhdr_pkt_len; @@ -3239,8 +3244,8 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) rx_pkt++; next_rx: - sw_cons = NEXT_RX_BD(sw_cons); - sw_prod = NEXT_RX_BD(sw_prod); + sw_cons = BNX2_NEXT_RX_BD(sw_cons); + sw_prod = BNX2_NEXT_RX_BD(sw_prod); if ((rx_pkt == budget)) break; @@ -4907,13 +4912,13 @@ bnx2_init_chip(struct bnx2 *bp) BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val); BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val); - val = (BCM_PAGE_BITS - 8) << 24; + val = (BNX2_PAGE_BITS - 8) << 24; BNX2_WR(bp, BNX2_RV2P_CONFIG, val); /* Configure page size. */ val = BNX2_RD(bp, BNX2_TBDR_CONFIG); val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE; - val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; + val |= (BNX2_PAGE_BITS - 8) << 24 | 0x40; BNX2_WR(bp, BNX2_TBDR_CONFIG, val); val = bp->mac_addr[0] + @@ -5113,7 +5118,7 @@ bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr) static void bnx2_init_tx_ring(struct bnx2 *bp, int ring_num) { - struct tx_bd *txbd; + struct bnx2_tx_bd *txbd; u32 cid = TX_CID; struct bnx2_napi *bnapi; struct bnx2_tx_ring_info *txr; @@ -5128,7 +5133,7 @@ bnx2_init_tx_ring(struct bnx2 *bp, int ring_num) bp->tx_wake_thresh = bp->tx_ring_size / 2; - txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT]; + txbd = &txr->tx_desc_ring[BNX2_MAX_TX_DESC_CNT]; txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32; txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff; @@ -5143,17 +5148,17 @@ bnx2_init_tx_ring(struct bnx2 *bp, int ring_num) } static void -bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size, - int num_rings) +bnx2_init_rxbd_rings(struct bnx2_rx_bd *rx_ring[], dma_addr_t dma[], + u32 buf_size, int num_rings) { int i; - struct rx_bd *rxbd; + struct bnx2_rx_bd *rxbd; for (i = 0; i < num_rings; i++) { int j; rxbd = &rx_ring[i][0]; - for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) { + for (j = 0; j < BNX2_MAX_RX_DESC_CNT; j++, rxbd++) { rxbd->rx_bd_len = buf_size; rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END; } @@ -5225,8 +5230,8 @@ bnx2_init_rx_ring(struct bnx2 *bp, int ring_num) ring_num, i, bp->rx_pg_ring_size); break; } - prod = NEXT_RX_BD(prod); - ring_prod = RX_PG_RING_IDX(prod); + prod = BNX2_NEXT_RX_BD(prod); + ring_prod = BNX2_RX_PG_RING_IDX(prod); } rxr->rx_pg_prod = prod; @@ -5237,8 +5242,8 @@ bnx2_init_rx_ring(struct bnx2 *bp, int ring_num) ring_num, i, bp->rx_ring_size); break; } - prod = NEXT_RX_BD(prod); - ring_prod = RX_RING_IDX(prod); + prod = BNX2_NEXT_RX_BD(prod); + ring_prod = BNX2_RX_RING_IDX(prod); } rxr->rx_prod = prod; @@ -5303,8 +5308,8 @@ static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size) { u32 max, num_rings = 1; - while (ring_size > MAX_RX_DESC_CNT) { - ring_size -= MAX_RX_DESC_CNT; + while (ring_size > BNX2_MAX_RX_DESC_CNT) { + ring_size -= BNX2_MAX_RX_DESC_CNT; num_rings++; } /* round to next power of 2 */ @@ -5337,13 +5342,14 @@ bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size) int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; jumbo_size = size * pages; - if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT) - jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT; + if (jumbo_size > BNX2_MAX_TOTAL_RX_PG_DESC_CNT) + jumbo_size = BNX2_MAX_TOTAL_RX_PG_DESC_CNT; bp->rx_pg_ring_size = jumbo_size; bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size, - MAX_RX_PG_RINGS); - bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1; + BNX2_MAX_RX_PG_RINGS); + bp->rx_max_pg_ring_idx = + (bp->rx_max_pg_ring * BNX2_RX_DESC_CNT) - 1; rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET; bp->rx_copy_thresh = 0; } @@ -5354,8 +5360,8 @@ bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size) NET_SKB_PAD + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET; bp->rx_ring_size = size; - bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS); - bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1; + bp->rx_max_ring = bnx2_find_max_ring(size, BNX2_MAX_RX_RINGS); + bp->rx_max_ring_idx = (bp->rx_max_ring * BNX2_RX_DESC_CNT) - 1; } static void @@ -5371,13 +5377,13 @@ bnx2_free_tx_skbs(struct bnx2 *bp) if (txr->tx_buf_ring == NULL) continue; - for (j = 0; j < TX_DESC_CNT; ) { - struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; + for (j = 0; j < BNX2_TX_DESC_CNT; ) { + struct bnx2_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; struct sk_buff *skb = tx_buf->skb; int k, last; if (skb == NULL) { - j = NEXT_TX_BD(j); + j = BNX2_NEXT_TX_BD(j); continue; } @@ -5389,9 +5395,9 @@ bnx2_free_tx_skbs(struct bnx2 *bp) tx_buf->skb = NULL; last = tx_buf->nr_frags; - j = NEXT_TX_BD(j); - for (k = 0; k < last; k++, j = NEXT_TX_BD(j)) { - tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)]; + j = BNX2_NEXT_TX_BD(j); + for (k = 0; k < last; k++, j = BNX2_NEXT_TX_BD(j)) { + tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(j)]; dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), skb_frag_size(&skb_shinfo(skb)->frags[k]), @@ -5417,7 +5423,7 @@ bnx2_free_rx_skbs(struct bnx2 *bp) return; for (j = 0; j < bp->rx_max_ring_idx; j++) { - struct sw_bd *rx_buf = &rxr->rx_buf_ring[j]; + struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[j]; u8 *data = rx_buf->data; if (data == NULL) @@ -5741,8 +5747,8 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) unsigned char *packet; u16 rx_start_idx, rx_idx; dma_addr_t map; - struct tx_bd *txbd; - struct sw_bd *rx_buf; + struct bnx2_tx_bd *txbd; + struct bnx2_sw_bd *rx_buf; struct l2_fhdr *rx_hdr; int ret = -ENODEV; struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi; @@ -5794,7 +5800,7 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) num_pkts = 0; - txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)]; + txbd = &txr->tx_desc_ring[BNX2_TX_RING_IDX(txr->tx_prod)]; txbd->tx_bd_haddr_hi = (u64) map >> 32; txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff; @@ -5802,7 +5808,7 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END; num_pkts++; - txr->tx_prod = NEXT_TX_BD(txr->tx_prod); + txr->tx_prod = BNX2_NEXT_TX_BD(txr->tx_prod); txr->tx_prod_bseq += pkt_size; BNX2_WR16(bp, txr->tx_bidx_addr, txr->tx_prod); @@ -6533,8 +6539,8 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) { struct bnx2 *bp = netdev_priv(dev); dma_addr_t mapping; - struct tx_bd *txbd; - struct sw_tx_bd *tx_buf; + struct bnx2_tx_bd *txbd; + struct bnx2_sw_tx_bd *tx_buf; u32 len, vlan_tag_flags, last_frag, mss; u16 prod, ring_prod; int i; @@ -6557,7 +6563,7 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) } len = skb_headlen(skb); prod = txr->tx_prod; - ring_prod = TX_RING_IDX(prod); + ring_prod = BNX2_TX_RING_IDX(prod); vlan_tag_flags = 0; if (skb->ip_summed == CHECKSUM_PARTIAL) { @@ -6627,8 +6633,8 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) for (i = 0; i < last_frag; i++) { const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; - prod = NEXT_TX_BD(prod); - ring_prod = TX_RING_IDX(prod); + prod = BNX2_NEXT_TX_BD(prod); + ring_prod = BNX2_TX_RING_IDX(prod); txbd = &txr->tx_desc_ring[ring_prod]; len = skb_frag_size(frag); @@ -6652,7 +6658,7 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) netdev_tx_sent_queue(txq, skb->len); - prod = NEXT_TX_BD(prod); + prod = BNX2_NEXT_TX_BD(prod); txr->tx_prod_bseq += skb->len; BNX2_WR16(bp, txr->tx_bidx_addr, prod); @@ -6682,7 +6688,7 @@ dma_error: /* start back at beginning and unmap skb */ prod = txr->tx_prod; - ring_prod = TX_RING_IDX(prod); + ring_prod = BNX2_TX_RING_IDX(prod); tx_buf = &txr->tx_buf_ring[ring_prod]; tx_buf->skb = NULL; dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), @@ -6690,8 +6696,8 @@ dma_error: /* unmap remaining mapped pages */ for (i = 0; i < last_frag; i++) { - prod = NEXT_TX_BD(prod); - ring_prod = TX_RING_IDX(prod); + prod = BNX2_NEXT_TX_BD(prod); + ring_prod = BNX2_TX_RING_IDX(prod); tx_buf = &txr->tx_buf_ring[ring_prod]; dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping), skb_frag_size(&skb_shinfo(skb)->frags[i]), @@ -7254,13 +7260,13 @@ bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) { struct bnx2 *bp = netdev_priv(dev); - ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT; - ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT; + ering->rx_max_pending = BNX2_MAX_TOTAL_RX_DESC_CNT; + ering->rx_jumbo_max_pending = BNX2_MAX_TOTAL_RX_PG_DESC_CNT; ering->rx_pending = bp->rx_ring_size; ering->rx_jumbo_pending = bp->rx_pg_ring_size; - ering->tx_max_pending = MAX_TX_DESC_CNT; + ering->tx_max_pending = BNX2_MAX_TX_DESC_CNT; ering->tx_pending = bp->tx_ring_size; } @@ -7326,8 +7332,8 @@ bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) struct bnx2 *bp = netdev_priv(dev); int rc; - if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) || - (ering->tx_pending > MAX_TX_DESC_CNT) || + if ((ering->rx_pending > BNX2_MAX_TOTAL_RX_DESC_CNT) || + (ering->tx_pending > BNX2_MAX_TX_DESC_CNT) || (ering->tx_pending <= MAX_SKB_FRAGS)) { return -EINVAL; @@ -8299,7 +8305,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bp->mac_addr[4] = (u8) (reg >> 8); bp->mac_addr[5] = (u8) reg; - bp->tx_ring_size = MAX_TX_DESC_CNT; + bp->tx_ring_size = BNX2_MAX_TX_DESC_CNT; bnx2_set_rx_ring_size(bp, 255); bp->tx_quick_cons_trip_int = 2; diff --git a/drivers/net/ethernet/broadcom/bnx2.h b/drivers/net/ethernet/broadcom/bnx2.h index 5f136745ffdd..58caa2266772 100644 --- a/drivers/net/ethernet/broadcom/bnx2.h +++ b/drivers/net/ethernet/broadcom/bnx2.h @@ -20,7 +20,7 @@ /* * tx_bd definition */ -struct tx_bd { +struct bnx2_tx_bd { u32 tx_bd_haddr_hi; u32 tx_bd_haddr_lo; u32 tx_bd_mss_nbytes; @@ -48,7 +48,7 @@ struct tx_bd { /* * rx_bd definition */ -struct rx_bd { +struct bnx2_rx_bd { u32 rx_bd_haddr_hi; u32 rx_bd_haddr_lo; u32 rx_bd_len; @@ -6538,37 +6538,38 @@ struct l2_fhdr { /* Use CPU native page size up to 16K for the ring sizes. */ #if (PAGE_SHIFT > 14) -#define BCM_PAGE_BITS 14 +#define BNX2_PAGE_BITS 14 #else -#define BCM_PAGE_BITS PAGE_SHIFT +#define BNX2_PAGE_BITS PAGE_SHIFT #endif -#define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS) +#define BNX2_PAGE_SIZE (1 << BNX2_PAGE_BITS) -#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct tx_bd)) -#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) +#define BNX2_TX_DESC_CNT (BNX2_PAGE_SIZE / sizeof(struct bnx2_tx_bd)) +#define BNX2_MAX_TX_DESC_CNT (BNX2_TX_DESC_CNT - 1) -#define MAX_RX_RINGS 8 -#define MAX_RX_PG_RINGS 32 -#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct rx_bd)) -#define MAX_RX_DESC_CNT (RX_DESC_CNT - 1) -#define MAX_TOTAL_RX_DESC_CNT (MAX_RX_DESC_CNT * MAX_RX_RINGS) -#define MAX_TOTAL_RX_PG_DESC_CNT (MAX_RX_DESC_CNT * MAX_RX_PG_RINGS) +#define BNX2_MAX_RX_RINGS 8 +#define BNX2_MAX_RX_PG_RINGS 32 +#define BNX2_RX_DESC_CNT (BNX2_PAGE_SIZE / sizeof(struct bnx2_rx_bd)) +#define BNX2_MAX_RX_DESC_CNT (BNX2_RX_DESC_CNT - 1) +#define BNX2_MAX_TOTAL_RX_DESC_CNT (BNX2_MAX_RX_DESC_CNT * BNX2_MAX_RX_RINGS) +#define BNX2_MAX_TOTAL_RX_PG_DESC_CNT \ + (BNX2_MAX_RX_DESC_CNT * BNX2_MAX_RX_PG_RINGS) -#define NEXT_TX_BD(x) (((x) & (MAX_TX_DESC_CNT - 1)) == \ - (MAX_TX_DESC_CNT - 1)) ? \ +#define BNX2_NEXT_TX_BD(x) (((x) & (BNX2_MAX_TX_DESC_CNT - 1)) == \ + (BNX2_MAX_TX_DESC_CNT - 1)) ? \ (x) + 2 : (x) + 1 -#define TX_RING_IDX(x) ((x) & MAX_TX_DESC_CNT) +#define BNX2_TX_RING_IDX(x) ((x) & BNX2_MAX_TX_DESC_CNT) -#define NEXT_RX_BD(x) (((x) & (MAX_RX_DESC_CNT - 1)) == \ - (MAX_RX_DESC_CNT - 1)) ? \ +#define BNX2_NEXT_RX_BD(x) (((x) & (BNX2_MAX_RX_DESC_CNT - 1)) == \ + (BNX2_MAX_RX_DESC_CNT - 1)) ? \ (x) + 2 : (x) + 1 -#define RX_RING_IDX(x) ((x) & bp->rx_max_ring_idx) -#define RX_PG_RING_IDX(x) ((x) & bp->rx_max_pg_ring_idx) +#define BNX2_RX_RING_IDX(x) ((x) & bp->rx_max_ring_idx) +#define BNX2_RX_PG_RING_IDX(x) ((x) & bp->rx_max_pg_ring_idx) -#define RX_RING(x) (((x) & ~MAX_RX_DESC_CNT) >> (BCM_PAGE_BITS - 4)) -#define RX_IDX(x) ((x) & MAX_RX_DESC_CNT) +#define BNX2_RX_RING(x) (((x) & ~BNX2_MAX_RX_DESC_CNT) >> (BNX2_PAGE_BITS - 4)) +#define BNX2_RX_IDX(x) ((x) & BNX2_MAX_RX_DESC_CNT) /* Context size. */ #define CTX_SHIFT 7 @@ -6609,7 +6610,7 @@ struct l2_fhdr { * RX ring buffer contains pointer to kmalloc() data only, * skb are built only after Hardware filled the frame. */ -struct sw_bd { +struct bnx2_sw_bd { u8 *data; DEFINE_DMA_UNMAP_ADDR(mapping); }; @@ -6623,23 +6624,23 @@ static inline struct l2_fhdr *get_l2_fhdr(u8 *data) } -struct sw_pg { +struct bnx2_sw_pg { struct page *page; DEFINE_DMA_UNMAP_ADDR(mapping); }; -struct sw_tx_bd { +struct bnx2_sw_tx_bd { struct sk_buff *skb; DEFINE_DMA_UNMAP_ADDR(mapping); unsigned short is_gso; unsigned short nr_frags; }; -#define SW_RXBD_RING_SIZE (sizeof(struct sw_bd) * RX_DESC_CNT) -#define SW_RXPG_RING_SIZE (sizeof(struct sw_pg) * RX_DESC_CNT) -#define RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT) -#define SW_TXBD_RING_SIZE (sizeof(struct sw_tx_bd) * TX_DESC_CNT) -#define TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT) +#define SW_RXBD_RING_SIZE (sizeof(struct bnx2_sw_bd) * BNX2_RX_DESC_CNT) +#define SW_RXPG_RING_SIZE (sizeof(struct bnx2_sw_pg) * BNX2_RX_DESC_CNT) +#define RXBD_RING_SIZE (sizeof(struct bnx2_rx_bd) * BNX2_RX_DESC_CNT) +#define SW_TXBD_RING_SIZE (sizeof(struct bnx2_sw_tx_bd) * BNX2_TX_DESC_CNT) +#define TXBD_RING_SIZE (sizeof(struct bnx2_tx_bd) * BNX2_TX_DESC_CNT) /* Buffered flash (Atmel: AT45DB011B) specific information */ #define SEEPROM_PAGE_BITS 2 @@ -6720,8 +6721,8 @@ struct bnx2_tx_ring_info { u32 tx_bidx_addr; u32 tx_bseq_addr; - struct tx_bd *tx_desc_ring; - struct sw_tx_bd *tx_buf_ring; + struct bnx2_tx_bd *tx_desc_ring; + struct bnx2_sw_tx_bd *tx_buf_ring; u16 tx_cons; u16 hw_tx_cons; @@ -6741,13 +6742,13 @@ struct bnx2_rx_ring_info { u16 rx_pg_prod; u16 rx_pg_cons; - struct sw_bd *rx_buf_ring; - struct rx_bd *rx_desc_ring[MAX_RX_RINGS]; - struct sw_pg *rx_pg_ring; - struct rx_bd *rx_pg_desc_ring[MAX_RX_PG_RINGS]; + struct bnx2_sw_bd *rx_buf_ring; + struct bnx2_rx_bd *rx_desc_ring[BNX2_MAX_RX_RINGS]; + struct bnx2_sw_pg *rx_pg_ring; + struct bnx2_rx_bd *rx_pg_desc_ring[BNX2_MAX_RX_PG_RINGS]; - dma_addr_t rx_desc_mapping[MAX_RX_RINGS]; - dma_addr_t rx_pg_desc_mapping[MAX_RX_PG_RINGS]; + dma_addr_t rx_desc_mapping[BNX2_MAX_RX_RINGS]; + dma_addr_t rx_pg_desc_mapping[BNX2_MAX_RX_PG_RINGS]; }; struct bnx2_napi { @@ -7052,7 +7053,7 @@ struct bnx2_rv2p_fw_file { #define RV2P_P1_FIXUP_PAGE_SIZE_IDX 0 #define RV2P_BD_PAGE_SIZE_MSK 0xffff -#define RV2P_BD_PAGE_SIZE ((BCM_PAGE_SIZE / 16) - 1) +#define RV2P_BD_PAGE_SIZE ((BNX2_PAGE_SIZE / 16) - 1) #define RV2P_PROC1 0 #define RV2P_PROC2 1 diff --git a/drivers/net/ethernet/broadcom/cnic.c b/drivers/net/ethernet/broadcom/cnic.c index 091c60a9897c..756a2a771291 100644 --- a/drivers/net/ethernet/broadcom/cnic.c +++ b/drivers/net/ethernet/broadcom/cnic.c @@ -724,7 +724,7 @@ static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma) for (i = 0; i < dma->num_pages; i++) { if (dma->pg_arr[i]) { - dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE, + dma_free_coherent(&dev->pcidev->dev, BNX2_PAGE_SIZE, dma->pg_arr[i], dma->pg_map_arr[i]); dma->pg_arr[i] = NULL; } @@ -783,7 +783,7 @@ static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma, for (i = 0; i < pages; i++) { dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev, - BCM_PAGE_SIZE, + BNX2_PAGE_SIZE, &dma->pg_map_arr[i], GFP_ATOMIC); if (dma->pg_arr[i] == NULL) @@ -792,8 +792,8 @@ static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma, if (!use_pg_tbl) return 0; - dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) & - ~(BCM_PAGE_SIZE - 1); + dma->pgtbl_size = ((pages * 8) + BNX2_PAGE_SIZE - 1) & + ~(BNX2_PAGE_SIZE - 1); dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size, &dma->pgtbl_map, GFP_ATOMIC); if (dma->pgtbl == NULL) @@ -898,8 +898,8 @@ static int cnic_alloc_context(struct cnic_dev *dev) if (CHIP_NUM(cp) == CHIP_NUM_5709) { int i, k, arr_size; - cp->ctx_blk_size = BCM_PAGE_SIZE; - cp->cids_per_blk = BCM_PAGE_SIZE / 128; + cp->ctx_blk_size = BNX2_PAGE_SIZE; + cp->cids_per_blk = BNX2_PAGE_SIZE / 128; arr_size = BNX2_MAX_CID / cp->cids_per_blk * sizeof(struct cnic_ctx); cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL); @@ -931,7 +931,7 @@ static int cnic_alloc_context(struct cnic_dev *dev) for (i = 0; i < cp->ctx_blks; i++) { cp->ctx_arr[i].ctx = dma_alloc_coherent(&dev->pcidev->dev, - BCM_PAGE_SIZE, + BNX2_PAGE_SIZE, &cp->ctx_arr[i].mapping, GFP_KERNEL); if (cp->ctx_arr[i].ctx == NULL) @@ -1011,7 +1011,7 @@ static int __cnic_alloc_uio_rings(struct cnic_uio_dev *udev, int pages) if (udev->l2_ring) return 0; - udev->l2_ring_size = pages * BCM_PAGE_SIZE; + udev->l2_ring_size = pages * BNX2_PAGE_SIZE; udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size, &udev->l2_ring_map, GFP_KERNEL | __GFP_COMP); @@ -2898,7 +2898,7 @@ static int cnic_l2_completion(struct cnic_local *cp) u16 hw_cons, sw_cons; struct cnic_uio_dev *udev = cp->udev; union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *) - (udev->l2_ring + (2 * BCM_PAGE_SIZE)); + (udev->l2_ring + (2 * BNX2_PAGE_SIZE)); u32 cmd; int comp = 0; @@ -4366,7 +4366,7 @@ static int cnic_setup_5709_context(struct cnic_dev *dev, int valid) u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk; u32 val; - memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE); + memset(cp->ctx_arr[i].ctx, 0, BNX2_PAGE_SIZE); CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0, (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit); @@ -4508,7 +4508,7 @@ static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev) u32 cid_addr, tx_cid, sb_id; u32 val, offset0, offset1, offset2, offset3; int i; - struct tx_bd *txbd; + struct bnx2_tx_bd *txbd; dma_addr_t buf_map, ring_map = udev->l2_ring_map; struct status_block *s_blk = cp->status_blk.gen; @@ -4554,7 +4554,7 @@ static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev) txbd = udev->l2_ring; buf_map = udev->l2_buf_map; - for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) { + for (i = 0; i < BNX2_MAX_TX_DESC_CNT; i++, txbd++) { txbd->tx_bd_haddr_hi = (u64) buf_map >> 32; txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff; } @@ -4574,7 +4574,7 @@ static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev) struct cnic_uio_dev *udev = cp->udev; u32 cid_addr, sb_id, val, coal_reg, coal_val; int i; - struct rx_bd *rxbd; + struct bnx2_rx_bd *rxbd; struct status_block *s_blk = cp->status_blk.gen; dma_addr_t ring_map = udev->l2_ring_map; @@ -4610,8 +4610,8 @@ static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev) val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id); cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val); - rxbd = udev->l2_ring + BCM_PAGE_SIZE; - for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) { + rxbd = udev->l2_ring + BNX2_PAGE_SIZE; + for (i = 0; i < BNX2_MAX_RX_DESC_CNT; i++, rxbd++) { dma_addr_t buf_map; int n = (i % cp->l2_rx_ring_size) + 1; @@ -4621,11 +4621,11 @@ static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev) rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32; rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff; } - val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32; + val = (u64) (ring_map + BNX2_PAGE_SIZE) >> 32; cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val); rxbd->rx_bd_haddr_hi = val; - val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff; + val = (u64) (ring_map + BNX2_PAGE_SIZE) & 0xffffffff; cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val); rxbd->rx_bd_haddr_lo = val; @@ -4691,10 +4691,10 @@ static int cnic_start_bnx2_hw(struct cnic_dev *dev) val = CNIC_RD(dev, BNX2_MQ_CONFIG); val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; - if (BCM_PAGE_BITS > 12) + if (BNX2_PAGE_BITS > 12) val |= (12 - 8) << 4; else - val |= (BCM_PAGE_BITS - 8) << 4; + val |= (BNX2_PAGE_BITS - 8) << 4; CNIC_WR(dev, BNX2_MQ_CONFIG, val); @@ -4724,13 +4724,13 @@ static int cnic_start_bnx2_hw(struct cnic_dev *dev) /* Initialize the kernel work queue context. */ val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE | - (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ; + (BNX2_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ; cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val); - val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16; + val = (BNX2_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16; cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val); - val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT; + val = ((BNX2_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT; cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val); val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32); @@ -4750,13 +4750,13 @@ static int cnic_start_bnx2_hw(struct cnic_dev *dev) /* Initialize the kernel complete queue context. */ val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE | - (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ; + (BNX2_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ; cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val); - val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16; + val = (BNX2_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16; cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val); - val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT; + val = ((BNX2_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT; cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val); val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32); @@ -4895,10 +4895,10 @@ static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev, u32 cli = cp->ethdev->iscsi_l2_client_id; u32 val; - memset(txbd, 0, BCM_PAGE_SIZE); + memset(txbd, 0, BNX2_PAGE_SIZE); buf_map = udev->l2_buf_map; - for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) { + for (i = 0; i < BNX2_MAX_TX_DESC_CNT; i += 3, txbd += 3) { struct eth_tx_start_bd *start_bd = &txbd->start_bd; struct eth_tx_parse_bd_e1x *pbd_e1x = &((txbd + 1)->parse_bd_e1x); @@ -4954,9 +4954,9 @@ static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev, struct cnic_local *cp = dev->cnic_priv; struct cnic_uio_dev *udev = cp->udev; struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring + - BCM_PAGE_SIZE); + BNX2_PAGE_SIZE); struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *) - (udev->l2_ring + (2 * BCM_PAGE_SIZE)); + (udev->l2_ring + (2 * BNX2_PAGE_SIZE)); struct host_sp_status_block *sb = cp->bnx2x_def_status_blk; int i; u32 cli = cp->ethdev->iscsi_l2_client_id; @@ -4980,20 +4980,20 @@ static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev, rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff); } - val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32; + val = (u64) (ring_map + BNX2_PAGE_SIZE) >> 32; rxbd->addr_hi = cpu_to_le32(val); data->rx.bd_page_base.hi = cpu_to_le32(val); - val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff; + val = (u64) (ring_map + BNX2_PAGE_SIZE) & 0xffffffff; rxbd->addr_lo = cpu_to_le32(val); data->rx.bd_page_base.lo = cpu_to_le32(val); rxcqe += BNX2X_MAX_RCQ_DESC_CNT; - val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32; + val = (u64) (ring_map + (2 * BNX2_PAGE_SIZE)) >> 32; rxcqe->addr_hi = cpu_to_le32(val); data->rx.cqe_page_base.hi = cpu_to_le32(val); - val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff; + val = (u64) (ring_map + (2 * BNX2_PAGE_SIZE)) & 0xffffffff; rxcqe->addr_lo = cpu_to_le32(val); data->rx.cqe_page_base.lo = cpu_to_le32(val); @@ -5258,8 +5258,8 @@ static void cnic_shutdown_rings(struct cnic_dev *dev) msleep(10); } clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags); - rx_ring = udev->l2_ring + BCM_PAGE_SIZE; - memset(rx_ring, 0, BCM_PAGE_SIZE); + rx_ring = udev->l2_ring + BNX2_PAGE_SIZE; + memset(rx_ring, 0, BNX2_PAGE_SIZE); } static int cnic_register_netdev(struct cnic_dev *dev) diff --git a/drivers/net/ethernet/broadcom/cnic.h b/drivers/net/ethernet/broadcom/cnic.h index 148604c3fa0c..6fa7a989606a 100644 --- a/drivers/net/ethernet/broadcom/cnic.h +++ b/drivers/net/ethernet/broadcom/cnic.h @@ -80,18 +80,18 @@ #define CNIC_LOCAL_PORT_MAX 61024 #define CNIC_LOCAL_PORT_RANGE (CNIC_LOCAL_PORT_MAX - CNIC_LOCAL_PORT_MIN) -#define KWQE_CNT (BCM_PAGE_SIZE / sizeof(struct kwqe)) -#define KCQE_CNT (BCM_PAGE_SIZE / sizeof(struct kcqe)) +#define KWQE_CNT (BNX2_PAGE_SIZE / sizeof(struct kwqe)) +#define KCQE_CNT (BNX2_PAGE_SIZE / sizeof(struct kcqe)) #define MAX_KWQE_CNT (KWQE_CNT - 1) #define MAX_KCQE_CNT (KCQE_CNT - 1) #define MAX_KWQ_IDX ((KWQ_PAGE_CNT * KWQE_CNT) - 1) #define MAX_KCQ_IDX ((KCQ_PAGE_CNT * KCQE_CNT) - 1) -#define KWQ_PG(x) (((x) & ~MAX_KWQE_CNT) >> (BCM_PAGE_BITS - 5)) +#define KWQ_PG(x) (((x) & ~MAX_KWQE_CNT) >> (BNX2_PAGE_BITS - 5)) #define KWQ_IDX(x) ((x) & MAX_KWQE_CNT) -#define KCQ_PG(x) (((x) & ~MAX_KCQE_CNT) >> (BCM_PAGE_BITS - 5)) +#define KCQ_PG(x) (((x) & ~MAX_KCQE_CNT) >> (BNX2_PAGE_BITS - 5)) #define KCQ_IDX(x) ((x) & MAX_KCQE_CNT) #define BNX2X_NEXT_KCQE(x) (((x) & (MAX_KCQE_CNT - 1)) == \ @@ -422,9 +422,11 @@ struct bnx2x_bd_chain_next { #define IS_E1H_OFFSET BNX2X_CHIP_IS_E1H(cp->chip_id) -#define BNX2X_RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) +#define BNX2X_RX_DESC_CNT (BNX2_PAGE_SIZE / \ + sizeof(struct eth_rx_bd)) #define BNX2X_MAX_RX_DESC_CNT (BNX2X_RX_DESC_CNT - 2) -#define BNX2X_RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) +#define BNX2X_RCQ_DESC_CNT (BNX2_PAGE_SIZE / \ + sizeof(union eth_rx_cqe)) #define BNX2X_MAX_RCQ_DESC_CNT (BNX2X_RCQ_DESC_CNT - 1) #define BNX2X_NEXT_RCQE(x) (((x) & BNX2X_MAX_RCQ_DESC_CNT) == \ -- cgit v1.2.3 From 4ce45e02469c382699f4c5f6df727aea9dd2e1ca Mon Sep 17 00:00:00 2001 From: Michael Chan Date: Thu, 6 Dec 2012 10:33:10 +0000 Subject: bnx2: Add BNX2 prefix to CHIP ID and name macros for namespace consistency. Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/ethernet/broadcom/bnx2.c | 178 ++++++++++++++++++----------------- drivers/net/ethernet/broadcom/bnx2.h | 48 +++++----- drivers/net/ethernet/broadcom/cnic.c | 14 +-- 3 files changed, 120 insertions(+), 120 deletions(-) (limited to 'drivers/net/ethernet/broadcom/bnx2.c') diff --git a/drivers/net/ethernet/broadcom/bnx2.c b/drivers/net/ethernet/broadcom/bnx2.c index 98cb76b9482c..a9b2feaf2879 100644 --- a/drivers/net/ethernet/broadcom/bnx2.c +++ b/drivers/net/ethernet/broadcom/bnx2.c @@ -306,7 +306,7 @@ bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) { offset += cid_addr; spin_lock_bh(&bp->indirect_lock); - if (CHIP_NUM(bp) == CHIP_NUM_5709) { + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { int i; BNX2_WR(bp, BNX2_CTX_CTX_DATA, val); @@ -887,7 +887,7 @@ bnx2_alloc_mem(struct bnx2 *bp) bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size; - if (CHIP_NUM(bp) == CHIP_NUM_5709) { + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE; if (bp->ctx_pages == 0) bp->ctx_pages = 1; @@ -1034,7 +1034,7 @@ bnx2_resolve_flow_ctrl(struct bnx2 *bp) } if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && - (CHIP_NUM(bp) == CHIP_NUM_5708)) { + (BNX2_CHIP(bp) == BNX2_CHIP_5708)) { u32 val; bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val); @@ -1310,7 +1310,7 @@ bnx2_set_mac_link(struct bnx2 *bp) if (bp->link_up) { switch (bp->line_speed) { case SPEED_10: - if (CHIP_NUM(bp) != CHIP_NUM_5706) { + if (BNX2_CHIP(bp) != BNX2_CHIP_5706) { val |= BNX2_EMAC_MODE_PORT_MII_10M; break; } @@ -1360,7 +1360,7 @@ static void bnx2_enable_bmsr1(struct bnx2 *bp) { if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && - (CHIP_NUM(bp) == CHIP_NUM_5709)) + (BNX2_CHIP(bp) == BNX2_CHIP_5709)) bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS); } @@ -1369,7 +1369,7 @@ static void bnx2_disable_bmsr1(struct bnx2 *bp) { if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && - (CHIP_NUM(bp) == CHIP_NUM_5709)) + (BNX2_CHIP(bp) == BNX2_CHIP_5709)) bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); } @@ -1386,7 +1386,7 @@ bnx2_test_and_enable_2g5(struct bnx2 *bp) if (bp->autoneg & AUTONEG_SPEED) bp->advertising |= ADVERTISED_2500baseX_Full; - if (CHIP_NUM(bp) == CHIP_NUM_5709) + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); bnx2_read_phy(bp, bp->mii_up1, &up1); @@ -1396,7 +1396,7 @@ bnx2_test_and_enable_2g5(struct bnx2 *bp) ret = 0; } - if (CHIP_NUM(bp) == CHIP_NUM_5709) + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); @@ -1412,7 +1412,7 @@ bnx2_test_and_disable_2g5(struct bnx2 *bp) if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) return 0; - if (CHIP_NUM(bp) == CHIP_NUM_5709) + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); bnx2_read_phy(bp, bp->mii_up1, &up1); @@ -1422,7 +1422,7 @@ bnx2_test_and_disable_2g5(struct bnx2 *bp) ret = 1; } - if (CHIP_NUM(bp) == CHIP_NUM_5709) + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); @@ -1438,7 +1438,7 @@ bnx2_enable_forced_2g5(struct bnx2 *bp) if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) return; - if (CHIP_NUM(bp) == CHIP_NUM_5709) { + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { u32 val; bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, @@ -1454,7 +1454,7 @@ bnx2_enable_forced_2g5(struct bnx2 *bp) MII_BNX2_BLK_ADDR_COMBO_IEEEB0); err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); - } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { + } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) { err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); if (!err) bmcr |= BCM5708S_BMCR_FORCE_2500; @@ -1482,7 +1482,7 @@ bnx2_disable_forced_2g5(struct bnx2 *bp) if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) return; - if (CHIP_NUM(bp) == CHIP_NUM_5709) { + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { u32 val; bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, @@ -1496,7 +1496,7 @@ bnx2_disable_forced_2g5(struct bnx2 *bp) MII_BNX2_BLK_ADDR_COMBO_IEEEB0); err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); - } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { + } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) { err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); if (!err) bmcr &= ~BCM5708S_BMCR_FORCE_2500; @@ -1547,7 +1547,7 @@ bnx2_set_link(struct bnx2 *bp) bnx2_disable_bmsr1(bp); if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && - (CHIP_NUM(bp) == CHIP_NUM_5706)) { + (BNX2_CHIP(bp) == BNX2_CHIP_5706)) { u32 val, an_dbg; if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) { @@ -1571,11 +1571,11 @@ bnx2_set_link(struct bnx2 *bp) bp->link_up = 1; if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { - if (CHIP_NUM(bp) == CHIP_NUM_5706) + if (BNX2_CHIP(bp) == BNX2_CHIP_5706) bnx2_5706s_linkup(bp); - else if (CHIP_NUM(bp) == CHIP_NUM_5708) + else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) bnx2_5708s_linkup(bp); - else if (CHIP_NUM(bp) == CHIP_NUM_5709) + else if (BNX2_CHIP(bp) == BNX2_CHIP_5709) bnx2_5709s_linkup(bp); } else { @@ -1757,7 +1757,7 @@ __acquires(&bp->phy_lock) new_bmcr = bmcr & ~BMCR_ANENABLE; new_bmcr |= BMCR_SPEED1000; - if (CHIP_NUM(bp) == CHIP_NUM_5709) { + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { if (bp->req_line_speed == SPEED_2500) bnx2_enable_forced_2g5(bp); else if (bp->req_line_speed == SPEED_1000) { @@ -1765,7 +1765,7 @@ __acquires(&bp->phy_lock) new_bmcr &= ~0x2000; } - } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { + } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) { if (bp->req_line_speed == SPEED_2500) new_bmcr |= BCM5708S_BMCR_FORCE_2500; else @@ -2230,9 +2230,9 @@ bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy) bnx2_write_phy(bp, BCM5708S_UP1, val); } - if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || - (CHIP_ID(bp) == CHIP_ID_5708_B0) || - (CHIP_ID(bp) == CHIP_ID_5708_B1)) { + if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) || + (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) || + (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1)) { /* increase tx signal amplitude */ bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_TX_MISC); @@ -2268,7 +2268,7 @@ bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy) bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; - if (CHIP_NUM(bp) == CHIP_NUM_5706) + if (BNX2_CHIP(bp) == BNX2_CHIP_5706) BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300); if (bp->dev->mtu > 1500) { @@ -2379,11 +2379,11 @@ __acquires(&bp->phy_lock) bp->phy_id |= val & 0xffff; if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { - if (CHIP_NUM(bp) == CHIP_NUM_5706) + if (BNX2_CHIP(bp) == BNX2_CHIP_5706) rc = bnx2_init_5706s_phy(bp, reset_phy); - else if (CHIP_NUM(bp) == CHIP_NUM_5708) + else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) rc = bnx2_init_5708s_phy(bp, reset_phy); - else if (CHIP_NUM(bp) == CHIP_NUM_5709) + else if (BNX2_CHIP(bp) == BNX2_CHIP_5709) rc = bnx2_init_5709s_phy(bp, reset_phy); } else { @@ -2449,7 +2449,7 @@ bnx2_dump_mcp_state(struct bnx2 *bp) u32 mcp_p0, mcp_p1; netdev_err(dev, "<--- start MCP states dump --->\n"); - if (CHIP_NUM(bp) == CHIP_NUM_5709) { + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { mcp_p0 = BNX2_MCP_STATE_P0; mcp_p1 = BNX2_MCP_STATE_P1; } else { @@ -2591,7 +2591,7 @@ bnx2_init_context(struct bnx2 *bp) vcid--; - if (CHIP_ID(bp) == CHIP_ID_5706_A0) { + if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { u32 new_vcid; vcid_addr = GET_PCID_ADDR(vcid); @@ -3668,10 +3668,10 @@ static int bnx2_request_uncached_firmware(struct bnx2 *bp) const struct bnx2_rv2p_fw_file *rv2p_fw; int rc; - if (CHIP_NUM(bp) == CHIP_NUM_5709) { + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { mips_fw_file = FW_MIPS_FILE_09; - if ((CHIP_ID(bp) == CHIP_ID_5709_A0) || - (CHIP_ID(bp) == CHIP_ID_5709_A1)) + if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A0) || + (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A1)) rv2p_fw_file = FW_RV2P_FILE_09_Ax; else rv2p_fw_file = FW_RV2P_FILE_09; @@ -4021,8 +4021,8 @@ bnx2_set_power_state(struct bnx2 *bp, pci_power_t state) 1, 0); pmcsr &= ~PCI_PM_CTRL_STATE_MASK; - if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || - (CHIP_ID(bp) == CHIP_ID_5706_A1)) { + if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) || + (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) { if (bp->wol) pmcsr |= 3; @@ -4292,7 +4292,7 @@ bnx2_init_nvram(struct bnx2 *bp) int j, entry_count, rc = 0; const struct flash_spec *flash; - if (CHIP_NUM(bp) == CHIP_NUM_5709) { + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { bp->flash_info = &flash_5709; goto get_flash_size; } @@ -4716,8 +4716,8 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) /* Wait for the current PCI transaction to complete before * issuing a reset. */ - if ((CHIP_NUM(bp) == CHIP_NUM_5706) || - (CHIP_NUM(bp) == CHIP_NUM_5708)) { + if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) || + (BNX2_CHIP(bp) == BNX2_CHIP_5708)) { BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS, BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | @@ -4751,7 +4751,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) * before we issue a reset. */ val = BNX2_RD(bp, BNX2_MISC_ID); - if (CHIP_NUM(bp) == CHIP_NUM_5709) { + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET); BNX2_RD(bp, BNX2_MISC_COMMAND); udelay(5); @@ -4773,8 +4773,8 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) * bus on 5706 A0 and A1. The msleep below provides plenty * of margin for write posting. */ - if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || - (CHIP_ID(bp) == CHIP_ID_5706_A1)) + if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) || + (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) msleep(20); /* Reset takes approximate 30 usec */ @@ -4813,7 +4813,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) bnx2_set_default_remote_link(bp); spin_unlock_bh(&bp->phy_lock); - if (CHIP_ID(bp) == CHIP_ID_5706_A0) { + if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { /* Adjust the voltage regular to two steps lower. The default * of this register is 0x0000000e. */ BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa); @@ -4855,13 +4855,14 @@ bnx2_init_chip(struct bnx2 *bp) if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133)) val |= (1 << 23); - if ((CHIP_NUM(bp) == CHIP_NUM_5706) && - (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX)) + if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) && + (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0) && + !(bp->flags & BNX2_FLAG_PCIX)) val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA; BNX2_WR(bp, BNX2_DMA_CONFIG, val); - if (CHIP_ID(bp) == CHIP_ID_5706_A0) { + if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { val = BNX2_RD(bp, BNX2_TDMA_CONFIG); val |= BNX2_TDMA_CONFIG_ONE_DMA; BNX2_WR(bp, BNX2_TDMA_CONFIG, val); @@ -4883,7 +4884,7 @@ bnx2_init_chip(struct bnx2 *bp) /* Initialize context mapping and zero out the quick contexts. The * context block must have already been enabled. */ - if (CHIP_NUM(bp) == CHIP_NUM_5709) { + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { rc = bnx2_init_5709_context(bp); if (rc) return rc; @@ -4900,9 +4901,9 @@ bnx2_init_chip(struct bnx2 *bp) val = BNX2_RD(bp, BNX2_MQ_CONFIG); val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; - if (CHIP_NUM(bp) == CHIP_NUM_5709) { + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { val |= BNX2_MQ_CONFIG_BIN_MQ_MODE; - if (CHIP_REV(bp) == CHIP_REV_Ax) + if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax) val |= BNX2_MQ_CONFIG_HALT_DIS; } @@ -4988,7 +4989,7 @@ bnx2_init_chip(struct bnx2 *bp) BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks); BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ - if (CHIP_ID(bp) == CHIP_ID_5706_A1) + if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) val = BNX2_HC_CONFIG_COLLECT_STATS; else { val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE | @@ -5044,7 +5045,7 @@ bnx2_init_chip(struct bnx2 *bp) /* Initialize the receive filter. */ bnx2_set_rx_mode(bp->dev); - if (CHIP_NUM(bp) == CHIP_NUM_5709) { + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL); val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE; BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val); @@ -5091,7 +5092,7 @@ bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr) u32 val, offset0, offset1, offset2, offset3; u32 cid_addr = GET_CID_ADDR(cid); - if (CHIP_NUM(bp) == CHIP_NUM_5709) { + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { offset0 = BNX2_L2CTX_TYPE_XI; offset1 = BNX2_L2CTX_CMD_TYPE_XI; offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI; @@ -5192,7 +5193,7 @@ bnx2_init_rx_ring(struct bnx2 *bp, int ring_num) bnx2_init_rx_context(bp, cid); - if (CHIP_NUM(bp) == CHIP_NUM_5709) { + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5); BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM); } @@ -5213,7 +5214,7 @@ bnx2_init_rx_ring(struct bnx2 *bp, int ring_num) val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff; bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val); - if (CHIP_NUM(bp) == CHIP_NUM_5709) + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT); } @@ -5621,7 +5622,7 @@ bnx2_test_registers(struct bnx2 *bp) ret = 0; is_5709 = 0; - if (CHIP_NUM(bp) == CHIP_NUM_5709) + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) is_5709 = 1; for (i = 0; reg_tbl[i].offset != 0xffff; i++) { @@ -5720,7 +5721,7 @@ bnx2_test_memory(struct bnx2 *bp) }; struct mem_entry *mem_tbl; - if (CHIP_NUM(bp) == CHIP_NUM_5709) + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) mem_tbl = mem_tbl_5709; else mem_tbl = mem_tbl_5706; @@ -6142,7 +6143,7 @@ bnx2_timer(unsigned long data) BNX2_HC_COMMAND_STATS_NOW); if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { - if (CHIP_NUM(bp) == CHIP_NUM_5706) + if (BNX2_CHIP(bp) == BNX2_CHIP_5706) bnx2_5706_serdes_timer(bp); else bnx2_5708_serdes_timer(bp); @@ -6280,7 +6281,7 @@ bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi) !(bp->flags & BNX2_FLAG_USING_MSIX)) { if (pci_enable_msi(bp->pdev) == 0) { bp->flags |= BNX2_FLAG_USING_MSI; - if (CHIP_NUM(bp) == CHIP_NUM_5709) { + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { bp->flags |= BNX2_FLAG_ONE_SHOT_MSI; bp->irq_tbl[0].handler = bnx2_msi_1shot; } else @@ -6816,8 +6817,8 @@ bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats) GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) + GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions); - if ((CHIP_NUM(bp) == CHIP_NUM_5706) || - (CHIP_ID(bp) == CHIP_ID_5708_A0)) + if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) || + (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0)) net_stats->tx_carrier_errors = 0; else { net_stats->tx_carrier_errors = @@ -7620,10 +7621,10 @@ bnx2_get_ethtool_stats(struct net_device *dev, return; } - if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || - (CHIP_ID(bp) == CHIP_ID_5706_A1) || - (CHIP_ID(bp) == CHIP_ID_5706_A2) || - (CHIP_ID(bp) == CHIP_ID_5708_A0)) + if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) || + (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) || + (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A2) || + (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0)) stats_len_arr = bnx2_5706_stats_len_arr; else stats_len_arr = bnx2_5708_stats_len_arr; @@ -8143,14 +8144,14 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID); - if (CHIP_NUM(bp) == CHIP_NUM_5709) { + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) { if (!pci_is_pcie(pdev)) { dev_err(&pdev->dev, "Not PCIE, aborting\n"); rc = -EIO; goto err_out_unmap; } bp->flags |= BNX2_FLAG_PCIE; - if (CHIP_REV(bp) == CHIP_REV_Ax) + if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax) bp->flags |= BNX2_FLAG_JUMBO_BROKEN; /* AER (Advanced Error Reporting) hooks */ @@ -8169,18 +8170,20 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bp->flags |= BNX2_FLAG_BROKEN_STATS; } - if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) { + if (BNX2_CHIP(bp) == BNX2_CHIP_5709 && + BNX2_CHIP_REV(bp) != BNX2_CHIP_REV_Ax) { if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) bp->flags |= BNX2_FLAG_MSIX_CAP; } - if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) { + if (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0 && + BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A1) { if (pci_find_capability(pdev, PCI_CAP_ID_MSI)) bp->flags |= BNX2_FLAG_MSI_CAP; } /* 5708 cannot support DMA addresses > 40-bit. */ - if (CHIP_NUM(bp) == CHIP_NUM_5708) + if (BNX2_CHIP(bp) == BNX2_CHIP_5708) persist_dma_mask = dma_mask = DMA_BIT_MASK(40); else persist_dma_mask = dma_mask = DMA_BIT_MASK(64); @@ -8203,12 +8206,11 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bnx2_get_pci_speed(bp); /* 5706A0 may falsely detect SERR and PERR. */ - if (CHIP_ID(bp) == CHIP_ID_5706_A0) { + if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { reg = BNX2_RD(bp, PCI_COMMAND); reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); BNX2_WR(bp, PCI_COMMAND, reg); - } - else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) && + } else if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) && !(bp->flags & BNX2_FLAG_PCIX)) { dev_err(&pdev->dev, @@ -8325,9 +8327,9 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bp->phy_addr = 1; /* Disable WOL support if we are running on a SERDES chip. */ - if (CHIP_NUM(bp) == CHIP_NUM_5709) + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) bnx2_get_5709_media(bp); - else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) + else if (BNX2_CHIP_BOND(bp) & BNX2_CHIP_BOND_SERDES_BIT) bp->phy_flags |= BNX2_PHY_FLAG_SERDES; bp->phy_port = PORT_TP; @@ -8338,7 +8340,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bp->flags |= BNX2_FLAG_NO_WOL; bp->wol = 0; } - if (CHIP_NUM(bp) == CHIP_NUM_5706) { + if (BNX2_CHIP(bp) == BNX2_CHIP_5706) { /* Don't do parallel detect on this board because of * some board problems. The link will not go down * if we do parallel detect. @@ -8351,25 +8353,25 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G) bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE; } - } else if (CHIP_NUM(bp) == CHIP_NUM_5706 || - CHIP_NUM(bp) == CHIP_NUM_5708) + } else if (BNX2_CHIP(bp) == BNX2_CHIP_5706 || + BNX2_CHIP(bp) == BNX2_CHIP_5708) bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX; - else if (CHIP_NUM(bp) == CHIP_NUM_5709 && - (CHIP_REV(bp) == CHIP_REV_Ax || - CHIP_REV(bp) == CHIP_REV_Bx)) + else if (BNX2_CHIP(bp) == BNX2_CHIP_5709 && + (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax || + BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Bx)) bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC; bnx2_init_fw_cap(bp); - if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || - (CHIP_ID(bp) == CHIP_ID_5708_B0) || - (CHIP_ID(bp) == CHIP_ID_5708_B1) || + if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) || + (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) || + (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1) || !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) { bp->flags |= BNX2_FLAG_NO_WOL; bp->wol = 0; } - if (CHIP_ID(bp) == CHIP_ID_5706_A0) { + if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) { bp->tx_quick_cons_trip_int = bp->tx_quick_cons_trip; bp->tx_ticks_int = bp->tx_ticks; @@ -8391,7 +8393,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) * AMD believes this incompatibility is unique to the 5706, and * prefers to locally disable MSI rather than globally disabling it. */ - if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) { + if (BNX2_CHIP(bp) == BNX2_CHIP_5706 && disable_msi == 0) { struct pci_dev *amd_8132 = NULL; while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD, @@ -8547,7 +8549,7 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_RXHASH | NETIF_F_RXCSUM; - if (CHIP_NUM(bp) == CHIP_NUM_5709) + if (BNX2_CHIP(bp) == BNX2_CHIP_5709) dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; dev->vlan_features = dev->hw_features; @@ -8562,15 +8564,15 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, " "node addr %pM\n", board_info[ent->driver_data].name, - ((CHIP_ID(bp) & 0xf000) >> 12) + 'A', - ((CHIP_ID(bp) & 0x0ff0) >> 4), + ((BNX2_CHIP_ID(bp) & 0xf000) >> 12) + 'A', + ((BNX2_CHIP_ID(bp) & 0x0ff0) >> 4), bnx2_bus_string(bp, str), (long)pci_resource_start(pdev, 0), pdev->irq, dev->dev_addr); return 0; error: - pci_iounmap(pdev, bp->regview); + iounmap(bp->regview); pci_release_regions(pdev); pci_disable_device(pdev); pci_set_drvdata(pdev, NULL); @@ -8748,7 +8750,7 @@ static void bnx2_io_resume(struct pci_dev *pdev) rtnl_unlock(); } -static const struct pci_error_handlers bnx2_err_handler = { +static struct pci_error_handlers bnx2_err_handler = { .error_detected = bnx2_io_error_detected, .slot_reset = bnx2_io_slot_reset, .resume = bnx2_io_resume, diff --git a/drivers/net/ethernet/broadcom/bnx2.h b/drivers/net/ethernet/broadcom/bnx2.h index 58caa2266772..38a640df58f7 100644 --- a/drivers/net/ethernet/broadcom/bnx2.h +++ b/drivers/net/ethernet/broadcom/bnx2.h @@ -6854,33 +6854,31 @@ struct bnx2 { u32 chip_id; /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ -#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000) -#define CHIP_NUM_5706 0x57060000 -#define CHIP_NUM_5708 0x57080000 -#define CHIP_NUM_5709 0x57090000 - -#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000) -#define CHIP_REV_Ax 0x00000000 -#define CHIP_REV_Bx 0x00001000 -#define CHIP_REV_Cx 0x00002000 - -#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0) -#define CHIP_BONDING(bp) (((bp)->chip_id) & 0x0000000f) - -#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0) -#define CHIP_ID_5706_A0 0x57060000 -#define CHIP_ID_5706_A1 0x57060010 -#define CHIP_ID_5706_A2 0x57060020 -#define CHIP_ID_5708_A0 0x57080000 -#define CHIP_ID_5708_B0 0x57081000 -#define CHIP_ID_5708_B1 0x57081010 -#define CHIP_ID_5709_A0 0x57090000 -#define CHIP_ID_5709_A1 0x57090010 - -#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0xf) +#define BNX2_CHIP(bp) (((bp)->chip_id) & 0xffff0000) +#define BNX2_CHIP_5706 0x57060000 +#define BNX2_CHIP_5708 0x57080000 +#define BNX2_CHIP_5709 0x57090000 + +#define BNX2_CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000) +#define BNX2_CHIP_REV_Ax 0x00000000 +#define BNX2_CHIP_REV_Bx 0x00001000 +#define BNX2_CHIP_REV_Cx 0x00002000 + +#define BNX2_CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0) +#define BNX2_CHIP_BOND(bp) (((bp)->chip_id) & 0x0000000f) + +#define BNX2_CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0) +#define BNX2_CHIP_ID_5706_A0 0x57060000 +#define BNX2_CHIP_ID_5706_A1 0x57060010 +#define BNX2_CHIP_ID_5706_A2 0x57060020 +#define BNX2_CHIP_ID_5708_A0 0x57080000 +#define BNX2_CHIP_ID_5708_B0 0x57081000 +#define BNX2_CHIP_ID_5708_B1 0x57081010 +#define BNX2_CHIP_ID_5709_A0 0x57090000 +#define BNX2_CHIP_ID_5709_A1 0x57090010 /* A serdes chip will have the first bit of the bond id set. */ -#define CHIP_BOND_ID_SERDES_BIT 0x01 +#define BNX2_CHIP_BOND_SERDES_BIT 0x01 u32 phy_addr; u32 phy_id; diff --git a/drivers/net/ethernet/broadcom/cnic.c b/drivers/net/ethernet/broadcom/cnic.c index 756a2a771291..57780986f6cc 100644 --- a/drivers/net/ethernet/broadcom/cnic.c +++ b/drivers/net/ethernet/broadcom/cnic.c @@ -895,7 +895,7 @@ static int cnic_alloc_context(struct cnic_dev *dev) { struct cnic_local *cp = dev->cnic_priv; - if (CHIP_NUM(cp) == CHIP_NUM_5709) { + if (BNX2_CHIP(cp) == BNX2_CHIP_5709) { int i, k, arr_size; cp->ctx_blk_size = BNX2_PAGE_SIZE; @@ -4358,7 +4358,7 @@ static int cnic_setup_5709_context(struct cnic_dev *dev, int valid) int ret = 0, i; u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0; - if (CHIP_NUM(cp) != CHIP_NUM_5709) + if (BNX2_CHIP(cp) != BNX2_CHIP_5709) return 0; for (i = 0; i < cp->ctx_blks; i++) { @@ -4526,7 +4526,7 @@ static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev) cp->tx_cons = *cp->tx_cons_ptr; cid_addr = GET_CID_ADDR(tx_cid); - if (CHIP_NUM(cp) == CHIP_NUM_5709) { + if (BNX2_CHIP(cp) == BNX2_CHIP_5709) { u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40; for (i = 0; i < PHY_CTX_SIZE; i += 4) @@ -4671,7 +4671,7 @@ static void cnic_set_bnx2_mac(struct cnic_dev *dev) CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val); val = 4 | BNX2_RPM_SORT_USER2_BC_EN; - if (CHIP_NUM(cp) != CHIP_NUM_5709) + if (BNX2_CHIP(cp) != BNX2_CHIP_5709) val |= BNX2_RPM_SORT_USER2_PROM_VLAN; CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0); @@ -4717,7 +4717,7 @@ static int cnic_start_bnx2_hw(struct cnic_dev *dev) cp->kwq_con_idx = 0; set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags); - if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708) + if (BNX2_CHIP(cp) == BNX2_CHIP_5706 || BNX2_CHIP(cp) == BNX2_CHIP_5708) cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15; else cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index; @@ -4917,9 +4917,9 @@ static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev, if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) pbd_e2->parsing_data = (UNICAST_ADDRESS << - ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT); + ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT); else - pbd_e1x->global_data = (UNICAST_ADDRESS << + pbd_e1x->global_data = (UNICAST_ADDRESS << ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT); } -- cgit v1.2.3 From 4bd9b0fffb193d2e288f67f81821af32df8d4349 Mon Sep 17 00:00:00 2001 From: Michael Chan Date: Thu, 6 Dec 2012 10:33:12 +0000 Subject: cnic, bnx2x, bnx2: Simplify cnic probing. Instead of using symbol_get(), cnic can now directly call the cnic_probe functions in struct bnx2x and struct bnx2. symbol_get() is not reliable as it fails when the module is still initializing. Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/ethernet/broadcom/bnx2.c | 2 +- drivers/net/ethernet/broadcom/bnx2.h | 1 + drivers/net/ethernet/broadcom/bnx2x/bnx2x.h | 1 + drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | 4 +++- drivers/net/ethernet/broadcom/cnic.c | 21 +++++++++------------ drivers/net/ethernet/broadcom/cnic_if.h | 7 ++----- 6 files changed, 17 insertions(+), 19 deletions(-) (limited to 'drivers/net/ethernet/broadcom/bnx2.c') diff --git a/drivers/net/ethernet/broadcom/bnx2.c b/drivers/net/ethernet/broadcom/bnx2.c index a9b2feaf2879..c16526d3046f 100644 --- a/drivers/net/ethernet/broadcom/bnx2.c +++ b/drivers/net/ethernet/broadcom/bnx2.c @@ -434,7 +434,6 @@ struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev) return cp; } -EXPORT_SYMBOL(bnx2_cnic_probe); static void bnx2_cnic_stop(struct bnx2 *bp) @@ -8422,6 +8421,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) bp->cnic_eth_dev.max_iscsi_conn = (bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) & BNX2_ISCSI_MAX_CONN_MASK) >> BNX2_ISCSI_MAX_CONN_SHIFT; + bp->cnic_probe = bnx2_cnic_probe; #endif pci_save_state(pdev); diff --git a/drivers/net/ethernet/broadcom/bnx2.h b/drivers/net/ethernet/broadcom/bnx2.h index 38a640df58f7..172efbecfea2 100644 --- a/drivers/net/ethernet/broadcom/bnx2.h +++ b/drivers/net/ethernet/broadcom/bnx2.h @@ -6984,6 +6984,7 @@ struct bnx2 { #ifdef BCM_CNIC struct mutex cnic_lock; struct cnic_eth_dev cnic_eth_dev; + struct cnic_eth_dev *(*cnic_probe)(struct net_device *); #endif const struct firmware *mips_firmware; diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h index 02ea644573ca..defa7d647126 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h @@ -1337,6 +1337,7 @@ struct bnx2x { u8 cnic_support; bool cnic_enabled; bool cnic_loaded; + struct cnic_eth_dev *(*cnic_probe)(struct net_device *); /* Flag that indicates that we can start looking for FCoE L2 queue * completions in the default status block. diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c index 75aea83ee68d..f34ff59a8095 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c @@ -12018,6 +12018,8 @@ static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, return control & PCI_MSIX_FLAGS_QSIZE; } +struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *); + static int bnx2x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) { @@ -12097,6 +12099,7 @@ static int bnx2x_init_one(struct pci_dev *pdev, bp->igu_sb_cnt = max_non_def_sbs; bp->msg_enable = debug; bp->cnic_support = cnic_cnt; + bp->cnic_probe = bnx2x_cnic_probe; pci_set_drvdata(pdev, dev); @@ -13038,6 +13041,5 @@ struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) cp->starting_cid); return cp; } -EXPORT_SYMBOL(bnx2x_cnic_probe); diff --git a/drivers/net/ethernet/broadcom/cnic.c b/drivers/net/ethernet/broadcom/cnic.c index b8650939a4be..df8c30d1a52c 100644 --- a/drivers/net/ethernet/broadcom/cnic.c +++ b/drivers/net/ethernet/broadcom/cnic.c @@ -40,6 +40,7 @@ #include #include +#define BCM_CNIC 1 #include "cnic_if.h" #include "bnx2.h" #include "bnx2x/bnx2x.h" @@ -5449,14 +5450,12 @@ static struct cnic_dev *init_bnx2_cnic(struct net_device *dev) struct pci_dev *pdev; struct cnic_dev *cdev; struct cnic_local *cp; + struct bnx2 *bp = netdev_priv(dev); struct cnic_eth_dev *ethdev = NULL; - struct cnic_eth_dev *(*probe)(struct net_device *) = NULL; - probe = symbol_get(bnx2_cnic_probe); - if (probe) { - ethdev = (*probe)(dev); - symbol_put(bnx2_cnic_probe); - } + if (bp->cnic_probe) + ethdev = (bp->cnic_probe)(dev); + if (!ethdev) return NULL; @@ -5511,14 +5510,12 @@ static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev) struct pci_dev *pdev; struct cnic_dev *cdev; struct cnic_local *cp; + struct bnx2x *bp = netdev_priv(dev); struct cnic_eth_dev *ethdev = NULL; - struct cnic_eth_dev *(*probe)(struct net_device *) = NULL; - probe = symbol_get(bnx2x_cnic_probe); - if (probe) { - ethdev = (*probe)(dev); - symbol_put(bnx2x_cnic_probe); - } + if (bp->cnic_probe) + ethdev = bp->cnic_probe(dev); + if (!ethdev) return NULL; diff --git a/drivers/net/ethernet/broadcom/cnic_if.h b/drivers/net/ethernet/broadcom/cnic_if.h index 502e11ef6373..2a35436f9095 100644 --- a/drivers/net/ethernet/broadcom/cnic_if.h +++ b/drivers/net/ethernet/broadcom/cnic_if.h @@ -14,8 +14,8 @@ #include "bnx2x/bnx2x_mfw_req.h" -#define CNIC_MODULE_VERSION "2.5.15" -#define CNIC_MODULE_RELDATE "Dec 04, 2012" +#define CNIC_MODULE_VERSION "2.5.16" +#define CNIC_MODULE_RELDATE "Dec 05, 2012" #define CNIC_ULP_RDMA 0 #define CNIC_ULP_ISCSI 1 @@ -353,7 +353,4 @@ extern int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops); extern int cnic_unregister_driver(int ulp_type); -extern struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev); -extern struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev); - #endif -- cgit v1.2.3 From fda4d85d6124134dd7c72d6559bd275732eb39b9 Mon Sep 17 00:00:00 2001 From: Michael Chan Date: Tue, 11 Dec 2012 18:24:20 -0800 Subject: bnx2: Fix accidental reversions. Commit 4ce45e02469c382699f4c5f6df727aea9dd2e1ca "bnx2: Add BNX2 prefix to CHIP ID and name macros" accidentally reverted 2 commits to use pci_ioumap() and to make pci_error_handlers const. This fixes those mistakes. Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/ethernet/broadcom/bnx2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/net/ethernet/broadcom/bnx2.c') diff --git a/drivers/net/ethernet/broadcom/bnx2.c b/drivers/net/ethernet/broadcom/bnx2.c index c16526d3046f..a1adfaf87f49 100644 --- a/drivers/net/ethernet/broadcom/bnx2.c +++ b/drivers/net/ethernet/broadcom/bnx2.c @@ -8572,7 +8572,7 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) return 0; error: - iounmap(bp->regview); + pci_iounmap(pdev, bp->regview); pci_release_regions(pdev); pci_disable_device(pdev); pci_set_drvdata(pdev, NULL); @@ -8750,7 +8750,7 @@ static void bnx2_io_resume(struct pci_dev *pdev) rtnl_unlock(); } -static struct pci_error_handlers bnx2_err_handler = { +static const struct pci_error_handlers bnx2_err_handler = { .error_detected = bnx2_io_error_detected, .slot_reset = bnx2_io_slot_reset, .resume = bnx2_io_resume, -- cgit v1.2.3