From ba228ac8f512c9cd09cb4245c424ab1632da0c24 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 23 Dec 2015 11:25:43 -0500 Subject: drm/amdgpu/cgs: add an interface to access PCI resources MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This provides an interface to get access to the base address of PCI resources (MMIO, DOORBELL, etc.). Only MMIO and DOORBELL are implemented right now. This is necessary to properly utilize shared drivers on platform devices. IP modules can use this interface to get the base address of the resource and add any additional offset and set the size when setting up the platform driver(s). Acked-by: Dave Airlie Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 36 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/amd/include/cgs_common.h | 34 ++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index 59485d0b3cfb..a081dda9fa2f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -398,6 +398,41 @@ static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr, WARN(ret, "pci_write_config_dword error"); } + +static int amdgpu_cgs_get_pci_resource(void *cgs_device, + enum cgs_resource_type resource_type, + uint64_t size, + uint64_t offset, + uint64_t *resource_base) +{ + CGS_FUNC_ADEV; + + if (resource_base == NULL) + return -EINVAL; + + switch (resource_type) { + case CGS_RESOURCE_TYPE_MMIO: + if (adev->rmmio_size == 0) + return -ENOENT; + if ((offset + size) > adev->rmmio_size) + return -EINVAL; + *resource_base = adev->rmmio_base; + return 0; + case CGS_RESOURCE_TYPE_DOORBELL: + if (adev->doorbell.size == 0) + return -ENOENT; + if ((offset + size) > adev->doorbell.size) + return -EINVAL; + *resource_base = adev->doorbell.base; + return 0; + case CGS_RESOURCE_TYPE_FB: + case CGS_RESOURCE_TYPE_IO: + case CGS_RESOURCE_TYPE_ROM: + default: + return -EINVAL; + } +} + static const void *amdgpu_cgs_atom_get_data_table(void *cgs_device, unsigned table, uint16_t *size, uint8_t *frev, uint8_t *crev) @@ -1041,6 +1076,7 @@ static const struct cgs_ops amdgpu_cgs_ops = { amdgpu_cgs_write_pci_config_byte, amdgpu_cgs_write_pci_config_word, amdgpu_cgs_write_pci_config_dword, + amdgpu_cgs_get_pci_resource, amdgpu_cgs_atom_get_data_table, amdgpu_cgs_atom_get_cmd_table_revs, amdgpu_cgs_atom_exec_cmd_table, diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h index 03affb348f69..713aec954692 100644 --- a/drivers/gpu/drm/amd/include/cgs_common.h +++ b/drivers/gpu/drm/amd/include/cgs_common.h @@ -122,6 +122,17 @@ struct cgs_system_info { uint64_t padding[13]; }; +/* + * enum cgs_resource_type - GPU resource type + */ +enum cgs_resource_type { + CGS_RESOURCE_TYPE_MMIO = 0, + CGS_RESOURCE_TYPE_FB, + CGS_RESOURCE_TYPE_IO, + CGS_RESOURCE_TYPE_DOORBELL, + CGS_RESOURCE_TYPE_ROM, +}; + /** * struct cgs_clock_limits - Clock limits * @@ -417,6 +428,23 @@ typedef void (*cgs_write_pci_config_word_t)(void *cgs_device, unsigned addr, typedef void (*cgs_write_pci_config_dword_t)(void *cgs_device, unsigned addr, uint32_t value); + +/** + * cgs_get_pci_resource() - provide access to a device resource (PCI BAR) + * @cgs_device: opaque device handle + * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL) + * @size: size of the region + * @offset: offset from the start of the region + * @resource_base: base address (not including offset) returned + * + * Return: 0 on success, -errno otherwise + */ +typedef int (*cgs_get_pci_resource_t)(void *cgs_device, + enum cgs_resource_type resource_type, + uint64_t size, + uint64_t offset, + uint64_t *resource_base); + /** * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table * @cgs_device: opaque device handle @@ -593,6 +621,8 @@ struct cgs_ops { cgs_write_pci_config_byte_t write_pci_config_byte; cgs_write_pci_config_word_t write_pci_config_word; cgs_write_pci_config_dword_t write_pci_config_dword; + /* PCI resources */ + cgs_get_pci_resource_t get_pci_resource; /* ATOM BIOS */ cgs_atom_get_data_table_t atom_get_data_table; cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs; @@ -708,5 +738,9 @@ struct cgs_device CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) #define cgs_query_system_info(dev, sys_info) \ CGS_CALL(query_system_info, dev, sys_info) +#define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \ + resource_base) \ + CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \ + resource_base) #endif /* _CGS_COMMON_H */ -- cgit v1.2.3 From 5f2323658e4829ffb893553297e64795a90cbcd9 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 6 Nov 2015 01:29:08 -0500 Subject: drm/amdgpu: add irq domain support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hardware blocks on the GPU like ACP generate interrupts in the GPU interrupt controller, but are driven by a separate driver. Add an irq domain to the GPU driver so that blocks like ACP can register a Linux interrupt. Acked-by: Dave Airlie Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 108 +++++++++++++++++++++++++++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 9 +++ drivers/gpu/drm/amd/amdgpu/cik_ih.c | 6 ++ drivers/gpu/drm/amd/amdgpu/cz_ih.c | 7 +++ drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 7 +++ drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 7 +++ 6 files changed, 136 insertions(+), 8 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 7c42ff670080..3006182c5d0d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -312,6 +312,7 @@ int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id, } adev->irq.sources[src_id] = source; + return 0; } @@ -335,15 +336,19 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev, return; } - src = adev->irq.sources[src_id]; - if (!src) { - DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id); - return; - } + if (adev->irq.virq[src_id]) { + generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id)); + } else { + src = adev->irq.sources[src_id]; + if (!src) { + DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id); + return; + } - r = src->funcs->process(adev, src, entry); - if (r) - DRM_ERROR("error processing interrupt (%d)\n", r); + r = src->funcs->process(adev, src, entry); + if (r) + DRM_ERROR("error processing interrupt (%d)\n", r); + } } /** @@ -461,3 +466,90 @@ bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, return !!atomic_read(&src->enabled_types[type]); } + +/* gen irq */ +static void amdgpu_irq_mask(struct irq_data *irqd) +{ + /* XXX */ +} + +static void amdgpu_irq_unmask(struct irq_data *irqd) +{ + /* XXX */ +} + +static struct irq_chip amdgpu_irq_chip = { + .name = "amdgpu-ih", + .irq_mask = amdgpu_irq_mask, + .irq_unmask = amdgpu_irq_unmask, +}; + +static int amdgpu_irqdomain_map(struct irq_domain *d, + unsigned int irq, irq_hw_number_t hwirq) +{ + if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID) + return -EPERM; + + irq_set_chip_and_handler(irq, + &amdgpu_irq_chip, handle_simple_irq); + return 0; +} + +static struct irq_domain_ops amdgpu_hw_irqdomain_ops = { + .map = amdgpu_irqdomain_map, +}; + +/** + * amdgpu_irq_add_domain - create a linear irq domain + * + * @adev: amdgpu device pointer + * + * Create an irq domain for GPU interrupt sources + * that may be driven by another driver (e.g., ACP). + */ +int amdgpu_irq_add_domain(struct amdgpu_device *adev) +{ + adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID, + &amdgpu_hw_irqdomain_ops, adev); + if (!adev->irq.domain) { + DRM_ERROR("GPU irq add domain failed\n"); + return -ENODEV; + } + + return 0; +} + +/** + * amdgpu_irq_remove_domain - remove the irq domain + * + * @adev: amdgpu device pointer + * + * Remove the irq domain for GPU interrupt sources + * that may be driven by another driver (e.g., ACP). + */ +void amdgpu_irq_remove_domain(struct amdgpu_device *adev) +{ + if (adev->irq.domain) { + irq_domain_remove(adev->irq.domain); + adev->irq.domain = NULL; + } +} + +/** + * amdgpu_irq_create_mapping - create a mapping between a domain irq and a + * Linux irq + * + * @adev: amdgpu device pointer + * @src_id: IH source id + * + * Create a mapping between a domain irq (GPU IH src id) and a Linux irq + * Use this for components that generate a GPU interrupt, but are driven + * by a different driver (e.g., ACP). + * Returns the Linux irq. + */ +unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id) +{ + adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id); + + return adev->irq.virq[src_id]; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h index 17b01aef4278..e124b59f39c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h @@ -24,6 +24,7 @@ #ifndef __AMDGPU_IRQ_H__ #define __AMDGPU_IRQ_H__ +#include #include "amdgpu_ih.h" #define AMDGPU_MAX_IRQ_SRC_ID 0x100 @@ -65,6 +66,10 @@ struct amdgpu_irq { /* interrupt ring */ struct amdgpu_ih_ring ih; const struct amdgpu_ih_funcs *ih_funcs; + + /* gen irq stuff */ + struct irq_domain *domain; /* GPU irq controller domain */ + unsigned virq[AMDGPU_MAX_IRQ_SRC_ID]; }; void amdgpu_irq_preinstall(struct drm_device *dev); @@ -90,4 +95,8 @@ int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type); +int amdgpu_irq_add_domain(struct amdgpu_device *adev); +void amdgpu_irq_remove_domain(struct amdgpu_device *adev); +unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id); + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c index 8993c50cb89f..30c9b3beeef9 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c @@ -274,6 +274,11 @@ static void cik_ih_set_rptr(struct amdgpu_device *adev) static int cik_ih_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int ret; + + ret = amdgpu_irq_add_domain(adev); + if (ret) + return ret; cik_ih_set_interrupt_funcs(adev); @@ -300,6 +305,7 @@ static int cik_ih_sw_fini(void *handle) amdgpu_irq_fini(adev); amdgpu_ih_ring_fini(adev); + amdgpu_irq_remove_domain(adev); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c index bc751bfbcae2..c79638f8e732 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c @@ -253,8 +253,14 @@ static void cz_ih_set_rptr(struct amdgpu_device *adev) static int cz_ih_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int ret; + + ret = amdgpu_irq_add_domain(adev); + if (ret) + return ret; cz_ih_set_interrupt_funcs(adev); + return 0; } @@ -278,6 +284,7 @@ static int cz_ih_sw_fini(void *handle) amdgpu_irq_fini(adev); amdgpu_ih_ring_fini(adev); + amdgpu_irq_remove_domain(adev); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c index 779532d350ff..679e7394a495 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c @@ -253,8 +253,14 @@ static void iceland_ih_set_rptr(struct amdgpu_device *adev) static int iceland_ih_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int ret; + + ret = amdgpu_irq_add_domain(adev); + if (ret) + return ret; iceland_ih_set_interrupt_funcs(adev); + return 0; } @@ -278,6 +284,7 @@ static int iceland_ih_sw_fini(void *handle) amdgpu_irq_fini(adev); amdgpu_ih_ring_fini(adev); + amdgpu_irq_remove_domain(adev); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index 743c372837aa..b6f7d7bff929 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -273,8 +273,14 @@ static void tonga_ih_set_rptr(struct amdgpu_device *adev) static int tonga_ih_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int ret; + + ret = amdgpu_irq_add_domain(adev); + if (ret) + return ret; tonga_ih_set_interrupt_funcs(adev); + return 0; } @@ -301,6 +307,7 @@ static int tonga_ih_sw_fini(void *handle) amdgpu_irq_fini(adev); amdgpu_ih_ring_fini(adev); + amdgpu_irq_add_domain(adev); return 0; } -- cgit v1.2.3 From f3b5cb3e68952d4a721cc733e03eeb5151dcaa1e Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Mon, 11 Jan 2016 11:25:18 +0800 Subject: drm/amd/powerplay: fix static checker warning for return meaningless value. The return value should be either negative or zero, no positive. Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c index d166fd925dbb..ebdb43a8daef 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c @@ -199,7 +199,7 @@ static int tonga_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) PP_ASSERT_WITH_CODE( 1 == SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP), "Failed to send Previous Message.", - return 1); + ); cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg); @@ -207,7 +207,7 @@ static int tonga_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) PP_ASSERT_WITH_CODE( 1 == SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP), "Failed to send Message.", - return 1); + ); return 0; } @@ -229,7 +229,7 @@ static int tonga_send_msg_to_smc_without_waiting PP_ASSERT_WITH_CODE( 1 == SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP), "Failed to send Previous Message.", - return 0); + ); cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg); return 0; -- cgit v1.2.3 From 888c9e33e4c5a503285921046c621f7c73199d2f Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Wed, 13 Jan 2016 12:55:18 +0800 Subject: drm/amdgpu: fix lost sync_to if scheduler is enabled. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit when scheduler is enabled, the semaphore isn't used at all. Signed-off-by: Chunming Zhou Reviewed-by: Christian König Cc: stable@vger.kernel.org --- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index dd005c336c97..181ce39ef5e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -293,7 +293,8 @@ int amdgpu_sync_rings(struct amdgpu_sync *sync, fence = to_amdgpu_fence(sync->sync_to[i]); /* check if we really need to sync */ - if (!amdgpu_fence_need_sync(fence, ring)) + if (!amdgpu_enable_scheduler && + !amdgpu_fence_need_sync(fence, ring)) continue; /* prevent GPU deadlocks */ @@ -303,7 +304,7 @@ int amdgpu_sync_rings(struct amdgpu_sync *sync, } if (amdgpu_enable_scheduler || !amdgpu_enable_semaphores) { - r = fence_wait(&fence->base, true); + r = fence_wait(sync->sync_to[i], true); if (r) return r; continue; -- cgit v1.2.3 From d83b1e8132f91ba9e038b5206dc81d32ecac1f75 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 18 Dec 2015 11:06:42 -0500 Subject: drm/amdgpu/cz: add code to enable forcing UVD clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit UVD DPM works similarly to SCLK DPM. Add a similar interface for UVD for forcing the UVD clocks. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 129 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/cz_dpm.h | 1 + 2 files changed, 130 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c index 8035d4d6a4f5..5ccea9f9c634 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c @@ -1078,6 +1078,37 @@ static uint32_t cz_get_eclk_level(struct amdgpu_device *adev, return i; } +static uint32_t cz_get_uvd_level(struct amdgpu_device *adev, + uint32_t clock, uint16_t msg) +{ + int i = 0; + struct amdgpu_uvd_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; + + switch (msg) { + case PPSMC_MSG_SetUvdSoftMin: + case PPSMC_MSG_SetUvdHardMin: + for (i = 0; i < table->count; i++) + if (clock <= table->entries[i].vclk) + break; + if (i == table->count) + i = table->count - 1; + break; + case PPSMC_MSG_SetUvdSoftMax: + case PPSMC_MSG_SetUvdHardMax: + for (i = table->count - 1; i >= 0; i--) + if (clock >= table->entries[i].vclk) + break; + if (i < 0) + i = 0; + break; + default: + break; + } + + return i; +} + static int cz_program_bootup_state(struct amdgpu_device *adev) { struct cz_power_info *pi = cz_get_pi(adev); @@ -1739,6 +1770,104 @@ static int cz_dpm_unforce_dpm_levels(struct amdgpu_device *adev) return 0; } + +static int cz_dpm_uvd_force_highest(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + int ret = 0; + + if (pi->uvd_dpm.soft_min_clk != pi->uvd_dpm.soft_max_clk) { + pi->uvd_dpm.soft_min_clk = + pi->uvd_dpm.soft_max_clk; + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetUvdSoftMin, + cz_get_uvd_level(adev, + pi->uvd_dpm.soft_min_clk, + PPSMC_MSG_SetUvdSoftMin)); + if (ret) + return ret; + } + + return ret; +} + +static int cz_dpm_uvd_force_lowest(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + int ret = 0; + + if (pi->uvd_dpm.soft_max_clk != pi->uvd_dpm.soft_min_clk) { + pi->uvd_dpm.soft_max_clk = pi->uvd_dpm.soft_min_clk; + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetUvdSoftMax, + cz_get_uvd_level(adev, + pi->uvd_dpm.soft_max_clk, + PPSMC_MSG_SetUvdSoftMax)); + if (ret) + return ret; + } + + return ret; +} + +static uint32_t cz_dpm_get_max_uvd_level(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + + if (!pi->max_uvd_level) { + cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxUvdLevel); + pi->max_uvd_level = cz_get_argument(adev) + 1; + } + + if (pi->max_uvd_level > CZ_MAX_HARDWARE_POWERLEVELS) { + DRM_ERROR("Invalid max uvd level!\n"); + return -EINVAL; + } + + return pi->max_uvd_level; +} + +static int cz_dpm_unforce_uvd_dpm_levels(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + struct amdgpu_uvd_clock_voltage_dependency_table *dep_table = + &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; + uint32_t level = 0; + int ret = 0; + + pi->uvd_dpm.soft_min_clk = dep_table->entries[0].vclk; + level = cz_dpm_get_max_uvd_level(adev) - 1; + if (level < dep_table->count) + pi->uvd_dpm.soft_max_clk = dep_table->entries[level].vclk; + else + pi->uvd_dpm.soft_max_clk = + dep_table->entries[dep_table->count - 1].vclk; + + /* get min/max sclk soft value + * notify SMU to execute */ + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetUvdSoftMin, + cz_get_uvd_level(adev, + pi->uvd_dpm.soft_min_clk, + PPSMC_MSG_SetUvdSoftMin)); + if (ret) + return ret; + + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetUvdSoftMax, + cz_get_uvd_level(adev, + pi->uvd_dpm.soft_max_clk, + PPSMC_MSG_SetUvdSoftMax)); + if (ret) + return ret; + + DRM_DEBUG("DPM uvd unforce state min=%d, max=%d.\n", + pi->uvd_dpm.soft_min_clk, + pi->uvd_dpm.soft_max_clk); + + return 0; +} + static int cz_dpm_force_dpm_level(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level) { diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.h b/drivers/gpu/drm/amd/amdgpu/cz_dpm.h index 99e1afc89629..6a6a6fe7967f 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.h @@ -183,6 +183,7 @@ struct cz_power_info { uint32_t voltage_drop_threshold; uint32_t gfx_pg_threshold; uint32_t max_sclk_level; + uint32_t max_uvd_level; /* flags */ bool didt_enabled; bool video_start; -- cgit v1.2.3 From 044c0629b55d73235161557a48870d663d0072f5 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 18 Dec 2015 11:25:16 -0500 Subject: drm/amdgpu/cz: add code to enable forcing VCE clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit VCE DPM works similarly to SCLK DPM. Add a similar interface for VCE for forcing the VCE clocks. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 98 ++++++++++++++++++++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/cz_dpm.h | 1 + 2 files changed, 98 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c index 5ccea9f9c634..02cba49f13a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c @@ -1770,7 +1770,6 @@ static int cz_dpm_unforce_dpm_levels(struct amdgpu_device *adev) return 0; } - static int cz_dpm_uvd_force_highest(struct amdgpu_device *adev) { struct cz_power_info *pi = cz_get_pi(adev); @@ -1868,6 +1867,103 @@ static int cz_dpm_unforce_uvd_dpm_levels(struct amdgpu_device *adev) return 0; } +static int cz_dpm_vce_force_highest(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + int ret = 0; + + if (pi->vce_dpm.soft_min_clk != pi->vce_dpm.soft_max_clk) { + pi->vce_dpm.soft_min_clk = + pi->vce_dpm.soft_max_clk; + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetEclkSoftMin, + cz_get_eclk_level(adev, + pi->vce_dpm.soft_min_clk, + PPSMC_MSG_SetEclkSoftMin)); + if (ret) + return ret; + } + + return ret; +} + +static int cz_dpm_vce_force_lowest(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + int ret = 0; + + if (pi->vce_dpm.soft_max_clk != pi->vce_dpm.soft_min_clk) { + pi->vce_dpm.soft_max_clk = pi->vce_dpm.soft_min_clk; + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetEclkSoftMax, + cz_get_uvd_level(adev, + pi->vce_dpm.soft_max_clk, + PPSMC_MSG_SetEclkSoftMax)); + if (ret) + return ret; + } + + return ret; +} + +static uint32_t cz_dpm_get_max_vce_level(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + + if (!pi->max_vce_level) { + cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxEclkLevel); + pi->max_vce_level = cz_get_argument(adev) + 1; + } + + if (pi->max_vce_level > CZ_MAX_HARDWARE_POWERLEVELS) { + DRM_ERROR("Invalid max vce level!\n"); + return -EINVAL; + } + + return pi->max_vce_level; +} + +static int cz_dpm_unforce_vce_dpm_levels(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + struct amdgpu_vce_clock_voltage_dependency_table *dep_table = + &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; + uint32_t level = 0; + int ret = 0; + + pi->vce_dpm.soft_min_clk = dep_table->entries[0].ecclk; + level = cz_dpm_get_max_vce_level(adev) - 1; + if (level < dep_table->count) + pi->vce_dpm.soft_max_clk = dep_table->entries[level].ecclk; + else + pi->vce_dpm.soft_max_clk = + dep_table->entries[dep_table->count - 1].ecclk; + + /* get min/max sclk soft value + * notify SMU to execute */ + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetEclkSoftMin, + cz_get_eclk_level(adev, + pi->vce_dpm.soft_min_clk, + PPSMC_MSG_SetEclkSoftMin)); + if (ret) + return ret; + + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetEclkSoftMax, + cz_get_eclk_level(adev, + pi->vce_dpm.soft_max_clk, + PPSMC_MSG_SetEclkSoftMax)); + if (ret) + return ret; + + DRM_DEBUG("DPM vce unforce state min=%d, max=%d.\n", + pi->vce_dpm.soft_min_clk, + pi->vce_dpm.soft_max_clk); + + return 0; +} + static int cz_dpm_force_dpm_level(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level) { diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.h b/drivers/gpu/drm/amd/amdgpu/cz_dpm.h index 6a6a6fe7967f..5df8c1faab51 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.h @@ -184,6 +184,7 @@ struct cz_power_info { uint32_t gfx_pg_threshold; uint32_t max_sclk_level; uint32_t max_uvd_level; + uint32_t max_vce_level; /* flags */ bool didt_enabled; bool video_start; -- cgit v1.2.3 From 5f57642672dd90e3183efcd9e6afbff1305a133a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 18 Dec 2015 11:28:49 -0500 Subject: drm/amdgpu/cz: force uvd clocks when sclks are forced MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c index 02cba49f13a8..bdf5a22ba450 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c @@ -1971,23 +1971,47 @@ static int cz_dpm_force_dpm_level(struct amdgpu_device *adev, switch (level) { case AMDGPU_DPM_FORCED_LEVEL_HIGH: + /* sclk */ ret = cz_dpm_unforce_dpm_levels(adev); if (ret) return ret; ret = cz_dpm_force_highest(adev); + if (ret) + return ret; + + /* uvd */ + ret = cz_dpm_unforce_uvd_dpm_levels(adev); + if (ret) + return ret; + ret = cz_dpm_uvd_force_highest(adev); if (ret) return ret; break; case AMDGPU_DPM_FORCED_LEVEL_LOW: + /* sclk */ ret = cz_dpm_unforce_dpm_levels(adev); if (ret) return ret; ret = cz_dpm_force_lowest(adev); + if (ret) + return ret; + + /* uvd */ + ret = cz_dpm_unforce_uvd_dpm_levels(adev); + if (ret) + return ret; + ret = cz_dpm_uvd_force_lowest(adev); if (ret) return ret; break; case AMDGPU_DPM_FORCED_LEVEL_AUTO: + /* sclk */ ret = cz_dpm_unforce_dpm_levels(adev); + if (ret) + return ret; + + /* uvd */ + ret = cz_dpm_unforce_uvd_dpm_levels(adev); if (ret) return ret; break; -- cgit v1.2.3 From 403664bbf840e80a45c4b97115ac518b40487f91 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 18 Dec 2015 11:33:30 -0500 Subject: drm/amdgpu/cz: force vce clocks when sclks are forced MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c index bdf5a22ba450..4dd17f2dd905 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c @@ -1984,6 +1984,14 @@ static int cz_dpm_force_dpm_level(struct amdgpu_device *adev, if (ret) return ret; ret = cz_dpm_uvd_force_highest(adev); + if (ret) + return ret; + + /* vce */ + ret = cz_dpm_unforce_vce_dpm_levels(adev); + if (ret) + return ret; + ret = cz_dpm_vce_force_highest(adev); if (ret) return ret; break; @@ -2001,6 +2009,14 @@ static int cz_dpm_force_dpm_level(struct amdgpu_device *adev, if (ret) return ret; ret = cz_dpm_uvd_force_lowest(adev); + if (ret) + return ret; + + /* vce */ + ret = cz_dpm_unforce_vce_dpm_levels(adev); + if (ret) + return ret; + ret = cz_dpm_vce_force_lowest(adev); if (ret) return ret; break; @@ -2012,6 +2028,11 @@ static int cz_dpm_force_dpm_level(struct amdgpu_device *adev, /* uvd */ ret = cz_dpm_unforce_uvd_dpm_levels(adev); + if (ret) + return ret; + + /* vce */ + ret = cz_dpm_unforce_vce_dpm_levels(adev); if (ret) return ret; break; @@ -2154,7 +2175,8 @@ static int cz_update_vce_dpm(struct amdgpu_device *adev) pi->vce_dpm.hard_min_clk = table->entries[table->count-1].ecclk; } else { /* non-stable p-state cases. without vce.Arbiter.EcclkHardMin */ - pi->vce_dpm.hard_min_clk = table->entries[0].ecclk; + /* leave it as set by user */ + /*pi->vce_dpm.hard_min_clk = table->entries[0].ecclk;*/ } cz_send_msg_to_smc_with_parameter(adev, -- cgit v1.2.3 From cc29ec874b3727e3f5a606bd1875e34f6e3f1593 Mon Sep 17 00:00:00 2001 From: Geliang Tang Date: Wed, 13 Jan 2016 22:48:42 +0800 Subject: drm/amdgpu: use kobj_to_dev() Use kobj_to_dev() instead of open-coding it. Signed-off-by: Geliang Tang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 4386cbac7f97..7d8d84eaea4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -326,7 +326,7 @@ static struct attribute *hwmon_attributes[] = { static umode_t hwmon_attributes_visible(struct kobject *kobj, struct attribute *attr, int index) { - struct device *dev = container_of(kobj, struct device, kobj); + struct device *dev = kobj_to_dev(kobj); struct amdgpu_device *adev = dev_get_drvdata(dev); umode_t effective_mode = attr->mode; -- cgit v1.2.3 From e3837b00b6bb2b0344dd28c601edda8eba42de7f Mon Sep 17 00:00:00 2001 From: Geliang Tang Date: Wed, 13 Jan 2016 22:48:43 +0800 Subject: drm/radeon: use kobj_to_dev() Use kobj_to_dev() instead of open-coding it. Signed-off-by: Geliang Tang Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 59abebd6b5dc..460c8f2989da 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -713,7 +713,7 @@ static struct attribute *hwmon_attributes[] = { static umode_t hwmon_attributes_visible(struct kobject *kobj, struct attribute *attr, int index) { - struct device *dev = container_of(kobj, struct device, kobj); + struct device *dev = kobj_to_dev(kobj); struct radeon_device *rdev = dev_get_drvdata(dev); umode_t effective_mode = attr->mode; -- cgit v1.2.3 From 33d48cf8256f2b72e4082a7996c04bf1e78fce81 Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 11 Jan 2016 15:35:18 +0100 Subject: drm/ttm: fix adding foreign BOs to the LRU during init v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If we import a BO with an external reservation object we don't reserve/unreserve it. So we never add it to the LRU causing a possible denial of service. v2: fix typo in commit message Reviewed-by: Thomas Hellstrom Signed-off-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_bo.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 745e996d2dbc..a98a5d5d756d 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -1170,9 +1170,15 @@ int ttm_bo_init(struct ttm_bo_device *bdev, if (likely(!ret)) ret = ttm_bo_validate(bo, placement, interruptible, false); - if (!resv) + if (!resv) { ttm_bo_unreserve(bo); + } else if (!(bo->mem.placement & TTM_PL_FLAG_NO_EVICT)) { + spin_lock(&bo->glob->lru_lock); + ttm_bo_add_to_lru(bo); + spin_unlock(&bo->glob->lru_lock); + } + if (unlikely(ret)) ttm_bo_unref(&bo); -- cgit v1.2.3 From ed704a43e84cc536081423dcd3491acf2791aaeb Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 11 Jan 2016 15:35:19 +0100 Subject: drm/ttm: fix adding foreign BOs to the swap LRU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It doesn't make any sense to try to swap out imported BOs. Reviewed-by: Thomas Hellstrom Signed-off-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_bo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index a98a5d5d756d..3ea9a01c960c 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -176,7 +176,7 @@ void ttm_bo_add_to_lru(struct ttm_buffer_object *bo) list_add_tail(&bo->lru, &man->lru); kref_get(&bo->list_kref); - if (bo->ttm != NULL) { + if (bo->ttm && !(bo->ttm->page_flags & TTM_PAGE_FLAG_SG)) { list_add_tail(&bo->swap, &bo->glob->swap_lru); kref_get(&bo->list_kref); } -- cgit v1.2.3 From ab74961810ba7935b5f9643da10daaa36690f48e Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 11 Jan 2016 15:35:20 +0100 Subject: drm/ttm: add ttm_bo_move_to_lru_tail function v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows the drivers to move a BO to the end of the LRU without removing and adding it again. v2: Make it more robust, handle pinned and swapable BOs as well. Reviewed-by: Thomas Hellstrom Signed-off-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_bo.c | 21 +++++++++++++++++++++ include/drm/ttm/ttm_bo_api.h | 10 ++++++++++ 2 files changed, 31 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 3ea9a01c960c..4cbf26555093 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -228,6 +228,27 @@ void ttm_bo_del_sub_from_lru(struct ttm_buffer_object *bo) } EXPORT_SYMBOL(ttm_bo_del_sub_from_lru); +void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo) +{ + struct ttm_bo_device *bdev = bo->bdev; + struct ttm_mem_type_manager *man; + + lockdep_assert_held(&bo->resv->lock.base); + + if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT) { + list_del_init(&bo->swap); + list_del_init(&bo->lru); + + } else { + if (bo->ttm && !(bo->ttm->page_flags & TTM_PAGE_FLAG_SG)) + list_move_tail(&bo->swap, &bo->glob->swap_lru); + + man = &bdev->man[bo->mem.mem_type]; + list_move_tail(&bo->lru, &man->lru); + } +} +EXPORT_SYMBOL(ttm_bo_move_to_lru_tail); + /* * Call bo->mutex locked. */ diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h index c768ddfbe53c..afae2316bd43 100644 --- a/include/drm/ttm/ttm_bo_api.h +++ b/include/drm/ttm/ttm_bo_api.h @@ -383,6 +383,16 @@ extern void ttm_bo_add_to_lru(struct ttm_buffer_object *bo); */ extern int ttm_bo_del_from_lru(struct ttm_buffer_object *bo); +/** + * ttm_bo_move_to_lru_tail + * + * @bo: The buffer object. + * + * Move this BO to the tail of all lru lists used to lookup and reserve an + * object. This function must be called with struct ttm_bo_global::lru_lock + * held, and is used to make a BO less likely to be considered for eviction. + */ +extern void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo); /** * ttm_bo_lock_delayed_workqueue -- cgit v1.2.3 From eceb8a1562db6fc3e1c21cd54a4be0189aa1d0e3 Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 11 Jan 2016 15:35:21 +0100 Subject: drm/amdgpu: move VM page tables to the LRU end on CS v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes it less likely to run into an ENOMEM because VM page tables are evicted last. v2: move the BOs in the LRU tail after validation Signed-off-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 ++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 27 +++++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 003959f99251..313b0cc8d676 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -987,6 +987,8 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, struct list_head *validated, struct amdgpu_bo_list_entry *entry); void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates); +void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, + struct amdgpu_vm *vm); int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, struct amdgpu_sync *sync); void amdgpu_vm_flush(struct amdgpu_ring *ring, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index ce0254d4dcd7..1fffc338f69d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -428,8 +428,10 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p) r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &duplicates); error_validate: - if (r) + if (r) { + amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm); ttm_eu_backoff_reservation(&p->ticket, &p->validated); + } error_reserve: if (need_mmap_lock) @@ -473,8 +475,11 @@ static int cmp_size_smaller_first(void *priv, struct list_head *a, **/ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff) { + struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; unsigned i; + amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm); + if (!error) { /* Sort the buffer list from the smallest to largest buffer, * which affects the order of buffers in the LRU list. diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 8f7688e598a1..aefc668e6b5d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -119,6 +119,33 @@ void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates) list_add(&entry->tv.head, duplicates); } + +} + +/** + * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail + * + * @adev: amdgpu device instance + * @vm: vm providing the BOs + * + * Move the PT BOs to the tail of the LRU. + */ +void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, + struct amdgpu_vm *vm) +{ + struct ttm_bo_global *glob = adev->mman.bdev.glob; + unsigned i; + + spin_lock(&glob->lru_lock); + for (i = 0; i <= vm->max_pde_used; ++i) { + struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; + + if (!entry->robj) + continue; + + ttm_bo_move_to_lru_tail(&entry->robj->tbo); + } + spin_unlock(&glob->lru_lock); } /** -- cgit v1.2.3 From d8e0cae645504a787b05abfb91afee8cd7fa1701 Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 11 Jan 2016 15:35:22 +0100 Subject: drm/amdgpu: validate duplicates first MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Most VM BOs end up in the duplicates list, validate it first make -ENOMEM less likely. Signed-off-by: Christian König Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 1fffc338f69d..6f89f8e034d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -421,11 +421,11 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p) amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates); - r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &p->validated); + r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &duplicates); if (r) goto error_validate; - r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &duplicates); + r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &p->validated); error_validate: if (r) { -- cgit v1.2.3