From aef13fd8426279fcd9e0b2b5b446d35c0d49ec5d Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 25 Jun 2018 14:02:58 +0200 Subject: drm/sun4i: DW HDMI PHY: Add support for second PLL Some DW HDMI PHYs, like those found in A64 and R40 SoCs, can select between two clock parents. Add code which reads second PLL from DT. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20180625120304.7543-19-jernej.skrabec@siol.net --- drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h') diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h index 3ba71aff92fc..46a3aa6a53a9 100644 --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h @@ -147,6 +147,7 @@ struct sun8i_hdmi_phy; struct sun8i_hdmi_phy_variant { bool has_phy_clk; + bool has_second_pll; void (*phy_init)(struct sun8i_hdmi_phy *phy); void (*phy_disable)(struct dw_hdmi *hdmi, struct sun8i_hdmi_phy *phy); @@ -160,6 +161,7 @@ struct sun8i_hdmi_phy { struct clk *clk_mod; struct clk *clk_phy; struct clk *clk_pll0; + struct clk *clk_pll1; unsigned int rcal; struct regmap *regs; struct reset_control *rst_phy; -- cgit v1.2.3