From 958a6f8ccb1964adc3eec84cf401c5baeb4fbca0 Mon Sep 17 00:00:00 2001 From: David Miller Date: Wed, 18 Feb 2009 01:35:23 -0800 Subject: drm: radeon: Fix unaligned access in r300_scratch(). In compat mode, the cmdbuf->buf 64-bit address cookie can potentially be only 32-bit aligned. Dereferencing this as 64-bit causes expensive unaligned traps on platforms like sparc64. Use get_unaligned() to fix. Signed-off-by: David S. Miller Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r300_cmdbuf.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/radeon/r300_cmdbuf.c') diff --git a/drivers/gpu/drm/radeon/r300_cmdbuf.c b/drivers/gpu/drm/radeon/r300_cmdbuf.c index cace3964feeb..3efa633966e8 100644 --- a/drivers/gpu/drm/radeon/r300_cmdbuf.c +++ b/drivers/gpu/drm/radeon/r300_cmdbuf.c @@ -37,6 +37,8 @@ #include "radeon_drv.h" #include "r300_reg.h" +#include + #define R300_SIMULTANEOUS_CLIPRECTS 4 /* Values for R300_RE_CLIPRECT_CNTL depending on the number of cliprects @@ -917,6 +919,7 @@ static int r300_scratch(drm_radeon_private_t *dev_priv, { u32 *ref_age_base; u32 i, buf_idx, h_pending; + u64 ptr_addr; RING_LOCALS; if (cmdbuf->bufsz < @@ -930,7 +933,8 @@ static int r300_scratch(drm_radeon_private_t *dev_priv, dev_priv->scratch_ages[header.scratch.reg]++; - ref_age_base = (u32 *)(unsigned long)*((uint64_t *)cmdbuf->buf); + ptr_addr = get_unaligned((u64 *)cmdbuf->buf); + ref_age_base = (u32 *)(unsigned long)ptr_addr; cmdbuf->buf += sizeof(u64); cmdbuf->bufsz -= sizeof(u64); -- cgit v1.2.3 From af7ae351ad63a137ece86740dbe3f181d09d810f Mon Sep 17 00:00:00 2001 From: Maciej Cencora Date: Tue, 24 Mar 2009 01:48:50 +0100 Subject: drm/radeon: add regs required for occlusion queries support [airlied: cleaned up slightly for drm-next] Signed-off-by: Maciej Cencora Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/r300_cmdbuf.c | 5 +++++ drivers/gpu/drm/radeon/r300_reg.h | 5 +++++ drivers/gpu/drm/radeon/radeon_cp.c | 2 +- drivers/gpu/drm/radeon/radeon_drv.h | 1 - 4 files changed, 11 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/radeon/r300_cmdbuf.c') diff --git a/drivers/gpu/drm/radeon/r300_cmdbuf.c b/drivers/gpu/drm/radeon/r300_cmdbuf.c index 3efa633966e8..cb2e470f97d4 100644 --- a/drivers/gpu/drm/radeon/r300_cmdbuf.c +++ b/drivers/gpu/drm/radeon/r300_cmdbuf.c @@ -207,6 +207,10 @@ void r300_init_reg_flags(struct drm_device *dev) ADD_RANGE(0x42C0, 2); ADD_RANGE(R300_RS_CNTL_0, 2); + ADD_RANGE(R300_SU_REG_DEST, 1); + if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) + ADD_RANGE(RV530_FG_ZBREG_DEST, 1); + ADD_RANGE(R300_SC_HYPERZ, 2); ADD_RANGE(0x43E8, 1); @@ -232,6 +236,7 @@ void r300_init_reg_flags(struct drm_device *dev) ADD_RANGE(R300_ZB_DEPTHPITCH, 1); ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1); ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13); + ADD_RANGE(R300_ZB_ZPASS_DATA, 2); /* ZB_ZPASS_DATA, ZB_ZPASS_ADDR */ ADD_RANGE(R300_TX_FILTER_0, 16); ADD_RANGE(R300_TX_FILTER1_0, 16); diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h index ee6f811599a3..bdbc95fa6721 100644 --- a/drivers/gpu/drm/radeon/r300_reg.h +++ b/drivers/gpu/drm/radeon/r300_reg.h @@ -1770,4 +1770,9 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define R500_RB3D_COLOR_CLEAR_VALUE_AR 0x46c0 #define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8 +#define R300_SU_REG_DEST 0x42c8 +#define RV530_FG_ZBREG_DEST 0x4be8 +#define R300_ZB_ZPASS_DATA 0x4f58 +#define R300_ZB_ZPASS_ADDR 0x4f5c + #endif /* _R300_REG_H */ diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c index 6f579a8e5349..77a7a4d84650 100644 --- a/drivers/gpu/drm/radeon/radeon_cp.c +++ b/drivers/gpu/drm/radeon/radeon_cp.c @@ -434,7 +434,7 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv) if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); - RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1)); + RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1)); } RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config); radeon_do_wait_for_idle(dev_priv); diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h index 7091aafff196..ed4d27e6ee6f 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.h +++ b/drivers/gpu/drm/radeon/radeon_drv.h @@ -687,7 +687,6 @@ extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pciga /* pipe config regs */ #define R400_GB_PIPE_SELECT 0x402c #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ -#define R500_SU_REG_DEST 0x42c8 #define R300_GB_TILE_CONFIG 0x4018 # define R300_ENABLE_TILING (1 << 0) # define R300_PIPE_COUNT_RV350 (0 << 1) -- cgit v1.2.3