From 0dc9b286b8d2c219a55f6ad05d144aa4da495e97 Mon Sep 17 00:00:00 2001 From: Nirmoy Das Date: Wed, 24 Jun 2020 20:26:44 +0200 Subject: drm/nouveau: don't use ttm bo->offset v3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Store ttm bo->offset in struct nouveau_bo instead. Signed-off-by: Nirmoy Das Acked-by: Christian König Link: https://patchwork.freedesktop.org/patch/372932/ Signed-off-by: Christian König --- drivers/gpu/drm/nouveau/nouveau_dmem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau/nouveau_dmem.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_dmem.c b/drivers/gpu/drm/nouveau/nouveau_dmem.c index ad89e09a0be3..f13086a32f0f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dmem.c +++ b/drivers/gpu/drm/nouveau/nouveau_dmem.c @@ -90,7 +90,7 @@ static unsigned long nouveau_dmem_page_addr(struct page *page) struct nouveau_dmem_chunk *chunk = page->zone_device_data; unsigned long idx = page_to_pfn(page) - chunk->pfn_first; - return (idx << PAGE_SHIFT) + chunk->bo->bo.offset; + return (idx << PAGE_SHIFT) + chunk->bo->offset; } static void nouveau_dmem_page_free(struct page *page) -- cgit v1.2.3 From 71e741ad124d07b15d7f1cd481f98d69867ca0a2 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 19:04:43 +1000 Subject: drm/nouveau/svm: convert migrate_copy to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_dmem.c | 33 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 17 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nouveau_dmem.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_dmem.c b/drivers/gpu/drm/nouveau/nouveau_dmem.c index 462ee0493651..a70dce4469f2 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dmem.c +++ b/drivers/gpu/drm/nouveau/nouveau_dmem.c @@ -29,6 +29,7 @@ #include #include +#include #include #include #include @@ -385,7 +386,7 @@ nvc0b5_migrate_copy(struct nouveau_drm *drm, u64 npages, enum nouveau_aper dst_aper, u64 dst_addr, enum nouveau_aper src_aper, u64 src_addr) { - struct nouveau_channel *chan = drm->dmem->migrate.chan; + struct nvif_push *push = drm->dmem->migrate.chan->chan.push; u32 launch_dma = (1 << 9) /* MULTI_LINE_ENABLE. */ | (1 << 8) /* DST_MEMORY_LAYOUT_PITCH. */ | (1 << 7) /* SRC_MEMORY_LAYOUT_PITCH. */ | @@ -393,17 +394,17 @@ nvc0b5_migrate_copy(struct nouveau_drm *drm, u64 npages, (2 << 0) /* DATA_TRANSFER_TYPE_NON_PIPELINED. */; int ret; - ret = RING_SPACE(chan, 13); + ret = PUSH_WAIT(push, 13); if (ret) return ret; if (src_aper != NOUVEAU_APER_VIRT) { switch (src_aper) { case NOUVEAU_APER_VRAM: - BEGIN_IMC0(chan, NvSubCopy, 0x0260, 0); + PUSH_NVIM(push, NVA0B5, 0x0260, 0); break; case NOUVEAU_APER_HOST: - BEGIN_IMC0(chan, NvSubCopy, 0x0260, 1); + PUSH_NVIM(push, NVA0B5, 0x0260, 1); break; default: return -EINVAL; @@ -414,10 +415,10 @@ nvc0b5_migrate_copy(struct nouveau_drm *drm, u64 npages, if (dst_aper != NOUVEAU_APER_VIRT) { switch (dst_aper) { case NOUVEAU_APER_VRAM: - BEGIN_IMC0(chan, NvSubCopy, 0x0264, 0); + PUSH_NVIM(push, NVA0B5, 0x0264, 0); break; case NOUVEAU_APER_HOST: - BEGIN_IMC0(chan, NvSubCopy, 0x0264, 1); + PUSH_NVIM(push, NVA0B5, 0x0264, 1); break; default: return -EINVAL; @@ -425,17 +426,15 @@ nvc0b5_migrate_copy(struct nouveau_drm *drm, u64 npages, launch_dma |= 0x00002000; /* DST_TYPE_PHYSICAL. */ } - BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); - OUT_RING (chan, upper_32_bits(src_addr)); - OUT_RING (chan, lower_32_bits(src_addr)); - OUT_RING (chan, upper_32_bits(dst_addr)); - OUT_RING (chan, lower_32_bits(dst_addr)); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, npages); - BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); - OUT_RING (chan, launch_dma); + PUSH_NVSQ(push, NVA0B5, 0x0400, upper_32_bits(src_addr), + 0x0404, lower_32_bits(src_addr), + 0x0408, upper_32_bits(dst_addr), + 0x040c, lower_32_bits(dst_addr), + 0x0410, PAGE_SIZE, + 0x0414, PAGE_SIZE, + 0x0418, PAGE_SIZE, + 0x041c, npages); + PUSH_NVSQ(push, NVA0B5, 0x0300, launch_dma); return 0; } -- cgit v1.2.3 From 44517aa8d787243dad59c0b55131ae4b6dc100f7 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 19:04:55 +1000 Subject: drm/nouveau/svm: convert migrate_clear to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_dma.h | 8 -------- drivers/gpu/drm/nouveau/nouveau_dmem.c | 28 ++++++++++++---------------- 2 files changed, 12 insertions(+), 24 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nouveau_dmem.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index 8778fd6002c0..32a1f03ec488 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -49,8 +49,6 @@ void nv50_dma_push(struct nouveau_channel *, u64 addr, int length); enum { NvSubSw = 1, NvSubImageBlit = 2, - - NvSubCopy = 4, /* DO NOT CHANGE - hardcoded for kepler gr fifo */ }; /* Object handles - for stuff that's doesn't use handle == oclass. */ @@ -94,12 +92,6 @@ BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size) OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2)); } -static inline void -BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data) -{ - OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2)); -} - #define WRITE_PUT(val) do { \ mb(); \ nouveau_bo_rd32(chan->push.buffer, 0); \ diff --git a/drivers/gpu/drm/nouveau/nouveau_dmem.c b/drivers/gpu/drm/nouveau/nouveau_dmem.c index a70dce4469f2..6528e60e567e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dmem.c +++ b/drivers/gpu/drm/nouveau/nouveau_dmem.c @@ -442,7 +442,7 @@ static int nvc0b5_migrate_clear(struct nouveau_drm *drm, u32 length, enum nouveau_aper dst_aper, u64 dst_addr) { - struct nouveau_channel *chan = drm->dmem->migrate.chan; + struct nvif_push *push = drm->dmem->migrate.chan->chan.push; u32 launch_dma = (1 << 10) /* REMAP_ENABLE_TRUE */ | (1 << 8) /* DST_MEMORY_LAYOUT_PITCH. */ | (1 << 7) /* SRC_MEMORY_LAYOUT_PITCH. */ | @@ -454,33 +454,29 @@ nvc0b5_migrate_clear(struct nouveau_drm *drm, u32 length, (1 << 24) /* NUM_DST_COMPONENTS_TWO */; int ret; - ret = RING_SPACE(chan, 12); + ret = PUSH_WAIT(push, 12); if (ret) return ret; switch (dst_aper) { case NOUVEAU_APER_VRAM: - BEGIN_IMC0(chan, NvSubCopy, 0x0264, 0); - break; + PUSH_NVIM(push, NVA0B5, 0x0264, 0); + break; case NOUVEAU_APER_HOST: - BEGIN_IMC0(chan, NvSubCopy, 0x0264, 1); + PUSH_NVIM(push, NVA0B5, 0x0264, 1); break; default: return -EINVAL; } launch_dma |= 0x00002000; /* DST_TYPE_PHYSICAL. */ - BEGIN_NVC0(chan, NvSubCopy, 0x0700, 3); - OUT_RING(chan, 0); - OUT_RING(chan, 0); - OUT_RING(chan, remap); - BEGIN_NVC0(chan, NvSubCopy, 0x0408, 2); - OUT_RING(chan, upper_32_bits(dst_addr)); - OUT_RING(chan, lower_32_bits(dst_addr)); - BEGIN_NVC0(chan, NvSubCopy, 0x0418, 1); - OUT_RING(chan, length >> 3); - BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); - OUT_RING(chan, launch_dma); + PUSH_NVSQ(push, NVA0B5, 0x0700, 0, + 0x0704, 0, + 0x0708, remap); + PUSH_NVSQ(push, NVA0B5, 0x0408, upper_32_bits(dst_addr), + 0x040c, lower_32_bits(dst_addr)); + PUSH_NVSQ(push, NVA0B5, 0x0418, length >> 3); + PUSH_NVSQ(push, NVA0B5, 0x0300, launch_dma); return 0; } -- cgit v1.2.3 From 66c3bdd4e7fa248c188478e05dbe74ab342732e6 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 19:16:31 +1000 Subject: drm/nouveau/svm: use NVIDIA's headers for migrate_copy() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_dmem.c | 59 ++++++++++++++++++++++------------ 1 file changed, 39 insertions(+), 20 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nouveau_dmem.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_dmem.c b/drivers/gpu/drm/nouveau/nouveau_dmem.c index 6528e60e567e..1943e276a8cf 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dmem.c +++ b/drivers/gpu/drm/nouveau/nouveau_dmem.c @@ -35,6 +35,8 @@ #include #include +#include + #include #include @@ -387,11 +389,7 @@ nvc0b5_migrate_copy(struct nouveau_drm *drm, u64 npages, enum nouveau_aper src_aper, u64 src_addr) { struct nvif_push *push = drm->dmem->migrate.chan->chan.push; - u32 launch_dma = (1 << 9) /* MULTI_LINE_ENABLE. */ | - (1 << 8) /* DST_MEMORY_LAYOUT_PITCH. */ | - (1 << 7) /* SRC_MEMORY_LAYOUT_PITCH. */ | - (1 << 2) /* FLUSH_ENABLE_TRUE. */ | - (2 << 0) /* DATA_TRANSFER_TYPE_NON_PIPELINED. */; + u32 launch_dma = 0; int ret; ret = PUSH_WAIT(push, 13); @@ -401,40 +399,61 @@ nvc0b5_migrate_copy(struct nouveau_drm *drm, u64 npages, if (src_aper != NOUVEAU_APER_VIRT) { switch (src_aper) { case NOUVEAU_APER_VRAM: - PUSH_NVIM(push, NVA0B5, 0x0260, 0); + PUSH_IMMD(push, NVA0B5, SET_SRC_PHYS_MODE, + NVDEF(NVA0B5, SET_SRC_PHYS_MODE, TARGET, LOCAL_FB)); break; case NOUVEAU_APER_HOST: - PUSH_NVIM(push, NVA0B5, 0x0260, 1); + PUSH_IMMD(push, NVA0B5, SET_SRC_PHYS_MODE, + NVDEF(NVA0B5, SET_SRC_PHYS_MODE, TARGET, COHERENT_SYSMEM)); break; default: return -EINVAL; } - launch_dma |= 0x00001000; /* SRC_TYPE_PHYSICAL. */ + + launch_dma |= NVDEF(NVA0B5, LAUNCH_DMA, SRC_TYPE, PHYSICAL); } if (dst_aper != NOUVEAU_APER_VIRT) { switch (dst_aper) { case NOUVEAU_APER_VRAM: - PUSH_NVIM(push, NVA0B5, 0x0264, 0); + PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE, + NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, LOCAL_FB)); break; case NOUVEAU_APER_HOST: - PUSH_NVIM(push, NVA0B5, 0x0264, 1); + PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE, + NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, COHERENT_SYSMEM)); break; default: return -EINVAL; } - launch_dma |= 0x00002000; /* DST_TYPE_PHYSICAL. */ + + launch_dma |= NVDEF(NVA0B5, LAUNCH_DMA, DST_TYPE, PHYSICAL); } - PUSH_NVSQ(push, NVA0B5, 0x0400, upper_32_bits(src_addr), - 0x0404, lower_32_bits(src_addr), - 0x0408, upper_32_bits(dst_addr), - 0x040c, lower_32_bits(dst_addr), - 0x0410, PAGE_SIZE, - 0x0414, PAGE_SIZE, - 0x0418, PAGE_SIZE, - 0x041c, npages); - PUSH_NVSQ(push, NVA0B5, 0x0300, launch_dma); + PUSH_MTHD(push, NVA0B5, OFFSET_IN_UPPER, + NVVAL(NVA0B5, OFFSET_IN_UPPER, UPPER, upper_32_bits(src_addr)), + + OFFSET_IN_LOWER, lower_32_bits(src_addr), + + OFFSET_OUT_UPPER, + NVVAL(NVA0B5, OFFSET_OUT_UPPER, UPPER, upper_32_bits(dst_addr)), + + OFFSET_OUT_LOWER, lower_32_bits(dst_addr), + PITCH_IN, PAGE_SIZE, + PITCH_OUT, PAGE_SIZE, + LINE_LENGTH_IN, PAGE_SIZE, + LINE_COUNT, npages); + + PUSH_MTHD(push, NVA0B5, LAUNCH_DMA, launch_dma | + NVDEF(NVA0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED) | + NVDEF(NVA0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE) | + NVDEF(NVA0B5, LAUNCH_DMA, SEMAPHORE_TYPE, NONE) | + NVDEF(NVA0B5, LAUNCH_DMA, INTERRUPT_TYPE, NONE) | + NVDEF(NVA0B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) | + NVDEF(NVA0B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) | + NVDEF(NVA0B5, LAUNCH_DMA, MULTI_LINE_ENABLE, TRUE) | + NVDEF(NVA0B5, LAUNCH_DMA, REMAP_ENABLE, FALSE) | + NVDEF(NVA0B5, LAUNCH_DMA, BYPASS_L2, USE_PTE_SETTING)); return 0; } -- cgit v1.2.3 From c47fceca2ef3718cee09bbf2941de44b3701c873 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 19:27:00 +1000 Subject: drm/nouveau/svm: use NVIDIA's headers for migrate_clear() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_dmem.c | 54 +++++++++++++++++++++------------- 1 file changed, 34 insertions(+), 20 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nouveau_dmem.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_dmem.c b/drivers/gpu/drm/nouveau/nouveau_dmem.c index 1943e276a8cf..98a1739e01e9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dmem.c +++ b/drivers/gpu/drm/nouveau/nouveau_dmem.c @@ -462,15 +462,7 @@ nvc0b5_migrate_clear(struct nouveau_drm *drm, u32 length, enum nouveau_aper dst_aper, u64 dst_addr) { struct nvif_push *push = drm->dmem->migrate.chan->chan.push; - u32 launch_dma = (1 << 10) /* REMAP_ENABLE_TRUE */ | - (1 << 8) /* DST_MEMORY_LAYOUT_PITCH. */ | - (1 << 7) /* SRC_MEMORY_LAYOUT_PITCH. */ | - (1 << 2) /* FLUSH_ENABLE_TRUE. */ | - (2 << 0) /* DATA_TRANSFER_TYPE_NON_PIPELINED. */; - u32 remap = (4 << 0) /* DST_X_CONST_A */ | - (5 << 4) /* DST_Y_CONST_B */ | - (3 << 16) /* COMPONENT_SIZE_FOUR */ | - (1 << 24) /* NUM_DST_COMPONENTS_TWO */; + u32 launch_dma = 0; int ret; ret = PUSH_WAIT(push, 12); @@ -479,23 +471,45 @@ nvc0b5_migrate_clear(struct nouveau_drm *drm, u32 length, switch (dst_aper) { case NOUVEAU_APER_VRAM: - PUSH_NVIM(push, NVA0B5, 0x0264, 0); + PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE, + NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, LOCAL_FB)); break; case NOUVEAU_APER_HOST: - PUSH_NVIM(push, NVA0B5, 0x0264, 1); + PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE, + NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, COHERENT_SYSMEM)); break; default: return -EINVAL; } - launch_dma |= 0x00002000; /* DST_TYPE_PHYSICAL. */ - - PUSH_NVSQ(push, NVA0B5, 0x0700, 0, - 0x0704, 0, - 0x0708, remap); - PUSH_NVSQ(push, NVA0B5, 0x0408, upper_32_bits(dst_addr), - 0x040c, lower_32_bits(dst_addr)); - PUSH_NVSQ(push, NVA0B5, 0x0418, length >> 3); - PUSH_NVSQ(push, NVA0B5, 0x0300, launch_dma); + + launch_dma |= NVDEF(NVA0B5, LAUNCH_DMA, DST_TYPE, PHYSICAL); + + PUSH_MTHD(push, NVA0B5, SET_REMAP_CONST_A, 0, + SET_REMAP_CONST_B, 0, + + SET_REMAP_COMPONENTS, + NVDEF(NVA0B5, SET_REMAP_COMPONENTS, DST_X, CONST_A) | + NVDEF(NVA0B5, SET_REMAP_COMPONENTS, DST_Y, CONST_B) | + NVDEF(NVA0B5, SET_REMAP_COMPONENTS, COMPONENT_SIZE, FOUR) | + NVDEF(NVA0B5, SET_REMAP_COMPONENTS, NUM_DST_COMPONENTS, TWO)); + + PUSH_MTHD(push, NVA0B5, OFFSET_OUT_UPPER, + NVVAL(NVA0B5, OFFSET_OUT_UPPER, UPPER, upper_32_bits(dst_addr)), + + OFFSET_OUT_LOWER, lower_32_bits(dst_addr)); + + PUSH_MTHD(push, NVA0B5, LINE_LENGTH_IN, length >> 3); + + PUSH_MTHD(push, NVA0B5, LAUNCH_DMA, launch_dma | + NVDEF(NVA0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED) | + NVDEF(NVA0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE) | + NVDEF(NVA0B5, LAUNCH_DMA, SEMAPHORE_TYPE, NONE) | + NVDEF(NVA0B5, LAUNCH_DMA, INTERRUPT_TYPE, NONE) | + NVDEF(NVA0B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) | + NVDEF(NVA0B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) | + NVDEF(NVA0B5, LAUNCH_DMA, MULTI_LINE_ENABLE, FALSE) | + NVDEF(NVA0B5, LAUNCH_DMA, REMAP_ENABLE, TRUE) | + NVDEF(NVA0B5, LAUNCH_DMA, BYPASS_L2, USE_PTE_SETTING)); return 0; } -- cgit v1.2.3