From cfe01a5eba1ff5723f3a47895fb7e9d890edf157 Mon Sep 17 00:00:00 2001 From: Shashank Sharma Date: Tue, 1 Sep 2015 19:41:38 +0530 Subject: drm/i915/bxt: Enable BXT DSI PLL This patch adds new functions for BXT clock and PLL programming. They are: 1. configure_dsi_pll for BXT. This function does the basic math and generates the divider ratio based on requested pixclock, and program clock registers. 2. enable_dsi_pll function. This function programs the calculated clock values on the PLL. 3. intel_enable_dsi_pll Wrapper function to use same code for multiple platforms. It checks the platform and calls appropriate core pll enable function. v2: Fixed Jani's review comments. Macros are adjusted as per convention. v3: Removed a redundant change wrt code comment. Signed-off-by: Shashank Sharma Signed-off-by: Uma Shankar Reviewed-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dsi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/i915/intel_dsi.h') diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h index 42a68593e32a..7f16c686771b 100644 --- a/drivers/gpu/drm/i915/intel_dsi.h +++ b/drivers/gpu/drm/i915/intel_dsi.h @@ -124,7 +124,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) return container_of(encoder, struct intel_dsi, base.base); } -extern void vlv_enable_dsi_pll(struct intel_encoder *encoder); +extern void intel_enable_dsi_pll(struct intel_encoder *encoder); extern void vlv_disable_dsi_pll(struct intel_encoder *encoder); extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp); -- cgit v1.2.3 From fe88fc6828f6471c9eebc511aa15984d055d11c1 Mon Sep 17 00:00:00 2001 From: Shashank Sharma Date: Tue, 1 Sep 2015 19:41:39 +0530 Subject: drm/i915/bxt: Disable DSI PLL for BXT This patch adds two new functions: - disable_dsi_pll. BXT DSI disable sequence and registers are different from previous platforms. - intel_disable_dsi_pll wrapper function to re-use the same code for multiple platforms. It checks platform type and calls appropriate core pll disable function. v2: Fixed Jani's review comments. v3: Rebased on latest drm-nightly branch. Signed-off-by: Shashank Sharma Signed-off-by: Uma Shankar Reviewed-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dsi.c | 2 +- drivers/gpu/drm/i915/intel_dsi.h | 2 +- drivers/gpu/drm/i915/intel_dsi_pll.c | 32 +++++++++++++++++++++++++++++++- 3 files changed, 33 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/i915/intel_dsi.h') diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index f2f819605e5c..50159a99d58a 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -557,7 +557,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) usleep_range(2000, 2500); } - vlv_disable_dsi_pll(encoder); + intel_disable_dsi_pll(encoder); } static void intel_dsi_post_disable(struct intel_encoder *encoder) diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h index 7f16c686771b..5cc46b4131f7 100644 --- a/drivers/gpu/drm/i915/intel_dsi.h +++ b/drivers/gpu/drm/i915/intel_dsi.h @@ -125,7 +125,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) } extern void intel_enable_dsi_pll(struct intel_encoder *encoder); -extern void vlv_disable_dsi_pll(struct intel_encoder *encoder); +extern void intel_disable_dsi_pll(struct intel_encoder *encoder); extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp); struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id); diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index b07483beded0..f335e6cd4431 100644 --- a/drivers/gpu/drm/i915/intel_dsi_pll.c +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c @@ -276,7 +276,7 @@ static void vlv_enable_dsi_pll(struct intel_encoder *encoder) DRM_DEBUG_KMS("DSI PLL locked\n"); } -void vlv_disable_dsi_pll(struct intel_encoder *encoder) +static void vlv_disable_dsi_pll(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; u32 tmp; @@ -293,6 +293,26 @@ void vlv_disable_dsi_pll(struct intel_encoder *encoder) mutex_unlock(&dev_priv->sb_lock); } +static void bxt_disable_dsi_pll(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; + u32 val; + + DRM_DEBUG_KMS("\n"); + + val = I915_READ(BXT_DSI_PLL_ENABLE); + val &= ~BXT_DSI_PLL_DO_ENABLE; + I915_WRITE(BXT_DSI_PLL_ENABLE, val); + + /* + * PLL lock should deassert within 200us. + * Wait up to 1ms before timing out. + */ + if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE) + & BXT_DSI_PLL_LOCKED) == 0, 1)) + DRM_ERROR("Timeout waiting for PLL lock deassertion\n"); +} + static void assert_bpp_mismatch(int pixel_format, int pipe_bpp) { int bpp = dsi_pixel_format_bpp(pixel_format); @@ -456,3 +476,13 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder) else if (IS_BROXTON(dev)) bxt_enable_dsi_pll(encoder); } + +void intel_disable_dsi_pll(struct intel_encoder *encoder) +{ + struct drm_device *dev = encoder->base.dev; + + if (IS_VALLEYVIEW(dev)) + vlv_disable_dsi_pll(encoder); + else if (IS_BROXTON(dev)) + bxt_disable_dsi_pll(encoder); +} -- cgit v1.2.3 From b389a45c6b2f9b310ddf631d23b9e3e045cf747b Mon Sep 17 00:00:00 2001 From: Shashank Sharma Date: Tue, 1 Sep 2015 19:41:44 +0530 Subject: drm/i915/bxt: DSI disable and post-disable This patch contains changes to support DSI disble sequence in BXT. The changes are: 1. BXT specific changes in clear_device_ready function. 2. BXT specific changes in DSI disable and post-disable functions. 3. Add a new function to reset BXT Dphy clock and dividers (bxt_dsi_reset_clocks). 4. Moved some part of the vlv clock reset code, in a new function (vlv_dsi_reset_clocks) maintaining the exact same sequence. 5. Wrapper function to call corresponding reset clock function. v2: Fixed Jani's review comments. v3: Removed the GET_DSI_PORT_CTRL Macro for consistency with earlier implementations as per Jani's suggestion. Signed-off-by: Uma Shankar Signed-off-by: Shashank Sharma Reviewed-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dsi.c | 36 ++++++++++++++++++--------------- drivers/gpu/drm/i915/intel_dsi.h | 2 ++ drivers/gpu/drm/i915/intel_dsi_pll.c | 39 ++++++++++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+), 16 deletions(-) (limited to 'drivers/gpu/drm/i915/intel_dsi.h') diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index b7eae5248f47..505501e808a2 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -417,12 +417,15 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); enum port port; u32 temp; + u32 port_ctrl; for_each_dsi_port(port, intel_dsi->ports) { /* de-assert ip_tg_enable signal */ - temp = I915_READ(MIPI_PORT_CTRL(port)); - I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE); - POSTING_READ(MIPI_PORT_CTRL(port)); + port_ctrl = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) : + MIPI_PORT_CTRL(port); + temp = I915_READ(port_ctrl); + I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); + POSTING_READ(port_ctrl); } } @@ -554,12 +557,7 @@ static void intel_dsi_disable(struct intel_encoder *encoder) /* Panel commands can be sent when clock is in LP11 */ I915_WRITE(MIPI_DEVICE_READY(port), 0x0); - temp = I915_READ(MIPI_CTRL(port)); - temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; - I915_WRITE(MIPI_CTRL(port), temp | - intel_dsi->escape_clk_div << - ESCAPE_CLOCK_DIVIDER_SHIFT); - + intel_dsi_reset_clocks(encoder, port); I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); @@ -578,10 +576,12 @@ static void intel_dsi_disable(struct intel_encoder *encoder) static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) { + struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); enum port port; u32 val; + u32 port_ctrl = 0; DRM_DEBUG_KMS("\n"); for_each_dsi_port(port, intel_dsi->ports) { @@ -598,18 +598,22 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) ULPS_STATE_ENTER); usleep_range(2000, 2500); + if (IS_BROXTON(dev)) + port_ctrl = BXT_MIPI_PORT_CTRL(port); + else if (IS_VALLEYVIEW(dev)) + /* Common bit for both MIPI Port A & MIPI Port C */ + port_ctrl = MIPI_PORT_CTRL(PORT_A); + /* Wait till Clock lanes are in LP-00 state for MIPI Port A * only. MIPI Port C has no similar bit for checking */ - if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT) - == 0x00000), 30)) + if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT) + == 0x00000), 30)) DRM_ERROR("DSI LP not going Low\n"); - /* Disable MIPI PHY transparent latch - * Common bit for both MIPI Port A & MIPI Port C - */ - val = I915_READ(MIPI_PORT_CTRL(PORT_A)); - I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD); + /* Disable MIPI PHY transparent latch */ + val = I915_READ(port_ctrl); + I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); usleep_range(1000, 1500); I915_WRITE(MIPI_DEVICE_READY(port), 0x00); diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h index 5cc46b4131f7..797a61245495 100644 --- a/drivers/gpu/drm/i915/intel_dsi.h +++ b/drivers/gpu/drm/i915/intel_dsi.h @@ -127,6 +127,8 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) extern void intel_enable_dsi_pll(struct intel_encoder *encoder); extern void intel_disable_dsi_pll(struct intel_encoder *encoder); extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp); +extern void intel_dsi_reset_clocks(struct intel_encoder *encoder, + enum port port); struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id); diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index 386336281997..c9a38f4dec2d 100644 --- a/drivers/gpu/drm/i915/intel_dsi_pll.c +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c @@ -384,6 +384,19 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) return pclk; } +void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) +{ + u32 temp; + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + + temp = I915_READ(MIPI_CTRL(port)); + temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; + I915_WRITE(MIPI_CTRL(port), temp | + intel_dsi->escape_clk_div << + ESCAPE_CLOCK_DIVIDER_SHIFT); +} + /* Program BXT Mipi clocks and dividers */ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port) { @@ -528,3 +541,29 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder) else if (IS_BROXTON(dev)) bxt_disable_dsi_pll(encoder); } + +void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) +{ + u32 tmp; + struct drm_device *dev = encoder->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + /* Clear old configurations */ + tmp = I915_READ(BXT_MIPI_CLOCK_CTL); + tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); + tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port)); + tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port)); + tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port)); + I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); + I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); +} + +void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) +{ + struct drm_device *dev = encoder->base.dev; + + if (IS_BROXTON(dev)) + bxt_dsi_reset_clocks(encoder, port); + else if (IS_VALLEYVIEW(dev)) + vlv_dsi_reset_clocks(encoder, port); +} -- cgit v1.2.3 From ce0c982152137789e6f09e9d8712034088adf3aa Mon Sep 17 00:00:00 2001 From: Shashank Sharma Date: Tue, 1 Sep 2015 19:41:46 +0530 Subject: drm/i915/bxt: get DSI pixelclock BXT's DSI PLL is different from that of VLV. So this patch adds a new function to get the current DSI pixel clock based on the PLL divider ratio and lane count. This function is required for intel_dsi_get_config() function. v2: Fixed Jani's review comments. Signed-off-by: Shashank Sharma Signed-off-by: Uma Shankar Reviewed-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dsi.c | 8 ++++++-- drivers/gpu/drm/i915/intel_dsi.h | 1 + drivers/gpu/drm/i915/intel_dsi_pll.c | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 42 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/i915/intel_dsi.h') diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 65911065e654..170ae6f4866e 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -695,7 +695,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, static void intel_dsi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { - u32 pclk; + u32 pclk = 0; DRM_DEBUG_KMS("\n"); /* @@ -704,7 +704,11 @@ static void intel_dsi_get_config(struct intel_encoder *encoder, */ pipe_config->dpll_hw_state.dpll_md = 0; - pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); + if (IS_BROXTON(encoder->base.dev)) + pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp); + else if (IS_VALLEYVIEW(encoder->base.dev)) + pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); + if (!pclk) return; diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h index 797a61245495..e6cb25239941 100644 --- a/drivers/gpu/drm/i915/intel_dsi.h +++ b/drivers/gpu/drm/i915/intel_dsi.h @@ -127,6 +127,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) extern void intel_enable_dsi_pll(struct intel_encoder *encoder); extern void intel_disable_dsi_pll(struct intel_encoder *encoder); extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp); +extern u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp); extern void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port); diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index c9a38f4dec2d..22c1ea9d3748 100644 --- a/drivers/gpu/drm/i915/intel_dsi_pll.c +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c @@ -384,6 +384,41 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) return pclk; } +u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) +{ + u32 pclk; + u32 dsi_clk; + u32 dsi_ratio; + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; + + /* Divide by zero */ + if (!pipe_bpp) { + DRM_ERROR("Invalid BPP(0)\n"); + return 0; + } + + dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) & + BXT_DSI_PLL_RATIO_MASK; + + /* Invalid DSI ratio ? */ + if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || + dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { + DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio); + return 0; + } + + dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2; + + /* pixel_format and pipe_bpp should agree */ + assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); + + pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp); + + DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk); + return pclk; +} + void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) { u32 temp; -- cgit v1.2.3