From f87c46c43175d382f3f1e4d067be529a84c6fb7c Mon Sep 17 00:00:00 2001 From: Vandita Kulkarni Date: Thu, 26 Aug 2021 11:18:10 +0530 Subject: drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband Wa_16012360555 SW will have to program the "LP to HS Wakeup Guardband" field to account for the repeaters on the HS Request/Ready PPI signaling between the Display engine and the DPHY. v2: Fix build issue. v3: Align to new naming (Jani) Signed-off-by: Vandita Kulkarni Reviewed-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20210826054811.10572-2-vandita.kulkarni@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/gpu/drm/i915/i915_reg.h') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a0c8110d4ca0..bd63760207b0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -11628,6 +11628,14 @@ enum skl_power_gate { _ICL_DSI_IO_MODECTL_1) #define COMBO_PHY_MODE_DSI (1 << 0) +/* TGL DSI Chicken register */ +#define _TGL_DSI_CHKN_REG_0 0x6B0C0 +#define _TGL_DSI_CHKN_REG_1 0x6B8C0 +#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port, \ + _TGL_DSI_CHKN_REG_0, \ + _TGL_DSI_CHKN_REG_1) +#define TGL_DSI_CHKN_LSHS_GB REG_GENMASK(15, 12) + /* Display Stream Splitter Control */ #define DSS_CTL1 _MMIO(0x67400) #define SPLITTER_ENABLE (1 << 31) -- cgit v1.2.3