From 86a08f1af2b29c2ffdfb4575f3fa7a9f1c7edbdf Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Fri, 16 Feb 2024 16:30:52 +0800 Subject: Revert "drm/amdgpu: Add pci usage to nbio v7.9" Remove implementation to get pcie usage for nbio v7.9 as pcie usage is handled by fw This reverts commit 59070fd9ccea58c3363d39f69c25fa98c71eb02f. Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_sh_mask.h | 8 -------- 1 file changed, 8 deletions(-) (limited to 'drivers/gpu/drm/amd/include') diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_sh_mask.h index e0c28c29ddb0..a22481e7bcdb 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_sh_mask.h @@ -38896,13 +38896,5 @@ #define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L #define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L -//PCIE_PERF_CNTL_TXCLK3 -#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL__SHIFT 0x0 -#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL_MASK 0x000000FFL - -//PCIE_PERF_CNTL_TXCLK7 -#define PCIE_PERF_CNTL_TXCLK7__EVENT0_SEL__SHIFT 0x0 -#define PCIE_PERF_CNTL_TXCLK7__EVENT0_SEL_MASK 0x000000FFL - #endif -- cgit v1.2.3 From 47136be6381c1c28b9e33b14849c9d1c7ec5e92e Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Mon, 29 Jan 2024 17:20:53 -0500 Subject: drm/amd: Update atomfirmware.h for DCN401 Add new firmware header definitions reqiured for DCN401 Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/atomfirmware.h | 32 ++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'drivers/gpu/drm/amd/include') diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index fa7d6ced786f..af3eebb4c9bc 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -610,6 +610,38 @@ struct atom_firmware_info_v3_4 { uint32_t reserved[2]; }; +struct atom_firmware_info_v3_5 { + struct atom_common_table_header table_header; + uint32_t firmware_revision; + uint32_t bootup_clk_reserved[2]; + uint32_t firmware_capability; // enum atombios_firmware_capability + uint32_t fw_protect_region_size_in_kb; /* FW allocate a write protect region at top of FB. */ + uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address + uint32_t bootup_voltage_reserved[2]; + uint8_t mem_module_id; + uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ + uint8_t hw_blt_mode; //0:HW_BLT_DMA_PIO_MODE; 1:HW_BLT_LITE_SDMA_MODE; 2:HW_BLT_PCI_IO_MODE + uint8_t reserved1; + uint32_t mc_baseaddr_high; + uint32_t mc_baseaddr_low; + uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def + uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id + uint8_t board_i2c_feature_slave_addr; + uint8_t ras_rom_i2c_slave_addr; + uint32_t bootup_voltage_reserved1; + uint32_t zfb_reserved; + // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS + uint32_t pplib_pptable_id; + uint32_t hw_voltage_reserved[3]; + uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt + uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt + uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb. + uint32_t pspbl_init_reserved[3]; + uint32_t spi_rom_size; // GPU spi rom size + uint16_t support_dev_in_objinfo; + uint16_t disp_phy_tunning_size; + uint32_t reserved[16]; +}; /* *************************************************************************** Data Table lcd_info structure -- cgit v1.2.3