From d51ac6d0a23caf1005cb640f8533161c5d2dd0c0 Mon Sep 17 00:00:00 2001 From: Le Ma Date: Tue, 24 May 2022 11:22:49 +0800 Subject: drm/amdgpu: add xcc index argument to select_sh_se function v2 v1: To support multiple XCD case (Le) v2: introduce xcc index to gfx_v11_0_select_sh_se (Hawking) Signed-off-by: Le Ma Reviewed-by: Hawking Zhang Signed-off-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/amdgpu/vi.c') diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 531f173ade2d..8e70581960fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -762,12 +762,12 @@ static uint32_t vi_get_register_value(struct amdgpu_device *adev, mutex_lock(&adev->grbm_idx_mutex); if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); + amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); val = RREG32(reg_offset); if (se_num != 0xffffffff || sh_num != 0xffffffff) - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); mutex_unlock(&adev->grbm_idx_mutex); return val; } else { -- cgit v1.2.3 From 20a29ac09192f9d9705015261652f277e8162f09 Mon Sep 17 00:00:00 2001 From: Likun Gao Date: Fri, 19 May 2023 18:54:18 +0800 Subject: drm/amdgpu: retire set_vga_state for some ASIC set_vga_state operation only allowed on SI generation ASIC, retire the realted function on those ASIC which did not do anything. Signed-off-by: Likun Gao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nv.c | 6 ------ drivers/gpu/drm/amd/amdgpu/soc15.c | 8 -------- drivers/gpu/drm/amd/amdgpu/soc21.c | 6 ------ drivers/gpu/drm/amd/amdgpu/vi.c | 6 ------ 4 files changed, 26 deletions(-) (limited to 'drivers/gpu/drm/amd/amdgpu/vi.c') diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index a5f76c9538c4..51523b27a186 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -341,11 +341,6 @@ void nv_grbm_select(struct amdgpu_device *adev, WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); } -static void nv_vga_set_state(struct amdgpu_device *adev, bool state) -{ - /* todo */ -} - static bool nv_read_disabled_bios(struct amdgpu_device *adev) { /* todo */ @@ -654,7 +649,6 @@ static const struct amdgpu_asic_funcs nv_asic_funcs = .read_register = &nv_read_register, .reset = &nv_asic_reset, .reset_method = &nv_asic_reset_method, - .set_vga_state = &nv_vga_set_state, .get_xclk = &nv_get_xclk, .set_uvd_clocks = &nv_set_uvd_clocks, .set_vce_clocks = &nv_set_vce_clocks, diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 122ba1a505c3..135440b5afe9 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -346,11 +346,6 @@ void soc15_grbm_select(struct amdgpu_device *adev, WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl); } -static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) -{ - /* todo */ -} - static bool soc15_read_disabled_bios(struct amdgpu_device *adev) { /* todo */ @@ -849,7 +844,6 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs = .read_register = &soc15_read_register, .reset = &soc15_asic_reset, .reset_method = &soc15_asic_reset_method, - .set_vga_state = &soc15_vga_set_state, .get_xclk = &soc15_get_xclk, .set_uvd_clocks = &soc15_set_uvd_clocks, .set_vce_clocks = &soc15_set_vce_clocks, @@ -871,7 +865,6 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs = .read_register = &soc15_read_register, .reset = &soc15_asic_reset, .reset_method = &soc15_asic_reset_method, - .set_vga_state = &soc15_vga_set_state, .get_xclk = &soc15_get_xclk, .set_uvd_clocks = &soc15_set_uvd_clocks, .set_vce_clocks = &soc15_set_vce_clocks, @@ -893,7 +886,6 @@ static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs = .read_register = &soc15_read_register, .reset = &soc15_asic_reset, .reset_method = &soc15_asic_reset_method, - .set_vga_state = &soc15_vga_set_state, .get_xclk = &soc15_get_xclk, .set_uvd_clocks = &soc15_set_uvd_clocks, .set_vce_clocks = &soc15_set_vce_clocks, diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 6bff936a6e55..e5e5d68a4d70 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -248,11 +248,6 @@ void soc21_grbm_select(struct amdgpu_device *adev, WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl); } -static void soc21_vga_set_state(struct amdgpu_device *adev, bool state) -{ - /* todo */ -} - static bool soc21_read_disabled_bios(struct amdgpu_device *adev) { /* todo */ @@ -559,7 +554,6 @@ static const struct amdgpu_asic_funcs soc21_asic_funcs = .read_register = &soc21_read_register, .reset = &soc21_asic_reset, .reset_method = &soc21_asic_reset_method, - .set_vga_state = &soc21_vga_set_state, .get_xclk = &soc21_get_xclk, .set_uvd_clocks = &soc21_set_uvd_clocks, .set_vce_clocks = &soc21_set_vce_clocks, diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 8e70581960fb..770f2d7a371f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -580,11 +580,6 @@ void vi_srbm_select(struct amdgpu_device *adev, WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl); } -static void vi_vga_set_state(struct amdgpu_device *adev, bool state) -{ - /* todo */ -} - static bool vi_read_disabled_bios(struct amdgpu_device *adev) { u32 bus_cntl; @@ -1435,7 +1430,6 @@ static const struct amdgpu_asic_funcs vi_asic_funcs = .read_register = &vi_read_register, .reset = &vi_asic_reset, .reset_method = &vi_asic_reset_method, - .set_vga_state = &vi_vga_set_state, .get_xclk = &vi_get_xclk, .set_uvd_clocks = &vi_set_uvd_clocks, .set_vce_clocks = &vi_set_vce_clocks, -- cgit v1.2.3 From 5a863904bab4f5d22012f7d68ab2becafc303a40 Mon Sep 17 00:00:00 2001 From: Chia-I Wu Date: Thu, 1 Jun 2023 14:48:08 -0700 Subject: drm/amdgpu: fix xclk freq on CHIP_STONEY According to Alex, most APUs from that time seem to have the same issue (vbios says 48Mhz, actual is 100Mhz). I only have a CHIP_STONEY so I limit the fixup to CHIP_STONEY Signed-off-by: Chia-I Wu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vi.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/amdgpu/vi.c') diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 770f2d7a371f..6a8494f98d3e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -542,8 +542,15 @@ static u32 vi_get_xclk(struct amdgpu_device *adev) u32 reference_clock = adev->clock.spll.reference_freq; u32 tmp; - if (adev->flags & AMD_IS_APU) - return reference_clock; + if (adev->flags & AMD_IS_APU) { + switch (adev->asic_type) { + case CHIP_STONEY: + /* vbios says 48Mhz, but the actual freq is 100Mhz */ + return 10000; + default: + return reference_clock; + } + } tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK)) -- cgit v1.2.3