From 5c992afcf8e4f91fac05d39b86c7f7922a50145c Mon Sep 17 00:00:00 2001 From: Andrew Bresticker Date: Wed, 14 May 2014 17:32:59 -0700 Subject: clk: tegra: Fix xusb_hs_src clock hierarchy Currently the Tegra1x4 clock init code hard-codes the mux setting for xusb_hs_src and treats it as a fixed-factor clock. It is, however, a mux which can be parented by either xusb_ss_src/2 or pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an entry in periph_clks[] for the xusb_hs_src mux. Signed-off-by: Andrew Bresticker Signed-off-by: Mike Turquette --- drivers/clk/tegra/clk-id.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/tegra/clk-id.h') diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h index c39613c519af..0011d547a9f7 100644 --- a/drivers/clk/tegra/clk-id.h +++ b/drivers/clk/tegra/clk-id.h @@ -233,6 +233,7 @@ enum clk_id { tegra_clk_xusb_hs_src, tegra_clk_xusb_ss, tegra_clk_xusb_ss_src, + tegra_clk_xusb_ss_div2, tegra_clk_max, }; -- cgit v1.2.3