From e86ffc4199c6004274cb4a169c7f84cc489532d4 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Thu, 19 Dec 2013 14:03:39 +0530 Subject: clk: exynos5250: Add CLK_SET_RATE_PARENT flag to mout_apll Add CLK_SET_RATE_PARENT flag to mout_apll clock. This will let us set the clock rate in the cpufreq driver. Signed-off-by: Sachin Kamat Acked-by: Mike Turquette Signed-off-by: Tomasz Figa --- drivers/clk/samsung/clk-exynos5250.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/clk/samsung') diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index d54f4212d4e9..cbbe423d4e2b 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -262,7 +262,8 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { /* * CMU_CPU */ - MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"), + MUX_FA(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + CLK_SET_RATE_PARENT, 0, "mout_apll"), MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), /* -- cgit v1.2.3