From b3244351e2b39bd49aba780ea204f0f2a45a4725 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Tue, 23 Jan 2024 15:21:10 -0600 Subject: clk: rockchip: rk3568: Add PLL rate for 128MHz Add PLL rate for 128MHz to allow the panel for the Anbernic RG-ARC series to run at 60hz. Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20240123212111.202146-4-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk-rk3568.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/rockchip/clk-rk3568.c') diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index b786ddc9af2a..8cb21d10beca 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -78,6 +78,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0), + RK3036_PLL_RATE(128000000, 1, 16, 3, 1, 1, 0), RK3036_PLL_RATE(126400000, 1, 79, 5, 3, 1, 0), RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0), RK3036_PLL_RATE(115200000, 1, 24, 5, 1, 1, 0), -- cgit v1.2.3